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.gitignore
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d51bbe5ae2
Add FPGA PHY source code
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%!s(int64=5) %!d(string=hai) anos |
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Makefile
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9280b86c0e
phy-fpha: Use PLL
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%!s(int64=5) %!d(string=hai) anos |
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block_ram_mod.v
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d51bbe5ae2
Add FPGA PHY source code
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%!s(int64=5) %!d(string=hai) anos |
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crcgen.py
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582596891f
crcgen: Move all tests to test module
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%!s(int64=5) %!d(string=hai) anos |
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crcgen_test.py
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aaeac12a95
crcgen: Run tests in parallel
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%!s(int64=5) %!d(string=hai) anos |
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edge_detect_mod.v
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d51bbe5ae2
Add FPGA PHY source code
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%!s(int64=5) %!d(string=hai) anos |
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led_blink_mod.v
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e7254d162d
fpga: Add LED blinker
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%!s(int64=5) %!d(string=hai) anos |
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main.v
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b8098b9b5a
phy-fpha: Declare miso as inout
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%!s(int64=5) %!d(string=hai) anos |
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parity_func.v
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d51bbe5ae2
Add FPGA PHY source code
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%!s(int64=5) %!d(string=hai) anos |
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profibus_phy_mod.v
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46bfec6f56
phy-fpga: Set CRC error flag
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%!s(int64=5) %!d(string=hai) anos |
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spi_slave_mod.v
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4b4d67b430
fpga: re-arrange pins
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%!s(int64=5) %!d(string=hai) anos |
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sync_signal_mod.v
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d51bbe5ae2
Add FPGA PHY source code
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%!s(int64=5) %!d(string=hai) anos |
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tinyfpga_bx.pcf
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d51bbe5ae2
Add FPGA PHY source code
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%!s(int64=5) %!d(string=hai) anos |
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uart_mod.v
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fb07d30621
uart: Limit sym timer
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%!s(int64=5) %!d(string=hai) anos |
Michael Buesch
b8098b9b5a
phy-fpha: Declare miso as inout