rama982/kernel_xiaomi_lancelot

Autor	SHA1 Wiadomość	Data
Ard Biesheuvel	0bcbfa51a7 drm: disable uncached DMA optimization for ARM and arm64	6 lat temu
Gabriel Krisman Bertazi	f9a87bd7d5 drm: Move drm_clflush prototypes to drm_cache header file	8 lat temu
Huacai Chen	221004c66a drm: Loongson-3 doesn't fully support wc memory	8 lat temu
Dave Airlie	4b0e4e4af6 drm: add helper to check for wc memory support	9 lat temu
Dave Airlie	c9c97b8c75 drm/ttm: consolidate cache flushing code in one place.	15 lat temu