Commit History

Autor SHA1 Mensaxe Data
  Ard Biesheuvel 0bcbfa51a7 drm: disable uncached DMA optimization for ARM and arm64 %!s(int64=5) %!d(string=hai) anos
  Gabriel Krisman Bertazi f9a87bd7d5 drm: Move drm_clflush prototypes to drm_cache header file %!s(int64=8) %!d(string=hai) anos
  Huacai Chen 221004c66a drm: Loongson-3 doesn't fully support wc memory %!s(int64=8) %!d(string=hai) anos
  Dave Airlie 4b0e4e4af6 drm: add helper to check for wc memory support %!s(int64=8) %!d(string=hai) anos
  Dave Airlie c9c97b8c75 drm/ttm: consolidate cache flushing code in one place. %!s(int64=15) %!d(string=hai) anos