 Michael Buesch
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3704f691c9
Fix incorrect MyHDL 'next' use
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il y a 1 an |
|
Michael Buesch
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b233945422
Remove unnecessary parenthesis
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il y a 1 an |
|
Michael Buesch
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7043d19067
Use private fields in bit classes
|
il y a 1 an |
|
Michael Buesch
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b4e298793c
Remove old py2 compat oldstyle class
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il y a 1 an |
|
Michael Buesch
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c4d3eeac29
Update copyright
|
il y a 1 an |
|
Michael Buesch
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9449b48ab1
Remove unnecessary parenthesis
|
il y a 1 an |
|
Michael Buesch
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d5fc1a9dca
Move polynomial parser to utils
|
il y a 1 an |
|
Michael Buesch
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3f6aa6e431
Stricter polynomial parsing
|
il y a 1 an |
|
Michael Buesch
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6ab9b404c2
Fix polynomial coefficient conversion for small bit size
|
il y a 1 an |
|
Michael Buesch
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7e1173cb19
Keep local ref to P
|
il y a 2 ans |
|
Michael Buesch
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91fafc4a55
Move test code to own file and don't import in normal runs
|
il y a 2 ans |
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Michael Buesch
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4f2a2f648c
Unify indentation among all supported languages
|
il y a 3 ans |
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Michael Buesch
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b420326d54
Don't generate trailing comma in Verilog module parameter list
|
il y a 3 ans |
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Michael Buesch
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d4496951ff
Rename main module to libcrcgen
|
il y a 3 ans |
