evergreen_blit_shaders.c 7.7 KB

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  1. /*
  2. * Copyright 2010 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Alex Deucher <alexander.deucher@amd.com>
  25. */
  26. #include <linux/types.h>
  27. #include <linux/kernel.h>
  28. /*
  29. * evergreen cards need to use the 3D engine to blit data which requires
  30. * quite a bit of hw state setup. Rather than pull the whole 3D driver
  31. * (which normally generates the 3D state) into the DRM, we opt to use
  32. * statically generated state tables. The regsiter state and shaders
  33. * were hand generated to support blitting functionality. See the 3D
  34. * driver or documentation for descriptions of the registers and
  35. * shader instructions.
  36. */
  37. const u32 evergreen_default_state[] =
  38. {
  39. 0xc0016900,
  40. 0x0000023b,
  41. 0x00000000, /* SQ_LDS_ALLOC_PS */
  42. 0xc0066900,
  43. 0x00000240,
  44. 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
  45. 0x00000000,
  46. 0x00000000,
  47. 0x00000000,
  48. 0x00000000,
  49. 0x00000000,
  50. 0xc0046900,
  51. 0x00000247,
  52. 0x00000000, /* SQ_GS_VERT_ITEMSIZE */
  53. 0x00000000,
  54. 0x00000000,
  55. 0x00000000,
  56. 0xc0026900,
  57. 0x00000010,
  58. 0x00000000, /* DB_Z_INFO */
  59. 0x00000000, /* DB_STENCIL_INFO */
  60. 0xc0016900,
  61. 0x00000200,
  62. 0x00000000, /* DB_DEPTH_CONTROL */
  63. 0xc0066900,
  64. 0x00000000,
  65. 0x00000060, /* DB_RENDER_CONTROL */
  66. 0x00000000, /* DB_COUNT_CONTROL */
  67. 0x00000000, /* DB_DEPTH_VIEW */
  68. 0x0000002a, /* DB_RENDER_OVERRIDE */
  69. 0x00000000, /* DB_RENDER_OVERRIDE2 */
  70. 0x00000000, /* DB_HTILE_DATA_BASE */
  71. 0xc0026900,
  72. 0x0000000a,
  73. 0x00000000, /* DB_STENCIL_CLEAR */
  74. 0x00000000, /* DB_DEPTH_CLEAR */
  75. 0xc0016900,
  76. 0x000002dc,
  77. 0x0000aa00, /* DB_ALPHA_TO_MASK */
  78. 0xc0016900,
  79. 0x00000080,
  80. 0x00000000, /* PA_SC_WINDOW_OFFSET */
  81. 0xc00d6900,
  82. 0x00000083,
  83. 0x0000ffff, /* PA_SC_CLIPRECT_RULE */
  84. 0x00000000, /* PA_SC_CLIPRECT_0_TL */
  85. 0x20002000, /* PA_SC_CLIPRECT_0_BR */
  86. 0x00000000,
  87. 0x20002000,
  88. 0x00000000,
  89. 0x20002000,
  90. 0x00000000,
  91. 0x20002000,
  92. 0xaaaaaaaa, /* PA_SC_EDGERULE */
  93. 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
  94. 0x0000000f, /* CB_TARGET_MASK */
  95. 0x0000000f, /* CB_SHADER_MASK */
  96. 0xc0226900,
  97. 0x00000094,
  98. 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
  99. 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
  100. 0x80000000,
  101. 0x20002000,
  102. 0x80000000,
  103. 0x20002000,
  104. 0x80000000,
  105. 0x20002000,
  106. 0x80000000,
  107. 0x20002000,
  108. 0x80000000,
  109. 0x20002000,
  110. 0x80000000,
  111. 0x20002000,
  112. 0x80000000,
  113. 0x20002000,
  114. 0x80000000,
  115. 0x20002000,
  116. 0x80000000,
  117. 0x20002000,
  118. 0x80000000,
  119. 0x20002000,
  120. 0x80000000,
  121. 0x20002000,
  122. 0x80000000,
  123. 0x20002000,
  124. 0x80000000,
  125. 0x20002000,
  126. 0x80000000,
  127. 0x20002000,
  128. 0x80000000,
  129. 0x20002000,
  130. 0x00000000, /* PA_SC_VPORT_ZMIN_0 */
  131. 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
  132. 0xc0016900,
  133. 0x000000d4,
  134. 0x00000000, /* SX_MISC */
  135. 0xc0026900,
  136. 0x00000292,
  137. 0x00000000, /* PA_SC_MODE_CNTL_0 */
  138. 0x00000000, /* PA_SC_MODE_CNTL_1 */
  139. 0xc0106900,
  140. 0x00000300,
  141. 0x00000000, /* PA_SC_LINE_CNTL */
  142. 0x00000000, /* PA_SC_AA_CONFIG */
  143. 0x00000005, /* PA_SU_VTX_CNTL */
  144. 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
  145. 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
  146. 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
  147. 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
  148. 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_0 */
  149. 0x00000000, /* */
  150. 0x00000000, /* */
  151. 0x00000000, /* */
  152. 0x00000000, /* */
  153. 0x00000000, /* */
  154. 0x00000000, /* */
  155. 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_7 */
  156. 0xffffffff, /* PA_SC_AA_MASK */
  157. 0xc00d6900,
  158. 0x00000202,
  159. 0x00cc0010, /* CB_COLOR_CONTROL */
  160. 0x00000210, /* DB_SHADER_CONTROL */
  161. 0x00010000, /* PA_CL_CLIP_CNTL */
  162. 0x00000004, /* PA_SU_SC_MODE_CNTL */
  163. 0x00000100, /* PA_CL_VTE_CNTL */
  164. 0x00000000, /* PA_CL_VS_OUT_CNTL */
  165. 0x00000000, /* PA_CL_NANINF_CNTL */
  166. 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
  167. 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
  168. 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
  169. 0x00000000, /* */
  170. 0x00000000, /* */
  171. 0x00000000, /* SQ_DYN_GPR_RESOURCE_LIMIT_1 */
  172. 0xc0066900,
  173. 0x000002de,
  174. 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
  175. 0x00000000, /* */
  176. 0x00000000, /* */
  177. 0x00000000, /* */
  178. 0x00000000, /* */
  179. 0x00000000, /* */
  180. 0xc0016900,
  181. 0x00000229,
  182. 0x00000000, /* SQ_PGM_START_FS */
  183. 0xc0016900,
  184. 0x0000022a,
  185. 0x00000000, /* SQ_PGM_RESOURCES_FS */
  186. 0xc0096900,
  187. 0x00000100,
  188. 0x00ffffff, /* VGT_MAX_VTX_INDX */
  189. 0x00000000, /* */
  190. 0x00000000, /* */
  191. 0x00000000, /* */
  192. 0x00000000, /* SX_ALPHA_TEST_CONTROL */
  193. 0x00000000, /* CB_BLEND_RED */
  194. 0x00000000, /* CB_BLEND_GREEN */
  195. 0x00000000, /* CB_BLEND_BLUE */
  196. 0x00000000, /* CB_BLEND_ALPHA */
  197. 0xc0026900,
  198. 0x000002a8,
  199. 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
  200. 0x00000000, /* */
  201. 0xc0026900,
  202. 0x000002ad,
  203. 0x00000000, /* VGT_REUSE_OFF */
  204. 0x00000000, /* */
  205. 0xc0116900,
  206. 0x00000280,
  207. 0x00000000, /* PA_SU_POINT_SIZE */
  208. 0x00000000, /* PA_SU_POINT_MINMAX */
  209. 0x00000008, /* PA_SU_LINE_CNTL */
  210. 0x00000000, /* PA_SC_LINE_STIPPLE */
  211. 0x00000000, /* VGT_OUTPUT_PATH_CNTL */
  212. 0x00000000, /* VGT_HOS_CNTL */
  213. 0x00000000, /* */
  214. 0x00000000, /* */
  215. 0x00000000, /* */
  216. 0x00000000, /* */
  217. 0x00000000, /* */
  218. 0x00000000, /* */
  219. 0x00000000, /* */
  220. 0x00000000, /* */
  221. 0x00000000, /* */
  222. 0x00000000, /* */
  223. 0x00000000, /* VGT_GS_MODE */
  224. 0xc0016900,
  225. 0x000002a1,
  226. 0x00000000, /* VGT_PRIMITIVEID_EN */
  227. 0xc0016900,
  228. 0x000002a5,
  229. 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
  230. 0xc0016900,
  231. 0x000002d5,
  232. 0x00000000, /* VGT_SHADER_STAGES_EN */
  233. 0xc0026900,
  234. 0x000002e5,
  235. 0x00000000, /* VGT_STRMOUT_CONFIG */
  236. 0x00000000, /* */
  237. 0xc0016900,
  238. 0x000001e0,
  239. 0x00000000, /* CB_BLEND0_CONTROL */
  240. 0xc0016900,
  241. 0x000001b1,
  242. 0x00000000, /* SPI_VS_OUT_CONFIG */
  243. 0xc0016900,
  244. 0x00000187,
  245. 0x00000000, /* SPI_VS_OUT_ID_0 */
  246. 0xc0016900,
  247. 0x00000191,
  248. 0x00000100, /* SPI_PS_INPUT_CNTL_0 */
  249. 0xc00b6900,
  250. 0x000001b3,
  251. 0x20000001, /* SPI_PS_IN_CONTROL_0 */
  252. 0x00000000, /* SPI_PS_IN_CONTROL_1 */
  253. 0x00000000, /* SPI_INTERP_CONTROL_0 */
  254. 0x00000000, /* SPI_INPUT_Z */
  255. 0x00000000, /* SPI_FOG_CNTL */
  256. 0x00100000, /* SPI_BARYC_CNTL */
  257. 0x00000000, /* SPI_PS_IN_CONTROL_2 */
  258. 0x00000000, /* */
  259. 0x00000000, /* */
  260. 0x00000000, /* */
  261. 0x00000000, /* */
  262. 0xc0026900,
  263. 0x00000316,
  264. 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
  265. 0x00000010, /* */
  266. };
  267. const u32 evergreen_vs[] =
  268. {
  269. 0x00000004,
  270. 0x80800400,
  271. 0x0000a03c,
  272. 0x95000688,
  273. 0x00004000,
  274. 0x15200688,
  275. 0x00000000,
  276. 0x00000000,
  277. 0x3c000000,
  278. 0x67961001,
  279. #ifdef __BIG_ENDIAN
  280. 0x000a0000,
  281. #else
  282. 0x00080000,
  283. #endif
  284. 0x00000000,
  285. 0x1c000000,
  286. 0x67961000,
  287. #ifdef __BIG_ENDIAN
  288. 0x00020008,
  289. #else
  290. 0x00000008,
  291. #endif
  292. 0x00000000,
  293. };
  294. const u32 evergreen_ps[] =
  295. {
  296. 0x00000003,
  297. 0xa00c0000,
  298. 0x00000008,
  299. 0x80400000,
  300. 0x00000000,
  301. 0x95200688,
  302. 0x00380400,
  303. 0x00146b10,
  304. 0x00380000,
  305. 0x20146b10,
  306. 0x00380400,
  307. 0x40146b00,
  308. 0x80380000,
  309. 0x60146b00,
  310. 0x00000000,
  311. 0x00000000,
  312. 0x00000010,
  313. 0x000d1000,
  314. 0xb0800000,
  315. 0x00000000,
  316. };
  317. const u32 evergreen_ps_size = ARRAY_SIZE(evergreen_ps);
  318. const u32 evergreen_vs_size = ARRAY_SIZE(evergreen_vs);
  319. const u32 evergreen_default_size = ARRAY_SIZE(evergreen_default_state);