pwm-sti.c 17 KB

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  1. /*
  2. * PWM device driver for ST SoCs
  3. *
  4. * Copyright (C) 2013-2016 STMicroelectronics (R&D) Limited
  5. *
  6. * Author: Ajit Pal Singh <ajitpal.singh@st.com>
  7. * Lee Jones <lee.jones@linaro.org>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. */
  14. #include <linux/clk.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/math64.h>
  17. #include <linux/mfd/syscon.h>
  18. #include <linux/module.h>
  19. #include <linux/of.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/pwm.h>
  22. #include <linux/regmap.h>
  23. #include <linux/sched.h>
  24. #include <linux/slab.h>
  25. #include <linux/time.h>
  26. #include <linux/wait.h>
  27. #define PWM_OUT_VAL(x) (0x00 + (4 * (x))) /* Device's Duty Cycle register */
  28. #define PWM_CPT_VAL(x) (0x10 + (4 * (x))) /* Capture value */
  29. #define PWM_CPT_EDGE(x) (0x30 + (4 * (x))) /* Edge to capture on */
  30. #define STI_PWM_CTRL 0x50 /* Control/Config register */
  31. #define STI_INT_EN 0x54 /* Interrupt Enable/Disable register */
  32. #define STI_INT_STA 0x58 /* Interrupt Status register */
  33. #define PWM_INT_ACK 0x5c
  34. #define PWM_PRESCALE_LOW_MASK 0x0f
  35. #define PWM_PRESCALE_HIGH_MASK 0xf0
  36. #define PWM_CPT_EDGE_MASK 0x03
  37. #define PWM_INT_ACK_MASK 0x1ff
  38. #define STI_MAX_CPT_DEVS 4
  39. #define CPT_DC_MAX 0xff
  40. /* Regfield IDs */
  41. enum {
  42. /* Bits in PWM_CTRL*/
  43. PWMCLK_PRESCALE_LOW,
  44. PWMCLK_PRESCALE_HIGH,
  45. CPTCLK_PRESCALE,
  46. PWM_OUT_EN,
  47. PWM_CPT_EN,
  48. PWM_CPT_INT_EN,
  49. PWM_CPT_INT_STAT,
  50. /* Keep last */
  51. MAX_REGFIELDS
  52. };
  53. /*
  54. * Each capture input can be programmed to detect rising-edge, falling-edge,
  55. * either edge or neither egde.
  56. */
  57. enum sti_cpt_edge {
  58. CPT_EDGE_DISABLED,
  59. CPT_EDGE_RISING,
  60. CPT_EDGE_FALLING,
  61. CPT_EDGE_BOTH,
  62. };
  63. struct sti_cpt_ddata {
  64. u32 snapshot[3];
  65. unsigned int index;
  66. struct mutex lock;
  67. wait_queue_head_t wait;
  68. };
  69. struct sti_pwm_compat_data {
  70. const struct reg_field *reg_fields;
  71. unsigned int pwm_num_devs;
  72. unsigned int cpt_num_devs;
  73. unsigned int max_pwm_cnt;
  74. unsigned int max_prescale;
  75. };
  76. struct sti_pwm_chip {
  77. struct device *dev;
  78. struct clk *pwm_clk;
  79. struct clk *cpt_clk;
  80. struct regmap *regmap;
  81. struct sti_pwm_compat_data *cdata;
  82. struct regmap_field *prescale_low;
  83. struct regmap_field *prescale_high;
  84. struct regmap_field *pwm_out_en;
  85. struct regmap_field *pwm_cpt_en;
  86. struct regmap_field *pwm_cpt_int_en;
  87. struct regmap_field *pwm_cpt_int_stat;
  88. struct pwm_chip chip;
  89. struct pwm_device *cur;
  90. unsigned long configured;
  91. unsigned int en_count;
  92. struct mutex sti_pwm_lock; /* To sync between enable/disable calls */
  93. void __iomem *mmio;
  94. };
  95. static const struct reg_field sti_pwm_regfields[MAX_REGFIELDS] = {
  96. [PWMCLK_PRESCALE_LOW] = REG_FIELD(STI_PWM_CTRL, 0, 3),
  97. [PWMCLK_PRESCALE_HIGH] = REG_FIELD(STI_PWM_CTRL, 11, 14),
  98. [CPTCLK_PRESCALE] = REG_FIELD(STI_PWM_CTRL, 4, 8),
  99. [PWM_OUT_EN] = REG_FIELD(STI_PWM_CTRL, 9, 9),
  100. [PWM_CPT_EN] = REG_FIELD(STI_PWM_CTRL, 10, 10),
  101. [PWM_CPT_INT_EN] = REG_FIELD(STI_INT_EN, 1, 4),
  102. [PWM_CPT_INT_STAT] = REG_FIELD(STI_INT_STA, 1, 4),
  103. };
  104. static inline struct sti_pwm_chip *to_sti_pwmchip(struct pwm_chip *chip)
  105. {
  106. return container_of(chip, struct sti_pwm_chip, chip);
  107. }
  108. /*
  109. * Calculate the prescaler value corresponding to the period.
  110. */
  111. static int sti_pwm_get_prescale(struct sti_pwm_chip *pc, unsigned long period,
  112. unsigned int *prescale)
  113. {
  114. struct sti_pwm_compat_data *cdata = pc->cdata;
  115. unsigned long clk_rate;
  116. unsigned long value;
  117. unsigned int ps;
  118. clk_rate = clk_get_rate(pc->pwm_clk);
  119. if (!clk_rate) {
  120. dev_err(pc->dev, "failed to get clock rate\n");
  121. return -EINVAL;
  122. }
  123. /*
  124. * prescale = ((period_ns * clk_rate) / (10^9 * (max_pwm_cnt + 1)) - 1
  125. */
  126. value = NSEC_PER_SEC / clk_rate;
  127. value *= cdata->max_pwm_cnt + 1;
  128. if (period % value)
  129. return -EINVAL;
  130. ps = period / value - 1;
  131. if (ps > cdata->max_prescale)
  132. return -EINVAL;
  133. *prescale = ps;
  134. return 0;
  135. }
  136. /*
  137. * For STiH4xx PWM IP, the PWM period is fixed to 256 local clock cycles. The
  138. * only way to change the period (apart from changing the PWM input clock) is
  139. * to change the PWM clock prescaler.
  140. *
  141. * The prescaler is of 8 bits, so 256 prescaler values and hence 256 possible
  142. * period values are supported (for a particular clock rate). The requested
  143. * period will be applied only if it matches one of these 256 values.
  144. */
  145. static int sti_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  146. int duty_ns, int period_ns)
  147. {
  148. struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
  149. struct sti_pwm_compat_data *cdata = pc->cdata;
  150. unsigned int ncfg, value, prescale = 0;
  151. struct pwm_device *cur = pc->cur;
  152. struct device *dev = pc->dev;
  153. bool period_same = false;
  154. int ret;
  155. ncfg = hweight_long(pc->configured);
  156. if (ncfg)
  157. period_same = (period_ns == pwm_get_period(cur));
  158. /*
  159. * Allow configuration changes if one of the following conditions
  160. * satisfy.
  161. * 1. No devices have been configured.
  162. * 2. Only one device has been configured and the new request is for
  163. * the same device.
  164. * 3. Only one device has been configured and the new request is for
  165. * a new device and period of the new device is same as the current
  166. * configured period.
  167. * 4. More than one devices are configured and period of the new
  168. * requestis the same as the current period.
  169. */
  170. if (!ncfg ||
  171. ((ncfg == 1) && (pwm->hwpwm == cur->hwpwm)) ||
  172. ((ncfg == 1) && (pwm->hwpwm != cur->hwpwm) && period_same) ||
  173. ((ncfg > 1) && period_same)) {
  174. /* Enable clock before writing to PWM registers. */
  175. ret = clk_enable(pc->pwm_clk);
  176. if (ret)
  177. return ret;
  178. ret = clk_enable(pc->cpt_clk);
  179. if (ret)
  180. return ret;
  181. if (!period_same) {
  182. ret = sti_pwm_get_prescale(pc, period_ns, &prescale);
  183. if (ret)
  184. goto clk_dis;
  185. value = prescale & PWM_PRESCALE_LOW_MASK;
  186. ret = regmap_field_write(pc->prescale_low, value);
  187. if (ret)
  188. goto clk_dis;
  189. value = (prescale & PWM_PRESCALE_HIGH_MASK) >> 4;
  190. ret = regmap_field_write(pc->prescale_high, value);
  191. if (ret)
  192. goto clk_dis;
  193. }
  194. /*
  195. * When PWMVal == 0, PWM pulse = 1 local clock cycle.
  196. * When PWMVal == max_pwm_count,
  197. * PWM pulse = (max_pwm_count + 1) local cycles,
  198. * that is continuous pulse: signal never goes low.
  199. */
  200. value = cdata->max_pwm_cnt * duty_ns / period_ns;
  201. ret = regmap_write(pc->regmap, PWM_OUT_VAL(pwm->hwpwm), value);
  202. if (ret)
  203. goto clk_dis;
  204. ret = regmap_field_write(pc->pwm_cpt_int_en, 0);
  205. set_bit(pwm->hwpwm, &pc->configured);
  206. pc->cur = pwm;
  207. dev_dbg(dev, "prescale:%u, period:%i, duty:%i, value:%u\n",
  208. prescale, period_ns, duty_ns, value);
  209. } else {
  210. return -EINVAL;
  211. }
  212. clk_dis:
  213. clk_disable(pc->pwm_clk);
  214. clk_disable(pc->cpt_clk);
  215. return ret;
  216. }
  217. static int sti_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  218. {
  219. struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
  220. struct device *dev = pc->dev;
  221. int ret = 0;
  222. /*
  223. * Since we have a common enable for all PWM devices, do not enable if
  224. * already enabled.
  225. */
  226. mutex_lock(&pc->sti_pwm_lock);
  227. if (!pc->en_count) {
  228. ret = clk_enable(pc->pwm_clk);
  229. if (ret)
  230. goto out;
  231. ret = clk_enable(pc->cpt_clk);
  232. if (ret)
  233. goto out;
  234. ret = regmap_field_write(pc->pwm_out_en, 1);
  235. if (ret) {
  236. dev_err(dev, "failed to enable PWM device %u: %d\n",
  237. pwm->hwpwm, ret);
  238. goto out;
  239. }
  240. }
  241. pc->en_count++;
  242. out:
  243. mutex_unlock(&pc->sti_pwm_lock);
  244. return ret;
  245. }
  246. static void sti_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  247. {
  248. struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
  249. mutex_lock(&pc->sti_pwm_lock);
  250. if (--pc->en_count) {
  251. mutex_unlock(&pc->sti_pwm_lock);
  252. return;
  253. }
  254. regmap_field_write(pc->pwm_out_en, 0);
  255. clk_disable(pc->pwm_clk);
  256. clk_disable(pc->cpt_clk);
  257. mutex_unlock(&pc->sti_pwm_lock);
  258. }
  259. static void sti_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
  260. {
  261. struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
  262. clear_bit(pwm->hwpwm, &pc->configured);
  263. }
  264. static int sti_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
  265. struct pwm_capture *result, unsigned long timeout)
  266. {
  267. struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
  268. struct sti_pwm_compat_data *cdata = pc->cdata;
  269. struct sti_cpt_ddata *ddata = pwm_get_chip_data(pwm);
  270. struct device *dev = pc->dev;
  271. unsigned int effective_ticks;
  272. unsigned long long high, low;
  273. int ret;
  274. if (pwm->hwpwm >= cdata->cpt_num_devs) {
  275. dev_err(dev, "device %u is not valid\n", pwm->hwpwm);
  276. return -EINVAL;
  277. }
  278. mutex_lock(&ddata->lock);
  279. ddata->index = 0;
  280. /* Prepare capture measurement */
  281. regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_RISING);
  282. regmap_field_write(pc->pwm_cpt_int_en, BIT(pwm->hwpwm));
  283. /* Enable capture */
  284. ret = regmap_field_write(pc->pwm_cpt_en, 1);
  285. if (ret) {
  286. dev_err(dev, "failed to enable PWM capture %u: %d\n",
  287. pwm->hwpwm, ret);
  288. goto out;
  289. }
  290. ret = wait_event_interruptible_timeout(ddata->wait, ddata->index > 1,
  291. msecs_to_jiffies(timeout));
  292. regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_DISABLED);
  293. if (ret == -ERESTARTSYS)
  294. goto out;
  295. switch (ddata->index) {
  296. case 0:
  297. case 1:
  298. /*
  299. * Getting here could mean:
  300. * - input signal is constant of less than 1 Hz
  301. * - there is no input signal at all
  302. *
  303. * In such case the frequency is rounded down to 0
  304. */
  305. result->period = 0;
  306. result->duty_cycle = 0;
  307. break;
  308. case 2:
  309. /* We have everying we need */
  310. high = ddata->snapshot[1] - ddata->snapshot[0];
  311. low = ddata->snapshot[2] - ddata->snapshot[1];
  312. effective_ticks = clk_get_rate(pc->cpt_clk);
  313. result->period = (high + low) * NSEC_PER_SEC;
  314. result->period /= effective_ticks;
  315. result->duty_cycle = high * NSEC_PER_SEC;
  316. result->duty_cycle /= effective_ticks;
  317. break;
  318. default:
  319. dev_err(dev, "internal error\n");
  320. break;
  321. }
  322. out:
  323. /* Disable capture */
  324. regmap_field_write(pc->pwm_cpt_en, 0);
  325. mutex_unlock(&ddata->lock);
  326. return ret;
  327. }
  328. static const struct pwm_ops sti_pwm_ops = {
  329. .capture = sti_pwm_capture,
  330. .config = sti_pwm_config,
  331. .enable = sti_pwm_enable,
  332. .disable = sti_pwm_disable,
  333. .free = sti_pwm_free,
  334. .owner = THIS_MODULE,
  335. };
  336. static irqreturn_t sti_pwm_interrupt(int irq, void *data)
  337. {
  338. struct sti_pwm_chip *pc = data;
  339. struct device *dev = pc->dev;
  340. struct sti_cpt_ddata *ddata;
  341. int devicenum;
  342. unsigned int cpt_int_stat;
  343. unsigned int reg;
  344. int ret = IRQ_NONE;
  345. ret = regmap_field_read(pc->pwm_cpt_int_stat, &cpt_int_stat);
  346. if (ret)
  347. return ret;
  348. while (cpt_int_stat) {
  349. devicenum = ffs(cpt_int_stat) - 1;
  350. ddata = pwm_get_chip_data(&pc->chip.pwms[devicenum]);
  351. /*
  352. * Capture input:
  353. * _______ _______
  354. * | | | |
  355. * __| |_________________| |________
  356. * ^0 ^1 ^2
  357. *
  358. * Capture start by the first available rising edge. When a
  359. * capture event occurs, capture value (CPT_VALx) is stored,
  360. * index incremented, capture edge changed.
  361. *
  362. * After the capture, if the index > 1, we have collected the
  363. * necessary data so we signal the thread waiting for it and
  364. * disable the capture by setting capture edge to none
  365. */
  366. regmap_read(pc->regmap,
  367. PWM_CPT_VAL(devicenum),
  368. &ddata->snapshot[ddata->index]);
  369. switch (ddata->index) {
  370. case 0:
  371. case 1:
  372. regmap_read(pc->regmap, PWM_CPT_EDGE(devicenum), &reg);
  373. reg ^= PWM_CPT_EDGE_MASK;
  374. regmap_write(pc->regmap, PWM_CPT_EDGE(devicenum), reg);
  375. ddata->index++;
  376. break;
  377. case 2:
  378. regmap_write(pc->regmap,
  379. PWM_CPT_EDGE(devicenum),
  380. CPT_EDGE_DISABLED);
  381. wake_up(&ddata->wait);
  382. break;
  383. default:
  384. dev_err(dev, "Internal error\n");
  385. }
  386. cpt_int_stat &= ~BIT_MASK(devicenum);
  387. ret = IRQ_HANDLED;
  388. }
  389. /* Just ACK everything */
  390. regmap_write(pc->regmap, PWM_INT_ACK, PWM_INT_ACK_MASK);
  391. return ret;
  392. }
  393. static int sti_pwm_probe_dt(struct sti_pwm_chip *pc)
  394. {
  395. struct device *dev = pc->dev;
  396. const struct reg_field *reg_fields;
  397. struct device_node *np = dev->of_node;
  398. struct sti_pwm_compat_data *cdata = pc->cdata;
  399. u32 num_devs;
  400. int ret;
  401. ret = of_property_read_u32(np, "st,pwm-num-chan", &num_devs);
  402. if (!ret)
  403. cdata->pwm_num_devs = num_devs;
  404. ret = of_property_read_u32(np, "st,capture-num-chan", &num_devs);
  405. if (!ret)
  406. cdata->cpt_num_devs = num_devs;
  407. if (!cdata->pwm_num_devs && !cdata->cpt_num_devs) {
  408. dev_err(dev, "No channels configured\n");
  409. return -EINVAL;
  410. }
  411. reg_fields = cdata->reg_fields;
  412. pc->prescale_low = devm_regmap_field_alloc(dev, pc->regmap,
  413. reg_fields[PWMCLK_PRESCALE_LOW]);
  414. if (IS_ERR(pc->prescale_low))
  415. return PTR_ERR(pc->prescale_low);
  416. pc->prescale_high = devm_regmap_field_alloc(dev, pc->regmap,
  417. reg_fields[PWMCLK_PRESCALE_HIGH]);
  418. if (IS_ERR(pc->prescale_high))
  419. return PTR_ERR(pc->prescale_high);
  420. pc->pwm_out_en = devm_regmap_field_alloc(dev, pc->regmap,
  421. reg_fields[PWM_OUT_EN]);
  422. if (IS_ERR(pc->pwm_out_en))
  423. return PTR_ERR(pc->pwm_out_en);
  424. pc->pwm_cpt_en = devm_regmap_field_alloc(dev, pc->regmap,
  425. reg_fields[PWM_CPT_EN]);
  426. if (IS_ERR(pc->pwm_cpt_en))
  427. return PTR_ERR(pc->pwm_cpt_en);
  428. pc->pwm_cpt_int_en = devm_regmap_field_alloc(dev, pc->regmap,
  429. reg_fields[PWM_CPT_INT_EN]);
  430. if (IS_ERR(pc->pwm_cpt_int_en))
  431. return PTR_ERR(pc->pwm_cpt_int_en);
  432. pc->pwm_cpt_int_stat = devm_regmap_field_alloc(dev, pc->regmap,
  433. reg_fields[PWM_CPT_INT_STAT]);
  434. if (PTR_ERR_OR_ZERO(pc->pwm_cpt_int_stat))
  435. return PTR_ERR(pc->pwm_cpt_int_stat);
  436. return 0;
  437. }
  438. static const struct regmap_config sti_pwm_regmap_config = {
  439. .reg_bits = 32,
  440. .val_bits = 32,
  441. .reg_stride = 4,
  442. };
  443. static int sti_pwm_probe(struct platform_device *pdev)
  444. {
  445. struct device *dev = &pdev->dev;
  446. struct sti_pwm_compat_data *cdata;
  447. struct sti_pwm_chip *pc;
  448. struct resource *res;
  449. unsigned int i;
  450. int irq, ret;
  451. pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
  452. if (!pc)
  453. return -ENOMEM;
  454. cdata = devm_kzalloc(dev, sizeof(*cdata), GFP_KERNEL);
  455. if (!cdata)
  456. return -ENOMEM;
  457. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  458. pc->mmio = devm_ioremap_resource(dev, res);
  459. if (IS_ERR(pc->mmio))
  460. return PTR_ERR(pc->mmio);
  461. pc->regmap = devm_regmap_init_mmio(dev, pc->mmio,
  462. &sti_pwm_regmap_config);
  463. if (IS_ERR(pc->regmap))
  464. return PTR_ERR(pc->regmap);
  465. irq = platform_get_irq(pdev, 0);
  466. if (irq < 0) {
  467. dev_err(&pdev->dev, "Failed to obtain IRQ\n");
  468. return irq;
  469. }
  470. ret = devm_request_irq(&pdev->dev, irq, sti_pwm_interrupt, 0,
  471. pdev->name, pc);
  472. if (ret < 0) {
  473. dev_err(&pdev->dev, "Failed to request IRQ\n");
  474. return ret;
  475. }
  476. /*
  477. * Setup PWM data with default values: some values could be replaced
  478. * with specific ones provided from Device Tree.
  479. */
  480. cdata->reg_fields = sti_pwm_regfields;
  481. cdata->max_prescale = 0xff;
  482. cdata->max_pwm_cnt = 255;
  483. cdata->pwm_num_devs = 0;
  484. cdata->cpt_num_devs = 0;
  485. pc->cdata = cdata;
  486. pc->dev = dev;
  487. pc->en_count = 0;
  488. mutex_init(&pc->sti_pwm_lock);
  489. ret = sti_pwm_probe_dt(pc);
  490. if (ret)
  491. return ret;
  492. if (!cdata->pwm_num_devs)
  493. goto skip_pwm;
  494. pc->pwm_clk = of_clk_get_by_name(dev->of_node, "pwm");
  495. if (IS_ERR(pc->pwm_clk)) {
  496. dev_err(dev, "failed to get PWM clock\n");
  497. return PTR_ERR(pc->pwm_clk);
  498. }
  499. ret = clk_prepare(pc->pwm_clk);
  500. if (ret) {
  501. dev_err(dev, "failed to prepare clock\n");
  502. return ret;
  503. }
  504. skip_pwm:
  505. if (!cdata->cpt_num_devs)
  506. goto skip_cpt;
  507. pc->cpt_clk = of_clk_get_by_name(dev->of_node, "capture");
  508. if (IS_ERR(pc->cpt_clk)) {
  509. dev_err(dev, "failed to get PWM capture clock\n");
  510. return PTR_ERR(pc->cpt_clk);
  511. }
  512. ret = clk_prepare(pc->cpt_clk);
  513. if (ret) {
  514. dev_err(dev, "failed to prepare clock\n");
  515. return ret;
  516. }
  517. skip_cpt:
  518. pc->chip.dev = dev;
  519. pc->chip.ops = &sti_pwm_ops;
  520. pc->chip.base = -1;
  521. pc->chip.npwm = pc->cdata->pwm_num_devs;
  522. ret = pwmchip_add(&pc->chip);
  523. if (ret < 0) {
  524. clk_unprepare(pc->pwm_clk);
  525. clk_unprepare(pc->cpt_clk);
  526. return ret;
  527. }
  528. for (i = 0; i < cdata->cpt_num_devs; i++) {
  529. struct sti_cpt_ddata *ddata;
  530. ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
  531. if (!ddata)
  532. return -ENOMEM;
  533. init_waitqueue_head(&ddata->wait);
  534. mutex_init(&ddata->lock);
  535. pwm_set_chip_data(&pc->chip.pwms[i], ddata);
  536. }
  537. platform_set_drvdata(pdev, pc);
  538. return 0;
  539. }
  540. static int sti_pwm_remove(struct platform_device *pdev)
  541. {
  542. struct sti_pwm_chip *pc = platform_get_drvdata(pdev);
  543. unsigned int i;
  544. for (i = 0; i < pc->cdata->pwm_num_devs; i++)
  545. pwm_disable(&pc->chip.pwms[i]);
  546. clk_unprepare(pc->pwm_clk);
  547. clk_unprepare(pc->cpt_clk);
  548. return pwmchip_remove(&pc->chip);
  549. }
  550. static const struct of_device_id sti_pwm_of_match[] = {
  551. { .compatible = "st,sti-pwm", },
  552. { /* sentinel */ }
  553. };
  554. MODULE_DEVICE_TABLE(of, sti_pwm_of_match);
  555. static struct platform_driver sti_pwm_driver = {
  556. .driver = {
  557. .name = "sti-pwm",
  558. .of_match_table = sti_pwm_of_match,
  559. },
  560. .probe = sti_pwm_probe,
  561. .remove = sti_pwm_remove,
  562. };
  563. module_platform_driver(sti_pwm_driver);
  564. MODULE_AUTHOR("Ajit Pal Singh <ajitpal.singh@st.com>");
  565. MODULE_DESCRIPTION("STMicroelectronics ST PWM driver");
  566. MODULE_LICENSE("GPL");