max1027.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523
  1. /*
  2. * iio/adc/max1027.c
  3. * Copyright (C) 2014 Philippe Reynes
  4. *
  5. * based on linux/drivers/iio/ad7923.c
  6. * Copyright 2011 Analog Devices Inc (from AD7923 Driver)
  7. * Copyright 2012 CS Systemes d'Information
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * max1027.c
  14. *
  15. * Partial support for max1027 and similar chips.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/spi/spi.h>
  20. #include <linux/delay.h>
  21. #include <linux/iio/iio.h>
  22. #include <linux/iio/buffer.h>
  23. #include <linux/iio/trigger.h>
  24. #include <linux/iio/trigger_consumer.h>
  25. #include <linux/iio/triggered_buffer.h>
  26. #define MAX1027_CONV_REG BIT(7)
  27. #define MAX1027_SETUP_REG BIT(6)
  28. #define MAX1027_AVG_REG BIT(5)
  29. #define MAX1027_RST_REG BIT(4)
  30. /* conversion register */
  31. #define MAX1027_TEMP BIT(0)
  32. #define MAX1027_SCAN_0_N (0x00 << 1)
  33. #define MAX1027_SCAN_N_M (0x01 << 1)
  34. #define MAX1027_SCAN_N (0x02 << 1)
  35. #define MAX1027_NOSCAN (0x03 << 1)
  36. #define MAX1027_CHAN(n) ((n) << 3)
  37. /* setup register */
  38. #define MAX1027_UNIPOLAR 0x02
  39. #define MAX1027_BIPOLAR 0x03
  40. #define MAX1027_REF_MODE0 (0x00 << 2)
  41. #define MAX1027_REF_MODE1 (0x01 << 2)
  42. #define MAX1027_REF_MODE2 (0x02 << 2)
  43. #define MAX1027_REF_MODE3 (0x03 << 2)
  44. #define MAX1027_CKS_MODE0 (0x00 << 4)
  45. #define MAX1027_CKS_MODE1 (0x01 << 4)
  46. #define MAX1027_CKS_MODE2 (0x02 << 4)
  47. #define MAX1027_CKS_MODE3 (0x03 << 4)
  48. /* averaging register */
  49. #define MAX1027_NSCAN_4 0x00
  50. #define MAX1027_NSCAN_8 0x01
  51. #define MAX1027_NSCAN_12 0x02
  52. #define MAX1027_NSCAN_16 0x03
  53. #define MAX1027_NAVG_4 (0x00 << 2)
  54. #define MAX1027_NAVG_8 (0x01 << 2)
  55. #define MAX1027_NAVG_16 (0x02 << 2)
  56. #define MAX1027_NAVG_32 (0x03 << 2)
  57. #define MAX1027_AVG_EN BIT(4)
  58. enum max1027_id {
  59. max1027,
  60. max1029,
  61. max1031,
  62. };
  63. static const struct spi_device_id max1027_id[] = {
  64. {"max1027", max1027},
  65. {"max1029", max1029},
  66. {"max1031", max1031},
  67. {}
  68. };
  69. MODULE_DEVICE_TABLE(spi, max1027_id);
  70. #ifdef CONFIG_OF
  71. static const struct of_device_id max1027_adc_dt_ids[] = {
  72. { .compatible = "maxim,max1027" },
  73. { .compatible = "maxim,max1029" },
  74. { .compatible = "maxim,max1031" },
  75. {},
  76. };
  77. MODULE_DEVICE_TABLE(of, max1027_adc_dt_ids);
  78. #endif
  79. #define MAX1027_V_CHAN(index) \
  80. { \
  81. .type = IIO_VOLTAGE, \
  82. .indexed = 1, \
  83. .channel = index, \
  84. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  85. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
  86. .scan_index = index + 1, \
  87. .scan_type = { \
  88. .sign = 'u', \
  89. .realbits = 10, \
  90. .storagebits = 16, \
  91. .shift = 2, \
  92. .endianness = IIO_BE, \
  93. }, \
  94. }
  95. #define MAX1027_T_CHAN \
  96. { \
  97. .type = IIO_TEMP, \
  98. .channel = 0, \
  99. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  100. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
  101. .scan_index = 0, \
  102. .scan_type = { \
  103. .sign = 'u', \
  104. .realbits = 12, \
  105. .storagebits = 16, \
  106. .endianness = IIO_BE, \
  107. }, \
  108. }
  109. static const struct iio_chan_spec max1027_channels[] = {
  110. MAX1027_T_CHAN,
  111. MAX1027_V_CHAN(0),
  112. MAX1027_V_CHAN(1),
  113. MAX1027_V_CHAN(2),
  114. MAX1027_V_CHAN(3),
  115. MAX1027_V_CHAN(4),
  116. MAX1027_V_CHAN(5),
  117. MAX1027_V_CHAN(6),
  118. MAX1027_V_CHAN(7)
  119. };
  120. static const struct iio_chan_spec max1029_channels[] = {
  121. MAX1027_T_CHAN,
  122. MAX1027_V_CHAN(0),
  123. MAX1027_V_CHAN(1),
  124. MAX1027_V_CHAN(2),
  125. MAX1027_V_CHAN(3),
  126. MAX1027_V_CHAN(4),
  127. MAX1027_V_CHAN(5),
  128. MAX1027_V_CHAN(6),
  129. MAX1027_V_CHAN(7),
  130. MAX1027_V_CHAN(8),
  131. MAX1027_V_CHAN(9),
  132. MAX1027_V_CHAN(10),
  133. MAX1027_V_CHAN(11)
  134. };
  135. static const struct iio_chan_spec max1031_channels[] = {
  136. MAX1027_T_CHAN,
  137. MAX1027_V_CHAN(0),
  138. MAX1027_V_CHAN(1),
  139. MAX1027_V_CHAN(2),
  140. MAX1027_V_CHAN(3),
  141. MAX1027_V_CHAN(4),
  142. MAX1027_V_CHAN(5),
  143. MAX1027_V_CHAN(6),
  144. MAX1027_V_CHAN(7),
  145. MAX1027_V_CHAN(8),
  146. MAX1027_V_CHAN(9),
  147. MAX1027_V_CHAN(10),
  148. MAX1027_V_CHAN(11),
  149. MAX1027_V_CHAN(12),
  150. MAX1027_V_CHAN(13),
  151. MAX1027_V_CHAN(14),
  152. MAX1027_V_CHAN(15)
  153. };
  154. static const unsigned long max1027_available_scan_masks[] = {
  155. 0x000001ff,
  156. 0x00000000,
  157. };
  158. static const unsigned long max1029_available_scan_masks[] = {
  159. 0x00001fff,
  160. 0x00000000,
  161. };
  162. static const unsigned long max1031_available_scan_masks[] = {
  163. 0x0001ffff,
  164. 0x00000000,
  165. };
  166. struct max1027_chip_info {
  167. const struct iio_chan_spec *channels;
  168. unsigned int num_channels;
  169. const unsigned long *available_scan_masks;
  170. };
  171. static const struct max1027_chip_info max1027_chip_info_tbl[] = {
  172. [max1027] = {
  173. .channels = max1027_channels,
  174. .num_channels = ARRAY_SIZE(max1027_channels),
  175. .available_scan_masks = max1027_available_scan_masks,
  176. },
  177. [max1029] = {
  178. .channels = max1029_channels,
  179. .num_channels = ARRAY_SIZE(max1029_channels),
  180. .available_scan_masks = max1029_available_scan_masks,
  181. },
  182. [max1031] = {
  183. .channels = max1031_channels,
  184. .num_channels = ARRAY_SIZE(max1031_channels),
  185. .available_scan_masks = max1031_available_scan_masks,
  186. },
  187. };
  188. struct max1027_state {
  189. const struct max1027_chip_info *info;
  190. struct spi_device *spi;
  191. struct iio_trigger *trig;
  192. __be16 *buffer;
  193. struct mutex lock;
  194. u8 reg ____cacheline_aligned;
  195. };
  196. static int max1027_read_single_value(struct iio_dev *indio_dev,
  197. struct iio_chan_spec const *chan,
  198. int *val)
  199. {
  200. int ret;
  201. struct max1027_state *st = iio_priv(indio_dev);
  202. if (iio_buffer_enabled(indio_dev)) {
  203. dev_warn(&indio_dev->dev, "trigger mode already enabled");
  204. return -EBUSY;
  205. }
  206. /* Start acquisition on conversion register write */
  207. st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2 | MAX1027_CKS_MODE2;
  208. ret = spi_write(st->spi, &st->reg, 1);
  209. if (ret < 0) {
  210. dev_err(&indio_dev->dev,
  211. "Failed to configure setup register\n");
  212. return ret;
  213. }
  214. /* Configure conversion register with the requested chan */
  215. st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) |
  216. MAX1027_NOSCAN | !!(chan->type == IIO_TEMP);
  217. ret = spi_write(st->spi, &st->reg, 1);
  218. if (ret < 0) {
  219. dev_err(&indio_dev->dev,
  220. "Failed to configure conversion register\n");
  221. return ret;
  222. }
  223. /*
  224. * For an unknown reason, when we use the mode "10" (write
  225. * conversion register), the interrupt doesn't occur every time.
  226. * So we just wait 1 ms.
  227. */
  228. mdelay(1);
  229. /* Read result */
  230. ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2);
  231. if (ret < 0)
  232. return ret;
  233. *val = be16_to_cpu(st->buffer[0]);
  234. return IIO_VAL_INT;
  235. }
  236. static int max1027_read_raw(struct iio_dev *indio_dev,
  237. struct iio_chan_spec const *chan,
  238. int *val, int *val2, long mask)
  239. {
  240. int ret = 0;
  241. struct max1027_state *st = iio_priv(indio_dev);
  242. mutex_lock(&st->lock);
  243. switch (mask) {
  244. case IIO_CHAN_INFO_RAW:
  245. ret = max1027_read_single_value(indio_dev, chan, val);
  246. break;
  247. case IIO_CHAN_INFO_SCALE:
  248. switch (chan->type) {
  249. case IIO_TEMP:
  250. *val = 1;
  251. *val2 = 8;
  252. ret = IIO_VAL_FRACTIONAL;
  253. break;
  254. case IIO_VOLTAGE:
  255. *val = 2500;
  256. *val2 = 10;
  257. ret = IIO_VAL_FRACTIONAL_LOG2;
  258. break;
  259. default:
  260. ret = -EINVAL;
  261. break;
  262. }
  263. break;
  264. default:
  265. ret = -EINVAL;
  266. break;
  267. }
  268. mutex_unlock(&st->lock);
  269. return ret;
  270. }
  271. static int max1027_debugfs_reg_access(struct iio_dev *indio_dev,
  272. unsigned reg, unsigned writeval,
  273. unsigned *readval)
  274. {
  275. struct max1027_state *st = iio_priv(indio_dev);
  276. u8 *val = (u8 *)st->buffer;
  277. if (readval != NULL)
  278. return -EINVAL;
  279. *val = (u8)writeval;
  280. return spi_write(st->spi, val, 1);
  281. }
  282. static int max1027_validate_trigger(struct iio_dev *indio_dev,
  283. struct iio_trigger *trig)
  284. {
  285. struct max1027_state *st = iio_priv(indio_dev);
  286. if (st->trig != trig)
  287. return -EINVAL;
  288. return 0;
  289. }
  290. static int max1027_set_trigger_state(struct iio_trigger *trig, bool state)
  291. {
  292. struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
  293. struct max1027_state *st = iio_priv(indio_dev);
  294. int ret;
  295. if (state) {
  296. /* Start acquisition on cnvst */
  297. st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE0 |
  298. MAX1027_REF_MODE2;
  299. ret = spi_write(st->spi, &st->reg, 1);
  300. if (ret < 0)
  301. return ret;
  302. /* Scan from 0 to max */
  303. st->reg = MAX1027_CONV_REG | MAX1027_CHAN(0) |
  304. MAX1027_SCAN_N_M | MAX1027_TEMP;
  305. ret = spi_write(st->spi, &st->reg, 1);
  306. if (ret < 0)
  307. return ret;
  308. } else {
  309. /* Start acquisition on conversion register write */
  310. st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE2 |
  311. MAX1027_REF_MODE2;
  312. ret = spi_write(st->spi, &st->reg, 1);
  313. if (ret < 0)
  314. return ret;
  315. }
  316. return 0;
  317. }
  318. static int max1027_validate_device(struct iio_trigger *trig,
  319. struct iio_dev *indio_dev)
  320. {
  321. struct iio_dev *indio = iio_trigger_get_drvdata(trig);
  322. if (indio != indio_dev)
  323. return -EINVAL;
  324. return 0;
  325. }
  326. static irqreturn_t max1027_trigger_handler(int irq, void *private)
  327. {
  328. struct iio_poll_func *pf = (struct iio_poll_func *)private;
  329. struct iio_dev *indio_dev = pf->indio_dev;
  330. struct max1027_state *st = iio_priv(indio_dev);
  331. pr_debug("%s(irq=%d, private=0x%p)\n", __func__, irq, private);
  332. /* fill buffer with all channel */
  333. spi_read(st->spi, st->buffer, indio_dev->masklength * 2);
  334. iio_push_to_buffers(indio_dev, st->buffer);
  335. iio_trigger_notify_done(indio_dev->trig);
  336. return IRQ_HANDLED;
  337. }
  338. static const struct iio_trigger_ops max1027_trigger_ops = {
  339. .owner = THIS_MODULE,
  340. .validate_device = &max1027_validate_device,
  341. .set_trigger_state = &max1027_set_trigger_state,
  342. };
  343. static const struct iio_info max1027_info = {
  344. .driver_module = THIS_MODULE,
  345. .read_raw = &max1027_read_raw,
  346. .validate_trigger = &max1027_validate_trigger,
  347. .debugfs_reg_access = &max1027_debugfs_reg_access,
  348. };
  349. static int max1027_probe(struct spi_device *spi)
  350. {
  351. int ret;
  352. struct iio_dev *indio_dev;
  353. struct max1027_state *st;
  354. pr_debug("%s: probe(spi = 0x%p)\n", __func__, spi);
  355. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  356. if (indio_dev == NULL) {
  357. pr_err("Can't allocate iio device\n");
  358. return -ENOMEM;
  359. }
  360. spi_set_drvdata(spi, indio_dev);
  361. st = iio_priv(indio_dev);
  362. st->spi = spi;
  363. st->info = &max1027_chip_info_tbl[spi_get_device_id(spi)->driver_data];
  364. mutex_init(&st->lock);
  365. indio_dev->name = spi_get_device_id(spi)->name;
  366. indio_dev->dev.parent = &spi->dev;
  367. indio_dev->dev.of_node = spi->dev.of_node;
  368. indio_dev->info = &max1027_info;
  369. indio_dev->modes = INDIO_DIRECT_MODE;
  370. indio_dev->channels = st->info->channels;
  371. indio_dev->num_channels = st->info->num_channels;
  372. indio_dev->available_scan_masks = st->info->available_scan_masks;
  373. st->buffer = devm_kmalloc(&indio_dev->dev,
  374. indio_dev->num_channels * 2,
  375. GFP_KERNEL);
  376. if (st->buffer == NULL) {
  377. dev_err(&indio_dev->dev, "Can't allocate buffer\n");
  378. return -ENOMEM;
  379. }
  380. ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
  381. &max1027_trigger_handler, NULL);
  382. if (ret < 0) {
  383. dev_err(&indio_dev->dev, "Failed to setup buffer\n");
  384. return ret;
  385. }
  386. st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-trigger",
  387. indio_dev->name);
  388. if (st->trig == NULL) {
  389. ret = -ENOMEM;
  390. dev_err(&indio_dev->dev, "Failed to allocate iio trigger\n");
  391. goto fail_trigger_alloc;
  392. }
  393. st->trig->ops = &max1027_trigger_ops;
  394. st->trig->dev.parent = &spi->dev;
  395. iio_trigger_set_drvdata(st->trig, indio_dev);
  396. iio_trigger_register(st->trig);
  397. ret = devm_request_threaded_irq(&spi->dev, spi->irq,
  398. iio_trigger_generic_data_rdy_poll,
  399. NULL,
  400. IRQF_TRIGGER_FALLING,
  401. spi->dev.driver->name, st->trig);
  402. if (ret < 0) {
  403. dev_err(&indio_dev->dev, "Failed to allocate IRQ.\n");
  404. goto fail_dev_register;
  405. }
  406. /* Disable averaging */
  407. st->reg = MAX1027_AVG_REG;
  408. ret = spi_write(st->spi, &st->reg, 1);
  409. if (ret < 0) {
  410. dev_err(&indio_dev->dev, "Failed to configure averaging register\n");
  411. goto fail_dev_register;
  412. }
  413. ret = iio_device_register(indio_dev);
  414. if (ret < 0) {
  415. dev_err(&indio_dev->dev, "Failed to register iio device\n");
  416. goto fail_dev_register;
  417. }
  418. return 0;
  419. fail_dev_register:
  420. fail_trigger_alloc:
  421. iio_triggered_buffer_cleanup(indio_dev);
  422. return ret;
  423. }
  424. static int max1027_remove(struct spi_device *spi)
  425. {
  426. struct iio_dev *indio_dev = spi_get_drvdata(spi);
  427. pr_debug("%s: remove(spi = 0x%p)\n", __func__, spi);
  428. iio_device_unregister(indio_dev);
  429. iio_triggered_buffer_cleanup(indio_dev);
  430. return 0;
  431. }
  432. static struct spi_driver max1027_driver = {
  433. .driver = {
  434. .name = "max1027",
  435. .of_match_table = of_match_ptr(max1027_adc_dt_ids),
  436. },
  437. .probe = max1027_probe,
  438. .remove = max1027_remove,
  439. .id_table = max1027_id,
  440. };
  441. module_spi_driver(max1027_driver);
  442. MODULE_AUTHOR("Philippe Reynes <tremyfr@yahoo.fr>");
  443. MODULE_DESCRIPTION("MAX1027/MAX1029/MAX1031 ADC");
  444. MODULE_LICENSE("GPL v2");