A USB 2.0 High-Speed (480 Mbps) Galvanic Isolator.
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USB 2.0 is one of the most commonly used data interface. Often, implementing galvanic isolation (electrical isolation) is desirable. First, galvanic isolation protects the computer from destruction by high voltage transients or faults in an industrial environment. In the context of computing, it can be used by embedded system developers and hardware hackers to protect their computers from unexpected faults from the development boards, such as a dangerous short-circuit from +12 V to +5 V. Given the widespread knowledge of USB Killers, infosec researchers, too, can make use of an isolator. Also, galvanic isolation is useful to stop unwanted conductive electromagnetic interference between the computer and the USB device. Hence, amateur radio operators with cheap, low-EMI-immunity USB software defined radios may also find reliefs from noise with an USB isolator. And potentially, audio and video engineers may find an isolator helpful for breaking a ground loop.
Unfortunately, although USB 2.0 isolators for Low Speed (1.5 Mbps) and Full Speed (12 Mbps) is readily available, there are few isolators for High-Speed USB (480 Mbps) interfaces due to the difficulty of its high data rate. Currently, the available isolators are either expensive (FPGA-based solution), difficult to buy (ASIC isolators), or inconvenient to use (USB over CAT-5 or fiber optics extender, which requires a receiver and a transmitter).
This project is an experimental project that explores the possibility of using the CH317 USB-to-Ethernet controller to implement a single-board, low-cost, compact High-Speed USB 2.0 galvanic isolator.
A four-layer PCB with controlled impedance is used to route high-speed USB, RGMII and Ethernet signals. Unlike conventional four-layer PCBs, there's no dedicated power plane but two ground planes - the stackup is Signal/Power, Ground, Ground, Signal/Power with an extensive use of stitching vias to provide an low-impedance current return path, and minimized its interference to amateur radio receivers.
The single-board PCB is physically separated into the primary (host) side and secondary (device) side an isolation barrier, with independent power supplies and ground planes. Both sides are connected only by a Ethernet transformer and nothing else. The transformer is designed for Power-over- Ethernet application, thus it has a more robust Hi-Pot rating (4 kV) than conventional transformers (1.5 kV). The transformer couples the Ethernet traffic to the device side of the board.
On the host side, the incoming USB traffic from the Micro-USB connector is handled by CH317, acting as an USB PHY and USB controller. Subsequently, CH317 acts an a Gigabit Ethernet PHY and translate the USB traffic from the computer to Ethernet frames, and drives a RTL8211F Gigabit Ethernet PHY via RGMII to transmit the information on-the-wire. CH317 also controls (read/write registers) on the RTL8211F PHY via a low-speed MDIO serial interface.
The transformer couples the Ethernet traffic from the primary to the secondary side of the board.
On the device side, the incoming Ethernet traffic is handled by another RTL8211F and forwarded to another CH317, acting as an Ethernet MAC. The Ethernet traffic is translated back to USB traffic and sends to the USB device via an USB-A connector. This process is bidirectional, which means the data can flow from host to device, or from device to host, thus establishing bidirectional High-Speed USB communication.
To ensure the communication link can recover and reset if an unexpected error has occurred (or if the USB is disconnected). A separate watchdog CH9317G is used to monitor the USB traffic (via D+ and D- lines), CH317 (via MDIO interface) and RTL8211F (via MDIO interface) simultaneously.
After some debugging, board v0.02 (see git tag) is currently functional and can successfully establish a high-speed USB 2.0 link. Unfortunately, the data rate is limited to less than 10 MB/s (80 Mbps) in benchmarks, so although High-Speed USB 2.0 is technically supported, but it's largely unusable by most USB 2.0 High-Speed devices.
It's unknown whether it's an inherent limitation of CH317Q, incompatibility with RTL8211F PHY, or high bit-error-rate due to PCB layout issues. Technical documentation of CH317 is under NDA, and it's unavailable to me, so troubleshooting is somewhat impossible.
The current suspicion is that it's an inherent limitation of CH317Q. CH317Q is the first generation of CH317, it's and already obsoleted and replaced by the second generation - CH317L. But the price of a CH317L is 5x more expensive than a CH317Q.
Currently, I have a plan to design another prototype based on the newer CH317L and see whether it could work as intended.