tegra_pcm.c 10 KB

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  1. /*
  2. * tegra_pcm.c - Tegra PCM driver
  3. *
  4. * Author: Stephen Warren <swarren@nvidia.com>
  5. * Copyright (C) 2010 - NVIDIA, Inc.
  6. *
  7. * Based on code copyright/by:
  8. *
  9. * Copyright (c) 2009-2010, NVIDIA Corporation.
  10. * Scott Peterson <speterson@nvidia.com>
  11. * Vijay Mali <vmali@nvidia.com>
  12. *
  13. * Copyright (C) 2010 Google, Inc.
  14. * Iliyan Malchev <malchev@google.com>
  15. *
  16. * This program is free software; you can redistribute it and/or
  17. * modify it under the terms of the GNU General Public License
  18. * version 2 as published by the Free Software Foundation.
  19. *
  20. * This program is distributed in the hope that it will be useful, but
  21. * WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  23. * General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  28. * 02110-1301 USA
  29. *
  30. */
  31. #include <linux/module.h>
  32. #include <linux/dma-mapping.h>
  33. #include <linux/slab.h>
  34. #include <sound/core.h>
  35. #include <sound/pcm.h>
  36. #include <sound/pcm_params.h>
  37. #include <sound/soc.h>
  38. #include "tegra_pcm.h"
  39. #define DRV_NAME "tegra-pcm-audio"
  40. static const struct snd_pcm_hardware tegra_pcm_hardware = {
  41. .info = SNDRV_PCM_INFO_MMAP |
  42. SNDRV_PCM_INFO_MMAP_VALID |
  43. SNDRV_PCM_INFO_PAUSE |
  44. SNDRV_PCM_INFO_RESUME |
  45. SNDRV_PCM_INFO_INTERLEAVED,
  46. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  47. .channels_min = 2,
  48. .channels_max = 2,
  49. .period_bytes_min = 1024,
  50. .period_bytes_max = PAGE_SIZE,
  51. .periods_min = 2,
  52. .periods_max = 8,
  53. .buffer_bytes_max = PAGE_SIZE * 8,
  54. .fifo_size = 4,
  55. };
  56. static void tegra_pcm_queue_dma(struct tegra_runtime_data *prtd)
  57. {
  58. struct snd_pcm_substream *substream = prtd->substream;
  59. struct snd_dma_buffer *buf = &substream->dma_buffer;
  60. struct tegra_dma_req *dma_req;
  61. unsigned long addr;
  62. dma_req = &prtd->dma_req[prtd->dma_req_idx];
  63. prtd->dma_req_idx = 1 - prtd->dma_req_idx;
  64. addr = buf->addr + prtd->dma_pos;
  65. prtd->dma_pos += dma_req->size;
  66. if (prtd->dma_pos >= prtd->dma_pos_end)
  67. prtd->dma_pos = 0;
  68. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  69. dma_req->source_addr = addr;
  70. else
  71. dma_req->dest_addr = addr;
  72. tegra_dma_enqueue_req(prtd->dma_chan, dma_req);
  73. }
  74. static void dma_complete_callback(struct tegra_dma_req *req)
  75. {
  76. struct tegra_runtime_data *prtd = (struct tegra_runtime_data *)req->dev;
  77. struct snd_pcm_substream *substream = prtd->substream;
  78. struct snd_pcm_runtime *runtime = substream->runtime;
  79. spin_lock(&prtd->lock);
  80. if (!prtd->running) {
  81. spin_unlock(&prtd->lock);
  82. return;
  83. }
  84. if (++prtd->period_index >= runtime->periods)
  85. prtd->period_index = 0;
  86. tegra_pcm_queue_dma(prtd);
  87. spin_unlock(&prtd->lock);
  88. snd_pcm_period_elapsed(substream);
  89. }
  90. static void setup_dma_tx_request(struct tegra_dma_req *req,
  91. struct tegra_pcm_dma_params * dmap)
  92. {
  93. req->complete = dma_complete_callback;
  94. req->to_memory = false;
  95. req->dest_addr = dmap->addr;
  96. req->dest_wrap = dmap->wrap;
  97. req->source_bus_width = 32;
  98. req->source_wrap = 0;
  99. req->dest_bus_width = dmap->width;
  100. req->req_sel = dmap->req_sel;
  101. }
  102. static void setup_dma_rx_request(struct tegra_dma_req *req,
  103. struct tegra_pcm_dma_params * dmap)
  104. {
  105. req->complete = dma_complete_callback;
  106. req->to_memory = true;
  107. req->source_addr = dmap->addr;
  108. req->dest_wrap = 0;
  109. req->source_bus_width = dmap->width;
  110. req->source_wrap = dmap->wrap;
  111. req->dest_bus_width = 32;
  112. req->req_sel = dmap->req_sel;
  113. }
  114. static int tegra_pcm_open(struct snd_pcm_substream *substream)
  115. {
  116. struct snd_pcm_runtime *runtime = substream->runtime;
  117. struct tegra_runtime_data *prtd;
  118. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  119. struct tegra_pcm_dma_params * dmap;
  120. int ret = 0;
  121. prtd = kzalloc(sizeof(struct tegra_runtime_data), GFP_KERNEL);
  122. if (prtd == NULL)
  123. return -ENOMEM;
  124. runtime->private_data = prtd;
  125. prtd->substream = substream;
  126. spin_lock_init(&prtd->lock);
  127. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  128. dmap = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
  129. setup_dma_tx_request(&prtd->dma_req[0], dmap);
  130. setup_dma_tx_request(&prtd->dma_req[1], dmap);
  131. } else {
  132. dmap = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
  133. setup_dma_rx_request(&prtd->dma_req[0], dmap);
  134. setup_dma_rx_request(&prtd->dma_req[1], dmap);
  135. }
  136. prtd->dma_req[0].dev = prtd;
  137. prtd->dma_req[1].dev = prtd;
  138. prtd->dma_chan = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
  139. if (prtd->dma_chan == NULL) {
  140. ret = -ENOMEM;
  141. goto err;
  142. }
  143. /* Set HW params now that initialization is complete */
  144. snd_soc_set_runtime_hwparams(substream, &tegra_pcm_hardware);
  145. /* Ensure that buffer size is a multiple of period size */
  146. ret = snd_pcm_hw_constraint_integer(runtime,
  147. SNDRV_PCM_HW_PARAM_PERIODS);
  148. if (ret < 0)
  149. goto err;
  150. return 0;
  151. err:
  152. if (prtd->dma_chan) {
  153. tegra_dma_free_channel(prtd->dma_chan);
  154. }
  155. kfree(prtd);
  156. return ret;
  157. }
  158. static int tegra_pcm_close(struct snd_pcm_substream *substream)
  159. {
  160. struct snd_pcm_runtime *runtime = substream->runtime;
  161. struct tegra_runtime_data *prtd = runtime->private_data;
  162. tegra_dma_free_channel(prtd->dma_chan);
  163. kfree(prtd);
  164. return 0;
  165. }
  166. static int tegra_pcm_hw_params(struct snd_pcm_substream *substream,
  167. struct snd_pcm_hw_params *params)
  168. {
  169. struct snd_pcm_runtime *runtime = substream->runtime;
  170. struct tegra_runtime_data *prtd = runtime->private_data;
  171. snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
  172. prtd->dma_req[0].size = params_period_bytes(params);
  173. prtd->dma_req[1].size = prtd->dma_req[0].size;
  174. return 0;
  175. }
  176. static int tegra_pcm_hw_free(struct snd_pcm_substream *substream)
  177. {
  178. snd_pcm_set_runtime_buffer(substream, NULL);
  179. return 0;
  180. }
  181. static int tegra_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
  182. {
  183. struct snd_pcm_runtime *runtime = substream->runtime;
  184. struct tegra_runtime_data *prtd = runtime->private_data;
  185. unsigned long flags;
  186. switch (cmd) {
  187. case SNDRV_PCM_TRIGGER_START:
  188. prtd->dma_pos = 0;
  189. prtd->dma_pos_end = frames_to_bytes(runtime, runtime->periods * runtime->period_size);
  190. prtd->period_index = 0;
  191. prtd->dma_req_idx = 0;
  192. /* Fall-through */
  193. case SNDRV_PCM_TRIGGER_RESUME:
  194. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  195. spin_lock_irqsave(&prtd->lock, flags);
  196. prtd->running = 1;
  197. spin_unlock_irqrestore(&prtd->lock, flags);
  198. tegra_pcm_queue_dma(prtd);
  199. tegra_pcm_queue_dma(prtd);
  200. break;
  201. case SNDRV_PCM_TRIGGER_STOP:
  202. case SNDRV_PCM_TRIGGER_SUSPEND:
  203. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  204. spin_lock_irqsave(&prtd->lock, flags);
  205. prtd->running = 0;
  206. spin_unlock_irqrestore(&prtd->lock, flags);
  207. tegra_dma_dequeue_req(prtd->dma_chan, &prtd->dma_req[0]);
  208. tegra_dma_dequeue_req(prtd->dma_chan, &prtd->dma_req[1]);
  209. break;
  210. default:
  211. return -EINVAL;
  212. }
  213. return 0;
  214. }
  215. static snd_pcm_uframes_t tegra_pcm_pointer(struct snd_pcm_substream *substream)
  216. {
  217. struct snd_pcm_runtime *runtime = substream->runtime;
  218. struct tegra_runtime_data *prtd = runtime->private_data;
  219. return prtd->period_index * runtime->period_size;
  220. }
  221. static int tegra_pcm_mmap(struct snd_pcm_substream *substream,
  222. struct vm_area_struct *vma)
  223. {
  224. struct snd_pcm_runtime *runtime = substream->runtime;
  225. return dma_mmap_writecombine(substream->pcm->card->dev, vma,
  226. runtime->dma_area,
  227. runtime->dma_addr,
  228. runtime->dma_bytes);
  229. }
  230. static struct snd_pcm_ops tegra_pcm_ops = {
  231. .open = tegra_pcm_open,
  232. .close = tegra_pcm_close,
  233. .ioctl = snd_pcm_lib_ioctl,
  234. .hw_params = tegra_pcm_hw_params,
  235. .hw_free = tegra_pcm_hw_free,
  236. .trigger = tegra_pcm_trigger,
  237. .pointer = tegra_pcm_pointer,
  238. .mmap = tegra_pcm_mmap,
  239. };
  240. static int tegra_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
  241. {
  242. struct snd_pcm_substream *substream = pcm->streams[stream].substream;
  243. struct snd_dma_buffer *buf = &substream->dma_buffer;
  244. size_t size = tegra_pcm_hardware.buffer_bytes_max;
  245. buf->area = dma_alloc_writecombine(pcm->card->dev, size,
  246. &buf->addr, GFP_KERNEL);
  247. if (!buf->area)
  248. return -ENOMEM;
  249. buf->dev.type = SNDRV_DMA_TYPE_DEV;
  250. buf->dev.dev = pcm->card->dev;
  251. buf->private_data = NULL;
  252. buf->bytes = size;
  253. return 0;
  254. }
  255. static void tegra_pcm_deallocate_dma_buffer(struct snd_pcm *pcm, int stream)
  256. {
  257. struct snd_pcm_substream *substream;
  258. struct snd_dma_buffer *buf;
  259. substream = pcm->streams[stream].substream;
  260. if (!substream)
  261. return;
  262. buf = &substream->dma_buffer;
  263. if (!buf->area)
  264. return;
  265. dma_free_writecombine(pcm->card->dev, buf->bytes,
  266. buf->area, buf->addr);
  267. buf->area = NULL;
  268. }
  269. static u64 tegra_dma_mask = DMA_BIT_MASK(32);
  270. static int tegra_pcm_new(struct snd_card *card,
  271. struct snd_soc_dai *dai, struct snd_pcm *pcm)
  272. {
  273. int ret = 0;
  274. if (!card->dev->dma_mask)
  275. card->dev->dma_mask = &tegra_dma_mask;
  276. if (!card->dev->coherent_dma_mask)
  277. card->dev->coherent_dma_mask = 0xffffffff;
  278. if (dai->driver->playback.channels_min) {
  279. ret = tegra_pcm_preallocate_dma_buffer(pcm,
  280. SNDRV_PCM_STREAM_PLAYBACK);
  281. if (ret)
  282. goto err;
  283. }
  284. if (dai->driver->capture.channels_min) {
  285. ret = tegra_pcm_preallocate_dma_buffer(pcm,
  286. SNDRV_PCM_STREAM_CAPTURE);
  287. if (ret)
  288. goto err_free_play;
  289. }
  290. return 0;
  291. err_free_play:
  292. tegra_pcm_deallocate_dma_buffer(pcm, SNDRV_PCM_STREAM_PLAYBACK);
  293. err:
  294. return ret;
  295. }
  296. static void tegra_pcm_free(struct snd_pcm *pcm)
  297. {
  298. tegra_pcm_deallocate_dma_buffer(pcm, SNDRV_PCM_STREAM_CAPTURE);
  299. tegra_pcm_deallocate_dma_buffer(pcm, SNDRV_PCM_STREAM_PLAYBACK);
  300. }
  301. struct snd_soc_platform_driver tegra_pcm_platform = {
  302. .ops = &tegra_pcm_ops,
  303. .pcm_new = tegra_pcm_new,
  304. .pcm_free = tegra_pcm_free,
  305. };
  306. static int __devinit tegra_pcm_platform_probe(struct platform_device *pdev)
  307. {
  308. return snd_soc_register_platform(&pdev->dev, &tegra_pcm_platform);
  309. }
  310. static int __devexit tegra_pcm_platform_remove(struct platform_device *pdev)
  311. {
  312. snd_soc_unregister_platform(&pdev->dev);
  313. return 0;
  314. }
  315. static struct platform_driver tegra_pcm_driver = {
  316. .driver = {
  317. .name = DRV_NAME,
  318. .owner = THIS_MODULE,
  319. },
  320. .probe = tegra_pcm_platform_probe,
  321. .remove = __devexit_p(tegra_pcm_platform_remove),
  322. };
  323. static int __init snd_tegra_pcm_init(void)
  324. {
  325. return platform_driver_register(&tegra_pcm_driver);
  326. }
  327. module_init(snd_tegra_pcm_init);
  328. static void __exit snd_tegra_pcm_exit(void)
  329. {
  330. platform_driver_unregister(&tegra_pcm_driver);
  331. }
  332. module_exit(snd_tegra_pcm_exit);
  333. MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
  334. MODULE_DESCRIPTION("Tegra PCM ASoC driver");
  335. MODULE_LICENSE("GPL");
  336. MODULE_ALIAS("platform:" DRV_NAME);