wm8804.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838
  1. /*
  2. * wm8804.c -- WM8804 S/PDIF transceiver driver
  3. *
  4. * Copyright 2010 Wolfson Microelectronics plc
  5. *
  6. * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/init.h>
  15. #include <linux/delay.h>
  16. #include <linux/pm.h>
  17. #include <linux/i2c.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/regulator/consumer.h>
  20. #include <linux/slab.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/soc.h>
  25. #include <sound/initval.h>
  26. #include <sound/tlv.h>
  27. #include "wm8804.h"
  28. #define WM8804_NUM_SUPPLIES 2
  29. static const char *wm8804_supply_names[WM8804_NUM_SUPPLIES] = {
  30. "PVDD",
  31. "DVDD"
  32. };
  33. static const u8 wm8804_reg_defs[] = {
  34. 0x05, /* R0 - RST/DEVID1 */
  35. 0x88, /* R1 - DEVID2 */
  36. 0x04, /* R2 - DEVREV */
  37. 0x21, /* R3 - PLL1 */
  38. 0xFD, /* R4 - PLL2 */
  39. 0x36, /* R5 - PLL3 */
  40. 0x07, /* R6 - PLL4 */
  41. 0x16, /* R7 - PLL5 */
  42. 0x18, /* R8 - PLL6 */
  43. 0xFF, /* R9 - SPDMODE */
  44. 0x00, /* R10 - INTMASK */
  45. 0x00, /* R11 - INTSTAT */
  46. 0x00, /* R12 - SPDSTAT */
  47. 0x00, /* R13 - RXCHAN1 */
  48. 0x00, /* R14 - RXCHAN2 */
  49. 0x00, /* R15 - RXCHAN3 */
  50. 0x00, /* R16 - RXCHAN4 */
  51. 0x00, /* R17 - RXCHAN5 */
  52. 0x00, /* R18 - SPDTX1 */
  53. 0x00, /* R19 - SPDTX2 */
  54. 0x00, /* R20 - SPDTX3 */
  55. 0x71, /* R21 - SPDTX4 */
  56. 0x0B, /* R22 - SPDTX5 */
  57. 0x70, /* R23 - GPO0 */
  58. 0x57, /* R24 - GPO1 */
  59. 0x00, /* R25 */
  60. 0x42, /* R26 - GPO2 */
  61. 0x06, /* R27 - AIFTX */
  62. 0x06, /* R28 - AIFRX */
  63. 0x80, /* R29 - SPDRX1 */
  64. 0x07, /* R30 - PWRDN */
  65. };
  66. struct wm8804_priv {
  67. enum snd_soc_control_type control_type;
  68. struct regulator_bulk_data supplies[WM8804_NUM_SUPPLIES];
  69. struct notifier_block disable_nb[WM8804_NUM_SUPPLIES];
  70. struct snd_soc_codec *codec;
  71. };
  72. static int txsrc_get(struct snd_kcontrol *kcontrol,
  73. struct snd_ctl_elem_value *ucontrol);
  74. static int txsrc_put(struct snd_kcontrol *kcontrol,
  75. struct snd_ctl_elem_value *ucontrol);
  76. /*
  77. * We can't use the same notifier block for more than one supply and
  78. * there's no way I can see to get from a callback to the caller
  79. * except container_of().
  80. */
  81. #define WM8804_REGULATOR_EVENT(n) \
  82. static int wm8804_regulator_event_##n(struct notifier_block *nb, \
  83. unsigned long event, void *data) \
  84. { \
  85. struct wm8804_priv *wm8804 = container_of(nb, struct wm8804_priv, \
  86. disable_nb[n]); \
  87. if (event & REGULATOR_EVENT_DISABLE) { \
  88. wm8804->codec->cache_sync = 1; \
  89. } \
  90. return 0; \
  91. }
  92. WM8804_REGULATOR_EVENT(0)
  93. WM8804_REGULATOR_EVENT(1)
  94. static const char *txsrc_text[] = { "S/PDIF RX", "AIF" };
  95. static const SOC_ENUM_SINGLE_EXT_DECL(txsrc, txsrc_text);
  96. static const struct snd_kcontrol_new wm8804_snd_controls[] = {
  97. SOC_ENUM_EXT("Input Source", txsrc, txsrc_get, txsrc_put),
  98. SOC_SINGLE("TX Playback Switch", WM8804_PWRDN, 2, 1, 1),
  99. SOC_SINGLE("AIF Playback Switch", WM8804_PWRDN, 4, 1, 1)
  100. };
  101. static int txsrc_get(struct snd_kcontrol *kcontrol,
  102. struct snd_ctl_elem_value *ucontrol)
  103. {
  104. struct snd_soc_codec *codec;
  105. unsigned int src;
  106. codec = snd_kcontrol_chip(kcontrol);
  107. src = snd_soc_read(codec, WM8804_SPDTX4);
  108. if (src & 0x40)
  109. ucontrol->value.integer.value[0] = 1;
  110. else
  111. ucontrol->value.integer.value[0] = 0;
  112. return 0;
  113. }
  114. static int txsrc_put(struct snd_kcontrol *kcontrol,
  115. struct snd_ctl_elem_value *ucontrol)
  116. {
  117. struct snd_soc_codec *codec;
  118. unsigned int src, txpwr;
  119. codec = snd_kcontrol_chip(kcontrol);
  120. if (ucontrol->value.integer.value[0] != 0
  121. && ucontrol->value.integer.value[0] != 1)
  122. return -EINVAL;
  123. src = snd_soc_read(codec, WM8804_SPDTX4);
  124. switch ((src & 0x40) >> 6) {
  125. case 0:
  126. if (!ucontrol->value.integer.value[0])
  127. return 0;
  128. break;
  129. case 1:
  130. if (ucontrol->value.integer.value[1])
  131. return 0;
  132. break;
  133. }
  134. /* save the current power state of the transmitter */
  135. txpwr = snd_soc_read(codec, WM8804_PWRDN) & 0x4;
  136. /* power down the transmitter */
  137. snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x4);
  138. /* set the tx source */
  139. snd_soc_update_bits(codec, WM8804_SPDTX4, 0x40,
  140. ucontrol->value.integer.value[0] << 6);
  141. if (ucontrol->value.integer.value[0]) {
  142. /* power down the receiver */
  143. snd_soc_update_bits(codec, WM8804_PWRDN, 0x2, 0x2);
  144. /* power up the AIF */
  145. snd_soc_update_bits(codec, WM8804_PWRDN, 0x10, 0);
  146. } else {
  147. /* don't power down the AIF -- may be used as an output */
  148. /* power up the receiver */
  149. snd_soc_update_bits(codec, WM8804_PWRDN, 0x2, 0);
  150. }
  151. /* restore the transmitter's configuration */
  152. snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, txpwr);
  153. return 0;
  154. }
  155. static int wm8804_volatile(struct snd_soc_codec *codec, unsigned int reg)
  156. {
  157. switch (reg) {
  158. case WM8804_RST_DEVID1:
  159. case WM8804_DEVID2:
  160. case WM8804_DEVREV:
  161. case WM8804_INTSTAT:
  162. case WM8804_SPDSTAT:
  163. case WM8804_RXCHAN1:
  164. case WM8804_RXCHAN2:
  165. case WM8804_RXCHAN3:
  166. case WM8804_RXCHAN4:
  167. case WM8804_RXCHAN5:
  168. return 1;
  169. default:
  170. break;
  171. }
  172. return 0;
  173. }
  174. static int wm8804_reset(struct snd_soc_codec *codec)
  175. {
  176. return snd_soc_write(codec, WM8804_RST_DEVID1, 0x0);
  177. }
  178. static int wm8804_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  179. {
  180. struct snd_soc_codec *codec;
  181. u16 format, master, bcp, lrp;
  182. codec = dai->codec;
  183. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  184. case SND_SOC_DAIFMT_I2S:
  185. format = 0x2;
  186. break;
  187. case SND_SOC_DAIFMT_RIGHT_J:
  188. format = 0x0;
  189. break;
  190. case SND_SOC_DAIFMT_LEFT_J:
  191. format = 0x1;
  192. break;
  193. case SND_SOC_DAIFMT_DSP_A:
  194. case SND_SOC_DAIFMT_DSP_B:
  195. format = 0x3;
  196. break;
  197. default:
  198. dev_err(dai->dev, "Unknown dai format\n");
  199. return -EINVAL;
  200. }
  201. /* set data format */
  202. snd_soc_update_bits(codec, WM8804_AIFTX, 0x3, format);
  203. snd_soc_update_bits(codec, WM8804_AIFRX, 0x3, format);
  204. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  205. case SND_SOC_DAIFMT_CBM_CFM:
  206. master = 1;
  207. break;
  208. case SND_SOC_DAIFMT_CBS_CFS:
  209. master = 0;
  210. break;
  211. default:
  212. dev_err(dai->dev, "Unknown master/slave configuration\n");
  213. return -EINVAL;
  214. }
  215. /* set master/slave mode */
  216. snd_soc_update_bits(codec, WM8804_AIFRX, 0x40, master << 6);
  217. bcp = lrp = 0;
  218. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  219. case SND_SOC_DAIFMT_NB_NF:
  220. break;
  221. case SND_SOC_DAIFMT_IB_IF:
  222. bcp = lrp = 1;
  223. break;
  224. case SND_SOC_DAIFMT_IB_NF:
  225. bcp = 1;
  226. break;
  227. case SND_SOC_DAIFMT_NB_IF:
  228. lrp = 1;
  229. break;
  230. default:
  231. dev_err(dai->dev, "Unknown polarity configuration\n");
  232. return -EINVAL;
  233. }
  234. /* set frame inversion */
  235. snd_soc_update_bits(codec, WM8804_AIFTX, 0x10 | 0x20,
  236. (bcp << 4) | (lrp << 5));
  237. snd_soc_update_bits(codec, WM8804_AIFRX, 0x10 | 0x20,
  238. (bcp << 4) | (lrp << 5));
  239. return 0;
  240. }
  241. static int wm8804_hw_params(struct snd_pcm_substream *substream,
  242. struct snd_pcm_hw_params *params,
  243. struct snd_soc_dai *dai)
  244. {
  245. struct snd_soc_codec *codec;
  246. u16 blen;
  247. codec = dai->codec;
  248. switch (params_format(params)) {
  249. case SNDRV_PCM_FORMAT_S16_LE:
  250. blen = 0x0;
  251. break;
  252. case SNDRV_PCM_FORMAT_S20_3LE:
  253. blen = 0x1;
  254. break;
  255. case SNDRV_PCM_FORMAT_S24_LE:
  256. blen = 0x2;
  257. break;
  258. default:
  259. dev_err(dai->dev, "Unsupported word length: %u\n",
  260. params_format(params));
  261. return -EINVAL;
  262. }
  263. /* set word length */
  264. snd_soc_update_bits(codec, WM8804_AIFTX, 0xc, blen << 2);
  265. snd_soc_update_bits(codec, WM8804_AIFRX, 0xc, blen << 2);
  266. return 0;
  267. }
  268. struct pll_div {
  269. u32 prescale:1;
  270. u32 mclkdiv:1;
  271. u32 freqmode:2;
  272. u32 n:4;
  273. u32 k:22;
  274. };
  275. /* PLL rate to output rate divisions */
  276. static struct {
  277. unsigned int div;
  278. unsigned int freqmode;
  279. unsigned int mclkdiv;
  280. } post_table[] = {
  281. { 2, 0, 0 },
  282. { 4, 0, 1 },
  283. { 4, 1, 0 },
  284. { 8, 1, 1 },
  285. { 8, 2, 0 },
  286. { 16, 2, 1 },
  287. { 12, 3, 0 },
  288. { 24, 3, 1 }
  289. };
  290. #define FIXED_PLL_SIZE ((1ULL << 22) * 10)
  291. static int pll_factors(struct pll_div *pll_div, unsigned int target,
  292. unsigned int source)
  293. {
  294. u64 Kpart;
  295. unsigned long int K, Ndiv, Nmod, tmp;
  296. int i;
  297. /*
  298. * Scale the output frequency up; the PLL should run in the
  299. * region of 90-100MHz.
  300. */
  301. for (i = 0; i < ARRAY_SIZE(post_table); i++) {
  302. tmp = target * post_table[i].div;
  303. if (tmp >= 90000000 && tmp <= 100000000) {
  304. pll_div->freqmode = post_table[i].freqmode;
  305. pll_div->mclkdiv = post_table[i].mclkdiv;
  306. target *= post_table[i].div;
  307. break;
  308. }
  309. }
  310. if (i == ARRAY_SIZE(post_table)) {
  311. pr_err("%s: Unable to scale output frequency: %uHz\n",
  312. __func__, target);
  313. return -EINVAL;
  314. }
  315. pll_div->prescale = 0;
  316. Ndiv = target / source;
  317. if (Ndiv < 5) {
  318. source >>= 1;
  319. pll_div->prescale = 1;
  320. Ndiv = target / source;
  321. }
  322. if (Ndiv < 5 || Ndiv > 13) {
  323. pr_err("%s: WM8804 N value is not within the recommended range: %lu\n",
  324. __func__, Ndiv);
  325. return -EINVAL;
  326. }
  327. pll_div->n = Ndiv;
  328. Nmod = target % source;
  329. Kpart = FIXED_PLL_SIZE * (u64)Nmod;
  330. do_div(Kpart, source);
  331. K = Kpart & 0xffffffff;
  332. if ((K % 10) >= 5)
  333. K += 5;
  334. K /= 10;
  335. pll_div->k = K;
  336. return 0;
  337. }
  338. static int wm8804_set_pll(struct snd_soc_dai *dai, int pll_id,
  339. int source, unsigned int freq_in,
  340. unsigned int freq_out)
  341. {
  342. struct snd_soc_codec *codec;
  343. codec = dai->codec;
  344. if (!freq_in || !freq_out) {
  345. /* disable the PLL */
  346. snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0x1);
  347. return 0;
  348. } else {
  349. int ret;
  350. struct pll_div pll_div;
  351. ret = pll_factors(&pll_div, freq_out, freq_in);
  352. if (ret)
  353. return ret;
  354. /* power down the PLL before reprogramming it */
  355. snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0x1);
  356. if (!freq_in || !freq_out)
  357. return 0;
  358. /* set PLLN and PRESCALE */
  359. snd_soc_update_bits(codec, WM8804_PLL4, 0xf | 0x10,
  360. pll_div.n | (pll_div.prescale << 4));
  361. /* set mclkdiv and freqmode */
  362. snd_soc_update_bits(codec, WM8804_PLL5, 0x3 | 0x8,
  363. pll_div.freqmode | (pll_div.mclkdiv << 3));
  364. /* set PLLK */
  365. snd_soc_write(codec, WM8804_PLL1, pll_div.k & 0xff);
  366. snd_soc_write(codec, WM8804_PLL2, (pll_div.k >> 8) & 0xff);
  367. snd_soc_write(codec, WM8804_PLL3, pll_div.k >> 16);
  368. /* power up the PLL */
  369. snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0);
  370. }
  371. return 0;
  372. }
  373. static int wm8804_set_sysclk(struct snd_soc_dai *dai,
  374. int clk_id, unsigned int freq, int dir)
  375. {
  376. struct snd_soc_codec *codec;
  377. codec = dai->codec;
  378. switch (clk_id) {
  379. case WM8804_TX_CLKSRC_MCLK:
  380. if ((freq >= 10000000 && freq <= 14400000)
  381. || (freq >= 16280000 && freq <= 27000000))
  382. snd_soc_update_bits(codec, WM8804_PLL6, 0x80, 0x80);
  383. else {
  384. dev_err(dai->dev, "OSCCLOCK is not within the "
  385. "recommended range: %uHz\n", freq);
  386. return -EINVAL;
  387. }
  388. break;
  389. case WM8804_TX_CLKSRC_PLL:
  390. snd_soc_update_bits(codec, WM8804_PLL6, 0x80, 0);
  391. break;
  392. case WM8804_CLKOUT_SRC_CLK1:
  393. snd_soc_update_bits(codec, WM8804_PLL6, 0x8, 0);
  394. break;
  395. case WM8804_CLKOUT_SRC_OSCCLK:
  396. snd_soc_update_bits(codec, WM8804_PLL6, 0x8, 0x8);
  397. break;
  398. default:
  399. dev_err(dai->dev, "Unknown clock source: %d\n", clk_id);
  400. return -EINVAL;
  401. }
  402. return 0;
  403. }
  404. static int wm8804_set_clkdiv(struct snd_soc_dai *dai,
  405. int div_id, int div)
  406. {
  407. struct snd_soc_codec *codec;
  408. codec = dai->codec;
  409. switch (div_id) {
  410. case WM8804_CLKOUT_DIV:
  411. snd_soc_update_bits(codec, WM8804_PLL5, 0x30,
  412. (div & 0x3) << 4);
  413. break;
  414. default:
  415. dev_err(dai->dev, "Unknown clock divider: %d\n", div_id);
  416. return -EINVAL;
  417. }
  418. return 0;
  419. }
  420. static void wm8804_sync_cache(struct snd_soc_codec *codec)
  421. {
  422. short i;
  423. u8 *cache;
  424. if (!codec->cache_sync)
  425. return;
  426. codec->cache_only = 0;
  427. cache = codec->reg_cache;
  428. for (i = 0; i < codec->driver->reg_cache_size; i++) {
  429. if (i == WM8804_RST_DEVID1 || cache[i] == wm8804_reg_defs[i])
  430. continue;
  431. snd_soc_write(codec, i, cache[i]);
  432. }
  433. codec->cache_sync = 0;
  434. }
  435. static int wm8804_set_bias_level(struct snd_soc_codec *codec,
  436. enum snd_soc_bias_level level)
  437. {
  438. int ret;
  439. struct wm8804_priv *wm8804;
  440. wm8804 = snd_soc_codec_get_drvdata(codec);
  441. switch (level) {
  442. case SND_SOC_BIAS_ON:
  443. break;
  444. case SND_SOC_BIAS_PREPARE:
  445. /* power up the OSC and the PLL */
  446. snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0);
  447. break;
  448. case SND_SOC_BIAS_STANDBY:
  449. if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
  450. ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies),
  451. wm8804->supplies);
  452. if (ret) {
  453. dev_err(codec->dev,
  454. "Failed to enable supplies: %d\n",
  455. ret);
  456. return ret;
  457. }
  458. wm8804_sync_cache(codec);
  459. }
  460. /* power down the OSC and the PLL */
  461. snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0x9);
  462. break;
  463. case SND_SOC_BIAS_OFF:
  464. /* power down the OSC and the PLL */
  465. snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0x9);
  466. regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies),
  467. wm8804->supplies);
  468. break;
  469. }
  470. codec->dapm.bias_level = level;
  471. return 0;
  472. }
  473. #ifdef CONFIG_PM
  474. static int wm8804_suspend(struct snd_soc_codec *codec, pm_message_t state)
  475. {
  476. wm8804_set_bias_level(codec, SND_SOC_BIAS_OFF);
  477. return 0;
  478. }
  479. static int wm8804_resume(struct snd_soc_codec *codec)
  480. {
  481. wm8804_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  482. return 0;
  483. }
  484. #else
  485. #define wm8804_suspend NULL
  486. #define wm8804_resume NULL
  487. #endif
  488. static int wm8804_remove(struct snd_soc_codec *codec)
  489. {
  490. struct wm8804_priv *wm8804;
  491. int i;
  492. wm8804 = snd_soc_codec_get_drvdata(codec);
  493. wm8804_set_bias_level(codec, SND_SOC_BIAS_OFF);
  494. for (i = 0; i < ARRAY_SIZE(wm8804->supplies); ++i)
  495. regulator_unregister_notifier(wm8804->supplies[i].consumer,
  496. &wm8804->disable_nb[i]);
  497. regulator_bulk_free(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
  498. return 0;
  499. }
  500. static int wm8804_probe(struct snd_soc_codec *codec)
  501. {
  502. struct wm8804_priv *wm8804;
  503. int i, id1, id2, ret;
  504. wm8804 = snd_soc_codec_get_drvdata(codec);
  505. wm8804->codec = codec;
  506. codec->dapm.idle_bias_off = 1;
  507. ret = snd_soc_codec_set_cache_io(codec, 8, 8, wm8804->control_type);
  508. if (ret < 0) {
  509. dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret);
  510. return ret;
  511. }
  512. for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++)
  513. wm8804->supplies[i].supply = wm8804_supply_names[i];
  514. ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8804->supplies),
  515. wm8804->supplies);
  516. if (ret) {
  517. dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
  518. return ret;
  519. }
  520. wm8804->disable_nb[0].notifier_call = wm8804_regulator_event_0;
  521. wm8804->disable_nb[1].notifier_call = wm8804_regulator_event_1;
  522. /* This should really be moved into the regulator core */
  523. for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++) {
  524. ret = regulator_register_notifier(wm8804->supplies[i].consumer,
  525. &wm8804->disable_nb[i]);
  526. if (ret != 0) {
  527. dev_err(codec->dev,
  528. "Failed to register regulator notifier: %d\n",
  529. ret);
  530. }
  531. }
  532. ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies),
  533. wm8804->supplies);
  534. if (ret) {
  535. dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
  536. goto err_reg_get;
  537. }
  538. id1 = snd_soc_read(codec, WM8804_RST_DEVID1);
  539. if (id1 < 0) {
  540. dev_err(codec->dev, "Failed to read device ID: %d\n", id1);
  541. ret = id1;
  542. goto err_reg_enable;
  543. }
  544. id2 = snd_soc_read(codec, WM8804_DEVID2);
  545. if (id2 < 0) {
  546. dev_err(codec->dev, "Failed to read device ID: %d\n", id2);
  547. ret = id2;
  548. goto err_reg_enable;
  549. }
  550. id2 = (id2 << 8) | id1;
  551. if (id2 != ((wm8804_reg_defs[WM8804_DEVID2] << 8)
  552. | wm8804_reg_defs[WM8804_RST_DEVID1])) {
  553. dev_err(codec->dev, "Invalid device ID: %#x\n", id2);
  554. ret = -EINVAL;
  555. goto err_reg_enable;
  556. }
  557. ret = snd_soc_read(codec, WM8804_DEVREV);
  558. if (ret < 0) {
  559. dev_err(codec->dev, "Failed to read device revision: %d\n",
  560. ret);
  561. goto err_reg_enable;
  562. }
  563. dev_info(codec->dev, "revision %c\n", ret + 'A');
  564. ret = wm8804_reset(codec);
  565. if (ret < 0) {
  566. dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
  567. goto err_reg_enable;
  568. }
  569. wm8804_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  570. snd_soc_add_controls(codec, wm8804_snd_controls,
  571. ARRAY_SIZE(wm8804_snd_controls));
  572. return 0;
  573. err_reg_enable:
  574. regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
  575. err_reg_get:
  576. regulator_bulk_free(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
  577. return ret;
  578. }
  579. static struct snd_soc_dai_ops wm8804_dai_ops = {
  580. .hw_params = wm8804_hw_params,
  581. .set_fmt = wm8804_set_fmt,
  582. .set_sysclk = wm8804_set_sysclk,
  583. .set_clkdiv = wm8804_set_clkdiv,
  584. .set_pll = wm8804_set_pll
  585. };
  586. #define WM8804_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  587. SNDRV_PCM_FMTBIT_S24_LE)
  588. #define WM8804_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
  589. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
  590. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \
  591. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
  592. static struct snd_soc_dai_driver wm8804_dai = {
  593. .name = "wm8804-spdif",
  594. .playback = {
  595. .stream_name = "Playback",
  596. .channels_min = 2,
  597. .channels_max = 2,
  598. .rates = WM8804_RATES,
  599. .formats = WM8804_FORMATS,
  600. },
  601. .capture = {
  602. .stream_name = "Capture",
  603. .channels_min = 2,
  604. .channels_max = 2,
  605. .rates = WM8804_RATES,
  606. .formats = WM8804_FORMATS,
  607. },
  608. .ops = &wm8804_dai_ops,
  609. .symmetric_rates = 1
  610. };
  611. static struct snd_soc_codec_driver soc_codec_dev_wm8804 = {
  612. .probe = wm8804_probe,
  613. .remove = wm8804_remove,
  614. .suspend = wm8804_suspend,
  615. .resume = wm8804_resume,
  616. .set_bias_level = wm8804_set_bias_level,
  617. .reg_cache_size = ARRAY_SIZE(wm8804_reg_defs),
  618. .reg_word_size = sizeof(u8),
  619. .reg_cache_default = wm8804_reg_defs,
  620. .volatile_register = wm8804_volatile
  621. };
  622. #if defined(CONFIG_SPI_MASTER)
  623. static int __devinit wm8804_spi_probe(struct spi_device *spi)
  624. {
  625. struct wm8804_priv *wm8804;
  626. int ret;
  627. wm8804 = kzalloc(sizeof *wm8804, GFP_KERNEL);
  628. if (!wm8804)
  629. return -ENOMEM;
  630. wm8804->control_type = SND_SOC_SPI;
  631. spi_set_drvdata(spi, wm8804);
  632. ret = snd_soc_register_codec(&spi->dev,
  633. &soc_codec_dev_wm8804, &wm8804_dai, 1);
  634. if (ret < 0)
  635. kfree(wm8804);
  636. return ret;
  637. }
  638. static int __devexit wm8804_spi_remove(struct spi_device *spi)
  639. {
  640. snd_soc_unregister_codec(&spi->dev);
  641. kfree(spi_get_drvdata(spi));
  642. return 0;
  643. }
  644. static struct spi_driver wm8804_spi_driver = {
  645. .driver = {
  646. .name = "wm8804",
  647. .owner = THIS_MODULE,
  648. },
  649. .probe = wm8804_spi_probe,
  650. .remove = __devexit_p(wm8804_spi_remove)
  651. };
  652. #endif
  653. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  654. static __devinit int wm8804_i2c_probe(struct i2c_client *i2c,
  655. const struct i2c_device_id *id)
  656. {
  657. struct wm8804_priv *wm8804;
  658. int ret;
  659. wm8804 = kzalloc(sizeof *wm8804, GFP_KERNEL);
  660. if (!wm8804)
  661. return -ENOMEM;
  662. wm8804->control_type = SND_SOC_I2C;
  663. i2c_set_clientdata(i2c, wm8804);
  664. ret = snd_soc_register_codec(&i2c->dev,
  665. &soc_codec_dev_wm8804, &wm8804_dai, 1);
  666. if (ret < 0)
  667. kfree(wm8804);
  668. return ret;
  669. }
  670. static __devexit int wm8804_i2c_remove(struct i2c_client *client)
  671. {
  672. snd_soc_unregister_codec(&client->dev);
  673. kfree(i2c_get_clientdata(client));
  674. return 0;
  675. }
  676. static const struct i2c_device_id wm8804_i2c_id[] = {
  677. { "wm8804", 0 },
  678. { }
  679. };
  680. MODULE_DEVICE_TABLE(i2c, wm8804_i2c_id);
  681. static struct i2c_driver wm8804_i2c_driver = {
  682. .driver = {
  683. .name = "wm8804",
  684. .owner = THIS_MODULE,
  685. },
  686. .probe = wm8804_i2c_probe,
  687. .remove = __devexit_p(wm8804_i2c_remove),
  688. .id_table = wm8804_i2c_id
  689. };
  690. #endif
  691. static int __init wm8804_modinit(void)
  692. {
  693. int ret = 0;
  694. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  695. ret = i2c_add_driver(&wm8804_i2c_driver);
  696. if (ret) {
  697. printk(KERN_ERR "Failed to register wm8804 I2C driver: %d\n",
  698. ret);
  699. }
  700. #endif
  701. #if defined(CONFIG_SPI_MASTER)
  702. ret = spi_register_driver(&wm8804_spi_driver);
  703. if (ret != 0) {
  704. printk(KERN_ERR "Failed to register wm8804 SPI driver: %d\n",
  705. ret);
  706. }
  707. #endif
  708. return ret;
  709. }
  710. module_init(wm8804_modinit);
  711. static void __exit wm8804_exit(void)
  712. {
  713. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  714. i2c_del_driver(&wm8804_i2c_driver);
  715. #endif
  716. #if defined(CONFIG_SPI_MASTER)
  717. spi_unregister_driver(&wm8804_spi_driver);
  718. #endif
  719. }
  720. module_exit(wm8804_exit);
  721. MODULE_DESCRIPTION("ASoC WM8804 driver");
  722. MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
  723. MODULE_LICENSE("GPL");