uda1380.c 24 KB

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  1. /*
  2. * uda1380.c - Philips UDA1380 ALSA SoC audio driver
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * Copyright (c) 2007-2009 Philipp Zabel <philipp.zabel@gmail.com>
  9. *
  10. * Modified by Richard Purdie <richard@openedhand.com> to fit into SoC
  11. * codec model.
  12. *
  13. * Copyright (c) 2005 Giorgio Padrin <giorgio@mandarinlogiq.org>
  14. * Copyright 2005 Openedhand Ltd.
  15. */
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/types.h>
  19. #include <linux/slab.h>
  20. #include <linux/errno.h>
  21. #include <linux/gpio.h>
  22. #include <linux/delay.h>
  23. #include <linux/i2c.h>
  24. #include <linux/workqueue.h>
  25. #include <sound/core.h>
  26. #include <sound/control.h>
  27. #include <sound/initval.h>
  28. #include <sound/soc.h>
  29. #include <sound/tlv.h>
  30. #include <sound/uda1380.h>
  31. #include "uda1380.h"
  32. /* codec private data */
  33. struct uda1380_priv {
  34. struct snd_soc_codec *codec;
  35. unsigned int dac_clk;
  36. struct work_struct work;
  37. void *control_data;
  38. };
  39. /*
  40. * uda1380 register cache
  41. */
  42. static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = {
  43. 0x0502, 0x0000, 0x0000, 0x3f3f,
  44. 0x0202, 0x0000, 0x0000, 0x0000,
  45. 0x0000, 0x0000, 0x0000, 0x0000,
  46. 0x0000, 0x0000, 0x0000, 0x0000,
  47. 0x0000, 0xff00, 0x0000, 0x4800,
  48. 0x0000, 0x0000, 0x0000, 0x0000,
  49. 0x0000, 0x0000, 0x0000, 0x0000,
  50. 0x0000, 0x0000, 0x0000, 0x0000,
  51. 0x0000, 0x8000, 0x0002, 0x0000,
  52. };
  53. static unsigned long uda1380_cache_dirty;
  54. /*
  55. * read uda1380 register cache
  56. */
  57. static inline unsigned int uda1380_read_reg_cache(struct snd_soc_codec *codec,
  58. unsigned int reg)
  59. {
  60. u16 *cache = codec->reg_cache;
  61. if (reg == UDA1380_RESET)
  62. return 0;
  63. if (reg >= UDA1380_CACHEREGNUM)
  64. return -1;
  65. return cache[reg];
  66. }
  67. /*
  68. * write uda1380 register cache
  69. */
  70. static inline void uda1380_write_reg_cache(struct snd_soc_codec *codec,
  71. u16 reg, unsigned int value)
  72. {
  73. u16 *cache = codec->reg_cache;
  74. if (reg >= UDA1380_CACHEREGNUM)
  75. return;
  76. if ((reg >= 0x10) && (cache[reg] != value))
  77. set_bit(reg - 0x10, &uda1380_cache_dirty);
  78. cache[reg] = value;
  79. }
  80. /*
  81. * write to the UDA1380 register space
  82. */
  83. static int uda1380_write(struct snd_soc_codec *codec, unsigned int reg,
  84. unsigned int value)
  85. {
  86. u8 data[3];
  87. /* data is
  88. * data[0] is register offset
  89. * data[1] is MS byte
  90. * data[2] is LS byte
  91. */
  92. data[0] = reg;
  93. data[1] = (value & 0xff00) >> 8;
  94. data[2] = value & 0x00ff;
  95. uda1380_write_reg_cache(codec, reg, value);
  96. /* the interpolator & decimator regs must only be written when the
  97. * codec DAI is active.
  98. */
  99. if (!codec->active && (reg >= UDA1380_MVOL))
  100. return 0;
  101. pr_debug("uda1380: hw write %x val %x\n", reg, value);
  102. if (codec->hw_write(codec->control_data, data, 3) == 3) {
  103. unsigned int val;
  104. i2c_master_send(codec->control_data, data, 1);
  105. i2c_master_recv(codec->control_data, data, 2);
  106. val = (data[0]<<8) | data[1];
  107. if (val != value) {
  108. pr_debug("uda1380: READ BACK VAL %x\n",
  109. (data[0]<<8) | data[1]);
  110. return -EIO;
  111. }
  112. if (reg >= 0x10)
  113. clear_bit(reg - 0x10, &uda1380_cache_dirty);
  114. return 0;
  115. } else
  116. return -EIO;
  117. }
  118. static void uda1380_sync_cache(struct snd_soc_codec *codec)
  119. {
  120. int reg;
  121. u8 data[3];
  122. u16 *cache = codec->reg_cache;
  123. /* Sync reg_cache with the hardware */
  124. for (reg = 0; reg < UDA1380_MVOL; reg++) {
  125. data[0] = reg;
  126. data[1] = (cache[reg] & 0xff00) >> 8;
  127. data[2] = cache[reg] & 0x00ff;
  128. if (codec->hw_write(codec->control_data, data, 3) != 3)
  129. dev_err(codec->dev, "%s: write to reg 0x%x failed\n",
  130. __func__, reg);
  131. }
  132. }
  133. static int uda1380_reset(struct snd_soc_codec *codec)
  134. {
  135. struct uda1380_platform_data *pdata = codec->dev->platform_data;
  136. if (gpio_is_valid(pdata->gpio_reset)) {
  137. gpio_set_value(pdata->gpio_reset, 1);
  138. mdelay(1);
  139. gpio_set_value(pdata->gpio_reset, 0);
  140. } else {
  141. u8 data[3];
  142. data[0] = UDA1380_RESET;
  143. data[1] = 0;
  144. data[2] = 0;
  145. if (codec->hw_write(codec->control_data, data, 3) != 3) {
  146. dev_err(codec->dev, "%s: failed\n", __func__);
  147. return -EIO;
  148. }
  149. }
  150. return 0;
  151. }
  152. static void uda1380_flush_work(struct work_struct *work)
  153. {
  154. struct uda1380_priv *uda1380 = container_of(work, struct uda1380_priv, work);
  155. struct snd_soc_codec *uda1380_codec = uda1380->codec;
  156. int bit, reg;
  157. for_each_set_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) {
  158. reg = 0x10 + bit;
  159. pr_debug("uda1380: flush reg %x val %x:\n", reg,
  160. uda1380_read_reg_cache(uda1380_codec, reg));
  161. uda1380_write(uda1380_codec, reg,
  162. uda1380_read_reg_cache(uda1380_codec, reg));
  163. clear_bit(bit, &uda1380_cache_dirty);
  164. }
  165. }
  166. /* declarations of ALSA reg_elem_REAL controls */
  167. static const char *uda1380_deemp[] = {
  168. "None",
  169. "32kHz",
  170. "44.1kHz",
  171. "48kHz",
  172. "96kHz",
  173. };
  174. static const char *uda1380_input_sel[] = {
  175. "Line",
  176. "Mic + Line R",
  177. "Line L",
  178. "Mic",
  179. };
  180. static const char *uda1380_output_sel[] = {
  181. "DAC",
  182. "Analog Mixer",
  183. };
  184. static const char *uda1380_spf_mode[] = {
  185. "Flat",
  186. "Minimum1",
  187. "Minimum2",
  188. "Maximum"
  189. };
  190. static const char *uda1380_capture_sel[] = {
  191. "ADC",
  192. "Digital Mixer"
  193. };
  194. static const char *uda1380_sel_ns[] = {
  195. "3rd-order",
  196. "5th-order"
  197. };
  198. static const char *uda1380_mix_control[] = {
  199. "off",
  200. "PCM only",
  201. "before sound processing",
  202. "after sound processing"
  203. };
  204. static const char *uda1380_sdet_setting[] = {
  205. "3200",
  206. "4800",
  207. "9600",
  208. "19200"
  209. };
  210. static const char *uda1380_os_setting[] = {
  211. "single-speed",
  212. "double-speed (no mixing)",
  213. "quad-speed (no mixing)"
  214. };
  215. static const struct soc_enum uda1380_deemp_enum[] = {
  216. SOC_ENUM_SINGLE(UDA1380_DEEMP, 8, 5, uda1380_deemp),
  217. SOC_ENUM_SINGLE(UDA1380_DEEMP, 0, 5, uda1380_deemp),
  218. };
  219. static const struct soc_enum uda1380_input_sel_enum =
  220. SOC_ENUM_SINGLE(UDA1380_ADC, 2, 4, uda1380_input_sel); /* SEL_MIC, SEL_LNA */
  221. static const struct soc_enum uda1380_output_sel_enum =
  222. SOC_ENUM_SINGLE(UDA1380_PM, 7, 2, uda1380_output_sel); /* R02_EN_AVC */
  223. static const struct soc_enum uda1380_spf_enum =
  224. SOC_ENUM_SINGLE(UDA1380_MODE, 14, 4, uda1380_spf_mode); /* M */
  225. static const struct soc_enum uda1380_capture_sel_enum =
  226. SOC_ENUM_SINGLE(UDA1380_IFACE, 6, 2, uda1380_capture_sel); /* SEL_SOURCE */
  227. static const struct soc_enum uda1380_sel_ns_enum =
  228. SOC_ENUM_SINGLE(UDA1380_MIXER, 14, 2, uda1380_sel_ns); /* SEL_NS */
  229. static const struct soc_enum uda1380_mix_enum =
  230. SOC_ENUM_SINGLE(UDA1380_MIXER, 12, 4, uda1380_mix_control); /* MIX, MIX_POS */
  231. static const struct soc_enum uda1380_sdet_enum =
  232. SOC_ENUM_SINGLE(UDA1380_MIXER, 4, 4, uda1380_sdet_setting); /* SD_VALUE */
  233. static const struct soc_enum uda1380_os_enum =
  234. SOC_ENUM_SINGLE(UDA1380_MIXER, 0, 3, uda1380_os_setting); /* OS */
  235. /*
  236. * from -48 dB in 1.5 dB steps (mute instead of -49.5 dB)
  237. */
  238. static DECLARE_TLV_DB_SCALE(amix_tlv, -4950, 150, 1);
  239. /*
  240. * from -78 dB in 1 dB steps (3 dB steps, really. LSB are ignored),
  241. * from -66 dB in 0.5 dB steps (2 dB steps, really) and
  242. * from -52 dB in 0.25 dB steps
  243. */
  244. static const unsigned int mvol_tlv[] = {
  245. TLV_DB_RANGE_HEAD(3),
  246. 0, 15, TLV_DB_SCALE_ITEM(-8200, 100, 1),
  247. 16, 43, TLV_DB_SCALE_ITEM(-6600, 50, 0),
  248. 44, 252, TLV_DB_SCALE_ITEM(-5200, 25, 0),
  249. };
  250. /*
  251. * from -72 dB in 1.5 dB steps (6 dB steps really),
  252. * from -66 dB in 0.75 dB steps (3 dB steps really),
  253. * from -60 dB in 0.5 dB steps (2 dB steps really) and
  254. * from -46 dB in 0.25 dB steps
  255. */
  256. static const unsigned int vc_tlv[] = {
  257. TLV_DB_RANGE_HEAD(4),
  258. 0, 7, TLV_DB_SCALE_ITEM(-7800, 150, 1),
  259. 8, 15, TLV_DB_SCALE_ITEM(-6600, 75, 0),
  260. 16, 43, TLV_DB_SCALE_ITEM(-6000, 50, 0),
  261. 44, 228, TLV_DB_SCALE_ITEM(-4600, 25, 0),
  262. };
  263. /* from 0 to 6 dB in 2 dB steps if SPF mode != flat */
  264. static DECLARE_TLV_DB_SCALE(tr_tlv, 0, 200, 0);
  265. /* from 0 to 24 dB in 2 dB steps, if SPF mode == maximum, otherwise cuts
  266. * off at 18 dB max) */
  267. static DECLARE_TLV_DB_SCALE(bb_tlv, 0, 200, 0);
  268. /* from -63 to 24 dB in 0.5 dB steps (-128...48) */
  269. static DECLARE_TLV_DB_SCALE(dec_tlv, -6400, 50, 1);
  270. /* from 0 to 24 dB in 3 dB steps */
  271. static DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
  272. /* from 0 to 30 dB in 2 dB steps */
  273. static DECLARE_TLV_DB_SCALE(vga_tlv, 0, 200, 0);
  274. static const struct snd_kcontrol_new uda1380_snd_controls[] = {
  275. SOC_DOUBLE_TLV("Analog Mixer Volume", UDA1380_AMIX, 0, 8, 44, 1, amix_tlv), /* AVCR, AVCL */
  276. SOC_DOUBLE_TLV("Master Playback Volume", UDA1380_MVOL, 0, 8, 252, 1, mvol_tlv), /* MVCL, MVCR */
  277. SOC_SINGLE_TLV("ADC Playback Volume", UDA1380_MIXVOL, 8, 228, 1, vc_tlv), /* VC2 */
  278. SOC_SINGLE_TLV("PCM Playback Volume", UDA1380_MIXVOL, 0, 228, 1, vc_tlv), /* VC1 */
  279. SOC_ENUM("Sound Processing Filter", uda1380_spf_enum), /* M */
  280. SOC_DOUBLE_TLV("Tone Control - Treble", UDA1380_MODE, 4, 12, 3, 0, tr_tlv), /* TRL, TRR */
  281. SOC_DOUBLE_TLV("Tone Control - Bass", UDA1380_MODE, 0, 8, 15, 0, bb_tlv), /* BBL, BBR */
  282. /**/ SOC_SINGLE("Master Playback Switch", UDA1380_DEEMP, 14, 1, 1), /* MTM */
  283. SOC_SINGLE("ADC Playback Switch", UDA1380_DEEMP, 11, 1, 1), /* MT2 from decimation filter */
  284. SOC_ENUM("ADC Playback De-emphasis", uda1380_deemp_enum[0]), /* DE2 */
  285. SOC_SINGLE("PCM Playback Switch", UDA1380_DEEMP, 3, 1, 1), /* MT1, from digital data input */
  286. SOC_ENUM("PCM Playback De-emphasis", uda1380_deemp_enum[1]), /* DE1 */
  287. SOC_SINGLE("DAC Polarity inverting Switch", UDA1380_MIXER, 15, 1, 0), /* DA_POL_INV */
  288. SOC_ENUM("Noise Shaper", uda1380_sel_ns_enum), /* SEL_NS */
  289. SOC_ENUM("Digital Mixer Signal Control", uda1380_mix_enum), /* MIX_POS, MIX */
  290. SOC_SINGLE("Silence Detector Switch", UDA1380_MIXER, 6, 1, 0), /* SDET_ON */
  291. SOC_ENUM("Silence Detector Setting", uda1380_sdet_enum), /* SD_VALUE */
  292. SOC_ENUM("Oversampling Input", uda1380_os_enum), /* OS */
  293. SOC_DOUBLE_S8_TLV("ADC Capture Volume", UDA1380_DEC, -128, 48, dec_tlv), /* ML_DEC, MR_DEC */
  294. /**/ SOC_SINGLE("ADC Capture Switch", UDA1380_PGA, 15, 1, 1), /* MT_ADC */
  295. SOC_DOUBLE_TLV("Line Capture Volume", UDA1380_PGA, 0, 8, 8, 0, pga_tlv), /* PGA_GAINCTRLL, PGA_GAINCTRLR */
  296. SOC_SINGLE("ADC Polarity inverting Switch", UDA1380_ADC, 12, 1, 0), /* ADCPOL_INV */
  297. SOC_SINGLE_TLV("Mic Capture Volume", UDA1380_ADC, 8, 15, 0, vga_tlv), /* VGA_CTRL */
  298. SOC_SINGLE("DC Filter Bypass Switch", UDA1380_ADC, 1, 1, 0), /* SKIP_DCFIL (before decimator) */
  299. SOC_SINGLE("DC Filter Enable Switch", UDA1380_ADC, 0, 1, 0), /* EN_DCFIL (at output of decimator) */
  300. SOC_SINGLE("AGC Timing", UDA1380_AGC, 8, 7, 0), /* TODO: enum, see table 62 */
  301. SOC_SINGLE("AGC Target level", UDA1380_AGC, 2, 3, 1), /* AGC_LEVEL */
  302. /* -5.5, -8, -11.5, -14 dBFS */
  303. SOC_SINGLE("AGC Switch", UDA1380_AGC, 0, 1, 0),
  304. };
  305. /* Input mux */
  306. static const struct snd_kcontrol_new uda1380_input_mux_control =
  307. SOC_DAPM_ENUM("Route", uda1380_input_sel_enum);
  308. /* Output mux */
  309. static const struct snd_kcontrol_new uda1380_output_mux_control =
  310. SOC_DAPM_ENUM("Route", uda1380_output_sel_enum);
  311. /* Capture mux */
  312. static const struct snd_kcontrol_new uda1380_capture_mux_control =
  313. SOC_DAPM_ENUM("Route", uda1380_capture_sel_enum);
  314. static const struct snd_soc_dapm_widget uda1380_dapm_widgets[] = {
  315. SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
  316. &uda1380_input_mux_control),
  317. SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM, 0, 0,
  318. &uda1380_output_mux_control),
  319. SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
  320. &uda1380_capture_mux_control),
  321. SND_SOC_DAPM_PGA("Left PGA", UDA1380_PM, 3, 0, NULL, 0),
  322. SND_SOC_DAPM_PGA("Right PGA", UDA1380_PM, 1, 0, NULL, 0),
  323. SND_SOC_DAPM_PGA("Mic LNA", UDA1380_PM, 4, 0, NULL, 0),
  324. SND_SOC_DAPM_ADC("Left ADC", "Left Capture", UDA1380_PM, 2, 0),
  325. SND_SOC_DAPM_ADC("Right ADC", "Right Capture", UDA1380_PM, 0, 0),
  326. SND_SOC_DAPM_INPUT("VINM"),
  327. SND_SOC_DAPM_INPUT("VINL"),
  328. SND_SOC_DAPM_INPUT("VINR"),
  329. SND_SOC_DAPM_MIXER("Analog Mixer", UDA1380_PM, 6, 0, NULL, 0),
  330. SND_SOC_DAPM_OUTPUT("VOUTLHP"),
  331. SND_SOC_DAPM_OUTPUT("VOUTRHP"),
  332. SND_SOC_DAPM_OUTPUT("VOUTL"),
  333. SND_SOC_DAPM_OUTPUT("VOUTR"),
  334. SND_SOC_DAPM_DAC("DAC", "Playback", UDA1380_PM, 10, 0),
  335. SND_SOC_DAPM_PGA("HeadPhone Driver", UDA1380_PM, 13, 0, NULL, 0),
  336. };
  337. static const struct snd_soc_dapm_route audio_map[] = {
  338. /* output mux */
  339. {"HeadPhone Driver", NULL, "Output Mux"},
  340. {"VOUTR", NULL, "Output Mux"},
  341. {"VOUTL", NULL, "Output Mux"},
  342. {"Analog Mixer", NULL, "VINR"},
  343. {"Analog Mixer", NULL, "VINL"},
  344. {"Analog Mixer", NULL, "DAC"},
  345. {"Output Mux", "DAC", "DAC"},
  346. {"Output Mux", "Analog Mixer", "Analog Mixer"},
  347. /* {"DAC", "Digital Mixer", "I2S" } */
  348. /* headphone driver */
  349. {"VOUTLHP", NULL, "HeadPhone Driver"},
  350. {"VOUTRHP", NULL, "HeadPhone Driver"},
  351. /* input mux */
  352. {"Left ADC", NULL, "Input Mux"},
  353. {"Input Mux", "Mic", "Mic LNA"},
  354. {"Input Mux", "Mic + Line R", "Mic LNA"},
  355. {"Input Mux", "Line L", "Left PGA"},
  356. {"Input Mux", "Line", "Left PGA"},
  357. /* right input */
  358. {"Right ADC", "Mic + Line R", "Right PGA"},
  359. {"Right ADC", "Line", "Right PGA"},
  360. /* inputs */
  361. {"Mic LNA", NULL, "VINM"},
  362. {"Left PGA", NULL, "VINL"},
  363. {"Right PGA", NULL, "VINR"},
  364. };
  365. static int uda1380_add_widgets(struct snd_soc_codec *codec)
  366. {
  367. struct snd_soc_dapm_context *dapm = &codec->dapm;
  368. snd_soc_dapm_new_controls(dapm, uda1380_dapm_widgets,
  369. ARRAY_SIZE(uda1380_dapm_widgets));
  370. snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
  371. return 0;
  372. }
  373. static int uda1380_set_dai_fmt_both(struct snd_soc_dai *codec_dai,
  374. unsigned int fmt)
  375. {
  376. struct snd_soc_codec *codec = codec_dai->codec;
  377. int iface;
  378. /* set up DAI based upon fmt */
  379. iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
  380. iface &= ~(R01_SFORI_MASK | R01_SIM | R01_SFORO_MASK);
  381. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  382. case SND_SOC_DAIFMT_I2S:
  383. iface |= R01_SFORI_I2S | R01_SFORO_I2S;
  384. break;
  385. case SND_SOC_DAIFMT_LSB:
  386. iface |= R01_SFORI_LSB16 | R01_SFORO_LSB16;
  387. break;
  388. case SND_SOC_DAIFMT_MSB:
  389. iface |= R01_SFORI_MSB | R01_SFORO_MSB;
  390. }
  391. /* DATAI is slave only, so in single-link mode, this has to be slave */
  392. if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
  393. return -EINVAL;
  394. uda1380_write(codec, UDA1380_IFACE, iface);
  395. return 0;
  396. }
  397. static int uda1380_set_dai_fmt_playback(struct snd_soc_dai *codec_dai,
  398. unsigned int fmt)
  399. {
  400. struct snd_soc_codec *codec = codec_dai->codec;
  401. int iface;
  402. /* set up DAI based upon fmt */
  403. iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
  404. iface &= ~R01_SFORI_MASK;
  405. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  406. case SND_SOC_DAIFMT_I2S:
  407. iface |= R01_SFORI_I2S;
  408. break;
  409. case SND_SOC_DAIFMT_LSB:
  410. iface |= R01_SFORI_LSB16;
  411. break;
  412. case SND_SOC_DAIFMT_MSB:
  413. iface |= R01_SFORI_MSB;
  414. }
  415. /* DATAI is slave only, so this has to be slave */
  416. if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
  417. return -EINVAL;
  418. uda1380_write(codec, UDA1380_IFACE, iface);
  419. return 0;
  420. }
  421. static int uda1380_set_dai_fmt_capture(struct snd_soc_dai *codec_dai,
  422. unsigned int fmt)
  423. {
  424. struct snd_soc_codec *codec = codec_dai->codec;
  425. int iface;
  426. /* set up DAI based upon fmt */
  427. iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
  428. iface &= ~(R01_SIM | R01_SFORO_MASK);
  429. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  430. case SND_SOC_DAIFMT_I2S:
  431. iface |= R01_SFORO_I2S;
  432. break;
  433. case SND_SOC_DAIFMT_LSB:
  434. iface |= R01_SFORO_LSB16;
  435. break;
  436. case SND_SOC_DAIFMT_MSB:
  437. iface |= R01_SFORO_MSB;
  438. }
  439. if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM)
  440. iface |= R01_SIM;
  441. uda1380_write(codec, UDA1380_IFACE, iface);
  442. return 0;
  443. }
  444. static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd,
  445. struct snd_soc_dai *dai)
  446. {
  447. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  448. struct snd_soc_codec *codec = rtd->codec;
  449. struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
  450. int mixer = uda1380_read_reg_cache(codec, UDA1380_MIXER);
  451. switch (cmd) {
  452. case SNDRV_PCM_TRIGGER_START:
  453. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  454. uda1380_write_reg_cache(codec, UDA1380_MIXER,
  455. mixer & ~R14_SILENCE);
  456. schedule_work(&uda1380->work);
  457. break;
  458. case SNDRV_PCM_TRIGGER_STOP:
  459. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  460. uda1380_write_reg_cache(codec, UDA1380_MIXER,
  461. mixer | R14_SILENCE);
  462. schedule_work(&uda1380->work);
  463. break;
  464. }
  465. return 0;
  466. }
  467. static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream,
  468. struct snd_pcm_hw_params *params,
  469. struct snd_soc_dai *dai)
  470. {
  471. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  472. struct snd_soc_codec *codec = rtd->codec;
  473. u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
  474. /* set WSPLL power and divider if running from this clock */
  475. if (clk & R00_DAC_CLK) {
  476. int rate = params_rate(params);
  477. u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
  478. clk &= ~0x3; /* clear SEL_LOOP_DIV */
  479. switch (rate) {
  480. case 6250 ... 12500:
  481. clk |= 0x0;
  482. break;
  483. case 12501 ... 25000:
  484. clk |= 0x1;
  485. break;
  486. case 25001 ... 50000:
  487. clk |= 0x2;
  488. break;
  489. case 50001 ... 100000:
  490. clk |= 0x3;
  491. break;
  492. }
  493. uda1380_write(codec, UDA1380_PM, R02_PON_PLL | pm);
  494. }
  495. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  496. clk |= R00_EN_DAC | R00_EN_INT;
  497. else
  498. clk |= R00_EN_ADC | R00_EN_DEC;
  499. uda1380_write(codec, UDA1380_CLK, clk);
  500. return 0;
  501. }
  502. static void uda1380_pcm_shutdown(struct snd_pcm_substream *substream,
  503. struct snd_soc_dai *dai)
  504. {
  505. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  506. struct snd_soc_codec *codec = rtd->codec;
  507. u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
  508. /* shut down WSPLL power if running from this clock */
  509. if (clk & R00_DAC_CLK) {
  510. u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
  511. uda1380_write(codec, UDA1380_PM, ~R02_PON_PLL & pm);
  512. }
  513. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  514. clk &= ~(R00_EN_DAC | R00_EN_INT);
  515. else
  516. clk &= ~(R00_EN_ADC | R00_EN_DEC);
  517. uda1380_write(codec, UDA1380_CLK, clk);
  518. }
  519. static int uda1380_set_bias_level(struct snd_soc_codec *codec,
  520. enum snd_soc_bias_level level)
  521. {
  522. int pm = uda1380_read_reg_cache(codec, UDA1380_PM);
  523. int reg;
  524. struct uda1380_platform_data *pdata = codec->dev->platform_data;
  525. if (codec->dapm.bias_level == level)
  526. return 0;
  527. switch (level) {
  528. case SND_SOC_BIAS_ON:
  529. case SND_SOC_BIAS_PREPARE:
  530. /* ADC, DAC on */
  531. uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm);
  532. break;
  533. case SND_SOC_BIAS_STANDBY:
  534. if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
  535. if (gpio_is_valid(pdata->gpio_power)) {
  536. gpio_set_value(pdata->gpio_power, 1);
  537. mdelay(1);
  538. uda1380_reset(codec);
  539. }
  540. uda1380_sync_cache(codec);
  541. }
  542. uda1380_write(codec, UDA1380_PM, 0x0);
  543. break;
  544. case SND_SOC_BIAS_OFF:
  545. if (!gpio_is_valid(pdata->gpio_power))
  546. break;
  547. gpio_set_value(pdata->gpio_power, 0);
  548. /* Mark mixer regs cache dirty to sync them with
  549. * codec regs on power on.
  550. */
  551. for (reg = UDA1380_MVOL; reg < UDA1380_CACHEREGNUM; reg++)
  552. set_bit(reg - 0x10, &uda1380_cache_dirty);
  553. }
  554. codec->dapm.bias_level = level;
  555. return 0;
  556. }
  557. #define UDA1380_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
  558. SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
  559. SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
  560. static struct snd_soc_dai_ops uda1380_dai_ops = {
  561. .hw_params = uda1380_pcm_hw_params,
  562. .shutdown = uda1380_pcm_shutdown,
  563. .trigger = uda1380_trigger,
  564. .set_fmt = uda1380_set_dai_fmt_both,
  565. };
  566. static struct snd_soc_dai_ops uda1380_dai_ops_playback = {
  567. .hw_params = uda1380_pcm_hw_params,
  568. .shutdown = uda1380_pcm_shutdown,
  569. .trigger = uda1380_trigger,
  570. .set_fmt = uda1380_set_dai_fmt_playback,
  571. };
  572. static struct snd_soc_dai_ops uda1380_dai_ops_capture = {
  573. .hw_params = uda1380_pcm_hw_params,
  574. .shutdown = uda1380_pcm_shutdown,
  575. .trigger = uda1380_trigger,
  576. .set_fmt = uda1380_set_dai_fmt_capture,
  577. };
  578. static struct snd_soc_dai_driver uda1380_dai[] = {
  579. {
  580. .name = "uda1380-hifi",
  581. .playback = {
  582. .stream_name = "Playback",
  583. .channels_min = 1,
  584. .channels_max = 2,
  585. .rates = UDA1380_RATES,
  586. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  587. .capture = {
  588. .stream_name = "Capture",
  589. .channels_min = 1,
  590. .channels_max = 2,
  591. .rates = UDA1380_RATES,
  592. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  593. .ops = &uda1380_dai_ops,
  594. },
  595. { /* playback only - dual interface */
  596. .name = "uda1380-hifi-playback",
  597. .playback = {
  598. .stream_name = "Playback",
  599. .channels_min = 1,
  600. .channels_max = 2,
  601. .rates = UDA1380_RATES,
  602. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  603. },
  604. .ops = &uda1380_dai_ops_playback,
  605. },
  606. { /* capture only - dual interface*/
  607. .name = "uda1380-hifi-capture",
  608. .capture = {
  609. .stream_name = "Capture",
  610. .channels_min = 1,
  611. .channels_max = 2,
  612. .rates = UDA1380_RATES,
  613. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  614. },
  615. .ops = &uda1380_dai_ops_capture,
  616. },
  617. };
  618. static int uda1380_suspend(struct snd_soc_codec *codec, pm_message_t state)
  619. {
  620. uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
  621. return 0;
  622. }
  623. static int uda1380_resume(struct snd_soc_codec *codec)
  624. {
  625. uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  626. return 0;
  627. }
  628. static int uda1380_probe(struct snd_soc_codec *codec)
  629. {
  630. struct uda1380_platform_data *pdata =codec->dev->platform_data;
  631. struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
  632. int ret;
  633. uda1380->codec = codec;
  634. codec->hw_write = (hw_write_t)i2c_master_send;
  635. codec->control_data = uda1380->control_data;
  636. if (!pdata)
  637. return -EINVAL;
  638. if (gpio_is_valid(pdata->gpio_reset)) {
  639. ret = gpio_request(pdata->gpio_reset, "uda1380 reset");
  640. if (ret)
  641. goto err_out;
  642. ret = gpio_direction_output(pdata->gpio_reset, 0);
  643. if (ret)
  644. goto err_gpio_reset_conf;
  645. }
  646. if (gpio_is_valid(pdata->gpio_power)) {
  647. ret = gpio_request(pdata->gpio_power, "uda1380 power");
  648. if (ret)
  649. goto err_gpio;
  650. ret = gpio_direction_output(pdata->gpio_power, 0);
  651. if (ret)
  652. goto err_gpio_power_conf;
  653. } else {
  654. ret = uda1380_reset(codec);
  655. if (ret) {
  656. dev_err(codec->dev, "Failed to issue reset\n");
  657. goto err_reset;
  658. }
  659. }
  660. INIT_WORK(&uda1380->work, uda1380_flush_work);
  661. /* power on device */
  662. uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  663. /* set clock input */
  664. switch (pdata->dac_clk) {
  665. case UDA1380_DAC_CLK_SYSCLK:
  666. uda1380_write_reg_cache(codec, UDA1380_CLK, 0);
  667. break;
  668. case UDA1380_DAC_CLK_WSPLL:
  669. uda1380_write_reg_cache(codec, UDA1380_CLK,
  670. R00_DAC_CLK);
  671. break;
  672. }
  673. snd_soc_add_controls(codec, uda1380_snd_controls,
  674. ARRAY_SIZE(uda1380_snd_controls));
  675. uda1380_add_widgets(codec);
  676. return 0;
  677. err_reset:
  678. err_gpio_power_conf:
  679. if (gpio_is_valid(pdata->gpio_power))
  680. gpio_free(pdata->gpio_power);
  681. err_gpio_reset_conf:
  682. err_gpio:
  683. if (gpio_is_valid(pdata->gpio_reset))
  684. gpio_free(pdata->gpio_reset);
  685. err_out:
  686. return ret;
  687. }
  688. /* power down chip */
  689. static int uda1380_remove(struct snd_soc_codec *codec)
  690. {
  691. struct uda1380_platform_data *pdata =codec->dev->platform_data;
  692. uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
  693. gpio_free(pdata->gpio_reset);
  694. gpio_free(pdata->gpio_power);
  695. return 0;
  696. }
  697. static struct snd_soc_codec_driver soc_codec_dev_uda1380 = {
  698. .probe = uda1380_probe,
  699. .remove = uda1380_remove,
  700. .suspend = uda1380_suspend,
  701. .resume = uda1380_resume,
  702. .read = uda1380_read_reg_cache,
  703. .write = uda1380_write,
  704. .set_bias_level = uda1380_set_bias_level,
  705. .reg_cache_size = ARRAY_SIZE(uda1380_reg),
  706. .reg_word_size = sizeof(u16),
  707. .reg_cache_default = uda1380_reg,
  708. .reg_cache_step = 1,
  709. };
  710. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  711. static __devinit int uda1380_i2c_probe(struct i2c_client *i2c,
  712. const struct i2c_device_id *id)
  713. {
  714. struct uda1380_priv *uda1380;
  715. int ret;
  716. uda1380 = kzalloc(sizeof(struct uda1380_priv), GFP_KERNEL);
  717. if (uda1380 == NULL)
  718. return -ENOMEM;
  719. i2c_set_clientdata(i2c, uda1380);
  720. uda1380->control_data = i2c;
  721. ret = snd_soc_register_codec(&i2c->dev,
  722. &soc_codec_dev_uda1380, uda1380_dai, ARRAY_SIZE(uda1380_dai));
  723. if (ret < 0)
  724. kfree(uda1380);
  725. return ret;
  726. }
  727. static int __devexit uda1380_i2c_remove(struct i2c_client *i2c)
  728. {
  729. snd_soc_unregister_codec(&i2c->dev);
  730. kfree(i2c_get_clientdata(i2c));
  731. return 0;
  732. }
  733. static const struct i2c_device_id uda1380_i2c_id[] = {
  734. { "uda1380", 0 },
  735. { }
  736. };
  737. MODULE_DEVICE_TABLE(i2c, uda1380_i2c_id);
  738. static struct i2c_driver uda1380_i2c_driver = {
  739. .driver = {
  740. .name = "uda1380-codec",
  741. .owner = THIS_MODULE,
  742. },
  743. .probe = uda1380_i2c_probe,
  744. .remove = __devexit_p(uda1380_i2c_remove),
  745. .id_table = uda1380_i2c_id,
  746. };
  747. #endif
  748. static int __init uda1380_modinit(void)
  749. {
  750. int ret;
  751. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  752. ret = i2c_add_driver(&uda1380_i2c_driver);
  753. if (ret != 0)
  754. pr_err("Failed to register UDA1380 I2C driver: %d\n", ret);
  755. #endif
  756. return 0;
  757. }
  758. module_init(uda1380_modinit);
  759. static void __exit uda1380_exit(void)
  760. {
  761. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  762. i2c_del_driver(&uda1380_i2c_driver);
  763. #endif
  764. }
  765. module_exit(uda1380_exit);
  766. MODULE_AUTHOR("Giorgio Padrin");
  767. MODULE_DESCRIPTION("Audio support for codec Philips UDA1380");
  768. MODULE_LICENSE("GPL");