jz4740.c 12 KB

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  1. /*
  2. * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * You should have received a copy of the GNU General Public License along
  9. * with this program; if not, write to the Free Software Foundation, Inc.,
  10. * 675 Mass Ave, Cambridge, MA 02139, USA.
  11. *
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/slab.h>
  17. #include <linux/delay.h>
  18. #include <sound/core.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/initval.h>
  22. #include <sound/soc.h>
  23. #define JZ4740_REG_CODEC_1 0x0
  24. #define JZ4740_REG_CODEC_2 0x1
  25. #define JZ4740_CODEC_1_LINE_ENABLE BIT(29)
  26. #define JZ4740_CODEC_1_MIC_ENABLE BIT(28)
  27. #define JZ4740_CODEC_1_SW1_ENABLE BIT(27)
  28. #define JZ4740_CODEC_1_ADC_ENABLE BIT(26)
  29. #define JZ4740_CODEC_1_SW2_ENABLE BIT(25)
  30. #define JZ4740_CODEC_1_DAC_ENABLE BIT(24)
  31. #define JZ4740_CODEC_1_VREF_DISABLE BIT(20)
  32. #define JZ4740_CODEC_1_VREF_AMP_DISABLE BIT(19)
  33. #define JZ4740_CODEC_1_VREF_PULLDOWN BIT(18)
  34. #define JZ4740_CODEC_1_VREF_LOW_CURRENT BIT(17)
  35. #define JZ4740_CODEC_1_VREF_HIGH_CURRENT BIT(16)
  36. #define JZ4740_CODEC_1_HEADPHONE_DISABLE BIT(14)
  37. #define JZ4740_CODEC_1_HEADPHONE_AMP_CHANGE_ANY BIT(13)
  38. #define JZ4740_CODEC_1_HEADPHONE_CHARGE BIT(12)
  39. #define JZ4740_CODEC_1_HEADPHONE_PULLDOWN (BIT(11) | BIT(10))
  40. #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M BIT(9)
  41. #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN BIT(8)
  42. #define JZ4740_CODEC_1_SUSPEND BIT(1)
  43. #define JZ4740_CODEC_1_RESET BIT(0)
  44. #define JZ4740_CODEC_1_LINE_ENABLE_OFFSET 29
  45. #define JZ4740_CODEC_1_MIC_ENABLE_OFFSET 28
  46. #define JZ4740_CODEC_1_SW1_ENABLE_OFFSET 27
  47. #define JZ4740_CODEC_1_ADC_ENABLE_OFFSET 26
  48. #define JZ4740_CODEC_1_SW2_ENABLE_OFFSET 25
  49. #define JZ4740_CODEC_1_DAC_ENABLE_OFFSET 24
  50. #define JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET 14
  51. #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET 8
  52. #define JZ4740_CODEC_2_INPUT_VOLUME_MASK 0x1f0000
  53. #define JZ4740_CODEC_2_SAMPLE_RATE_MASK 0x000f00
  54. #define JZ4740_CODEC_2_MIC_BOOST_GAIN_MASK 0x000030
  55. #define JZ4740_CODEC_2_HEADPHONE_VOLUME_MASK 0x000003
  56. #define JZ4740_CODEC_2_INPUT_VOLUME_OFFSET 16
  57. #define JZ4740_CODEC_2_SAMPLE_RATE_OFFSET 8
  58. #define JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET 4
  59. #define JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET 0
  60. static const uint32_t jz4740_codec_regs[] = {
  61. 0x021b2302, 0x00170803,
  62. };
  63. struct jz4740_codec {
  64. void __iomem *base;
  65. struct resource *mem;
  66. };
  67. static unsigned int jz4740_codec_read(struct snd_soc_codec *codec,
  68. unsigned int reg)
  69. {
  70. struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec);
  71. return readl(jz4740_codec->base + (reg << 2));
  72. }
  73. static int jz4740_codec_write(struct snd_soc_codec *codec, unsigned int reg,
  74. unsigned int val)
  75. {
  76. struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec);
  77. u32 *cache = codec->reg_cache;
  78. cache[reg] = val;
  79. writel(val, jz4740_codec->base + (reg << 2));
  80. return 0;
  81. }
  82. static const struct snd_kcontrol_new jz4740_codec_controls[] = {
  83. SOC_SINGLE("Master Playback Volume", JZ4740_REG_CODEC_2,
  84. JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET, 3, 0),
  85. SOC_SINGLE("Master Capture Volume", JZ4740_REG_CODEC_2,
  86. JZ4740_CODEC_2_INPUT_VOLUME_OFFSET, 31, 0),
  87. SOC_SINGLE("Master Playback Switch", JZ4740_REG_CODEC_1,
  88. JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET, 1, 1),
  89. SOC_SINGLE("Mic Capture Volume", JZ4740_REG_CODEC_2,
  90. JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET, 3, 0),
  91. };
  92. static const struct snd_kcontrol_new jz4740_codec_output_controls[] = {
  93. SOC_DAPM_SINGLE("Bypass Switch", JZ4740_REG_CODEC_1,
  94. JZ4740_CODEC_1_SW1_ENABLE_OFFSET, 1, 0),
  95. SOC_DAPM_SINGLE("DAC Switch", JZ4740_REG_CODEC_1,
  96. JZ4740_CODEC_1_SW2_ENABLE_OFFSET, 1, 0),
  97. };
  98. static const struct snd_kcontrol_new jz4740_codec_input_controls[] = {
  99. SOC_DAPM_SINGLE("Line Capture Switch", JZ4740_REG_CODEC_1,
  100. JZ4740_CODEC_1_LINE_ENABLE_OFFSET, 1, 0),
  101. SOC_DAPM_SINGLE("Mic Capture Switch", JZ4740_REG_CODEC_1,
  102. JZ4740_CODEC_1_MIC_ENABLE_OFFSET, 1, 0),
  103. };
  104. static const struct snd_soc_dapm_widget jz4740_codec_dapm_widgets[] = {
  105. SND_SOC_DAPM_ADC("ADC", "Capture", JZ4740_REG_CODEC_1,
  106. JZ4740_CODEC_1_ADC_ENABLE_OFFSET, 0),
  107. SND_SOC_DAPM_DAC("DAC", "Playback", JZ4740_REG_CODEC_1,
  108. JZ4740_CODEC_1_DAC_ENABLE_OFFSET, 0),
  109. SND_SOC_DAPM_MIXER("Output Mixer", JZ4740_REG_CODEC_1,
  110. JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET, 1,
  111. jz4740_codec_output_controls,
  112. ARRAY_SIZE(jz4740_codec_output_controls)),
  113. SND_SOC_DAPM_MIXER_NAMED_CTL("Input Mixer", SND_SOC_NOPM, 0, 0,
  114. jz4740_codec_input_controls,
  115. ARRAY_SIZE(jz4740_codec_input_controls)),
  116. SND_SOC_DAPM_MIXER("Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),
  117. SND_SOC_DAPM_OUTPUT("LOUT"),
  118. SND_SOC_DAPM_OUTPUT("ROUT"),
  119. SND_SOC_DAPM_INPUT("MIC"),
  120. SND_SOC_DAPM_INPUT("LIN"),
  121. SND_SOC_DAPM_INPUT("RIN"),
  122. };
  123. static const struct snd_soc_dapm_route jz4740_codec_dapm_routes[] = {
  124. {"Line Input", NULL, "LIN"},
  125. {"Line Input", NULL, "RIN"},
  126. {"Input Mixer", "Line Capture Switch", "Line Input"},
  127. {"Input Mixer", "Mic Capture Switch", "MIC"},
  128. {"ADC", NULL, "Input Mixer"},
  129. {"Output Mixer", "Bypass Switch", "Input Mixer"},
  130. {"Output Mixer", "DAC Switch", "DAC"},
  131. {"LOUT", NULL, "Output Mixer"},
  132. {"ROUT", NULL, "Output Mixer"},
  133. };
  134. static int jz4740_codec_hw_params(struct snd_pcm_substream *substream,
  135. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  136. {
  137. uint32_t val;
  138. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  139. struct snd_soc_codec *codec =rtd->codec;
  140. switch (params_rate(params)) {
  141. case 8000:
  142. val = 0;
  143. break;
  144. case 11025:
  145. val = 1;
  146. break;
  147. case 12000:
  148. val = 2;
  149. break;
  150. case 16000:
  151. val = 3;
  152. break;
  153. case 22050:
  154. val = 4;
  155. break;
  156. case 24000:
  157. val = 5;
  158. break;
  159. case 32000:
  160. val = 6;
  161. break;
  162. case 44100:
  163. val = 7;
  164. break;
  165. case 48000:
  166. val = 8;
  167. break;
  168. default:
  169. return -EINVAL;
  170. }
  171. val <<= JZ4740_CODEC_2_SAMPLE_RATE_OFFSET;
  172. snd_soc_update_bits(codec, JZ4740_REG_CODEC_2,
  173. JZ4740_CODEC_2_SAMPLE_RATE_MASK, val);
  174. return 0;
  175. }
  176. static struct snd_soc_dai_ops jz4740_codec_dai_ops = {
  177. .hw_params = jz4740_codec_hw_params,
  178. };
  179. static struct snd_soc_dai_driver jz4740_codec_dai = {
  180. .name = "jz4740-hifi",
  181. .playback = {
  182. .stream_name = "Playback",
  183. .channels_min = 2,
  184. .channels_max = 2,
  185. .rates = SNDRV_PCM_RATE_8000_48000,
  186. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
  187. },
  188. .capture = {
  189. .stream_name = "Capture",
  190. .channels_min = 2,
  191. .channels_max = 2,
  192. .rates = SNDRV_PCM_RATE_8000_48000,
  193. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
  194. },
  195. .ops = &jz4740_codec_dai_ops,
  196. .symmetric_rates = 1,
  197. };
  198. static void jz4740_codec_wakeup(struct snd_soc_codec *codec)
  199. {
  200. int i;
  201. uint32_t *cache = codec->reg_cache;
  202. snd_soc_update_bits(codec, JZ4740_REG_CODEC_1,
  203. JZ4740_CODEC_1_RESET, JZ4740_CODEC_1_RESET);
  204. udelay(2);
  205. snd_soc_update_bits(codec, JZ4740_REG_CODEC_1,
  206. JZ4740_CODEC_1_SUSPEND | JZ4740_CODEC_1_RESET, 0);
  207. for (i = 0; i < ARRAY_SIZE(jz4740_codec_regs); ++i)
  208. jz4740_codec_write(codec, i, cache[i]);
  209. }
  210. static int jz4740_codec_set_bias_level(struct snd_soc_codec *codec,
  211. enum snd_soc_bias_level level)
  212. {
  213. unsigned int mask;
  214. unsigned int value;
  215. switch (level) {
  216. case SND_SOC_BIAS_ON:
  217. break;
  218. case SND_SOC_BIAS_PREPARE:
  219. mask = JZ4740_CODEC_1_VREF_DISABLE |
  220. JZ4740_CODEC_1_VREF_AMP_DISABLE |
  221. JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
  222. value = 0;
  223. snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, mask, value);
  224. break;
  225. case SND_SOC_BIAS_STANDBY:
  226. /* The only way to clear the suspend flag is to reset the codec */
  227. if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
  228. jz4740_codec_wakeup(codec);
  229. mask = JZ4740_CODEC_1_VREF_DISABLE |
  230. JZ4740_CODEC_1_VREF_AMP_DISABLE |
  231. JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
  232. value = JZ4740_CODEC_1_VREF_DISABLE |
  233. JZ4740_CODEC_1_VREF_AMP_DISABLE |
  234. JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
  235. snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, mask, value);
  236. break;
  237. case SND_SOC_BIAS_OFF:
  238. mask = JZ4740_CODEC_1_SUSPEND;
  239. value = JZ4740_CODEC_1_SUSPEND;
  240. snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, mask, value);
  241. break;
  242. default:
  243. break;
  244. }
  245. codec->dapm.bias_level = level;
  246. return 0;
  247. }
  248. static int jz4740_codec_dev_probe(struct snd_soc_codec *codec)
  249. {
  250. snd_soc_update_bits(codec, JZ4740_REG_CODEC_1,
  251. JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE);
  252. jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  253. return 0;
  254. }
  255. static int jz4740_codec_dev_remove(struct snd_soc_codec *codec)
  256. {
  257. jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
  258. return 0;
  259. }
  260. #ifdef CONFIG_PM_SLEEP
  261. static int jz4740_codec_suspend(struct snd_soc_codec *codec, pm_message_t state)
  262. {
  263. return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
  264. }
  265. static int jz4740_codec_resume(struct snd_soc_codec *codec)
  266. {
  267. return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  268. }
  269. #else
  270. #define jz4740_codec_suspend NULL
  271. #define jz4740_codec_resume NULL
  272. #endif
  273. static struct snd_soc_codec_driver soc_codec_dev_jz4740_codec = {
  274. .probe = jz4740_codec_dev_probe,
  275. .remove = jz4740_codec_dev_remove,
  276. .suspend = jz4740_codec_suspend,
  277. .resume = jz4740_codec_resume,
  278. .read = jz4740_codec_read,
  279. .write = jz4740_codec_write,
  280. .set_bias_level = jz4740_codec_set_bias_level,
  281. .reg_cache_default = jz4740_codec_regs,
  282. .reg_word_size = sizeof(u32),
  283. .reg_cache_size = 2,
  284. .controls = jz4740_codec_controls,
  285. .num_controls = ARRAY_SIZE(jz4740_codec_controls),
  286. .dapm_widgets = jz4740_codec_dapm_widgets,
  287. .num_dapm_widgets = ARRAY_SIZE(jz4740_codec_dapm_widgets),
  288. .dapm_routes = jz4740_codec_dapm_routes,
  289. .num_dapm_routes = ARRAY_SIZE(jz4740_codec_dapm_routes),
  290. };
  291. static int __devinit jz4740_codec_probe(struct platform_device *pdev)
  292. {
  293. int ret;
  294. struct jz4740_codec *jz4740_codec;
  295. struct resource *mem;
  296. jz4740_codec = kzalloc(sizeof(*jz4740_codec), GFP_KERNEL);
  297. if (!jz4740_codec)
  298. return -ENOMEM;
  299. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  300. if (!mem) {
  301. dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
  302. ret = -ENOENT;
  303. goto err_free_codec;
  304. }
  305. mem = request_mem_region(mem->start, resource_size(mem), pdev->name);
  306. if (!mem) {
  307. dev_err(&pdev->dev, "Failed to request mmio memory region\n");
  308. ret = -EBUSY;
  309. goto err_free_codec;
  310. }
  311. jz4740_codec->base = ioremap(mem->start, resource_size(mem));
  312. if (!jz4740_codec->base) {
  313. dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
  314. ret = -EBUSY;
  315. goto err_release_mem_region;
  316. }
  317. jz4740_codec->mem = mem;
  318. platform_set_drvdata(pdev, jz4740_codec);
  319. ret = snd_soc_register_codec(&pdev->dev,
  320. &soc_codec_dev_jz4740_codec, &jz4740_codec_dai, 1);
  321. if (ret) {
  322. dev_err(&pdev->dev, "Failed to register codec\n");
  323. goto err_iounmap;
  324. }
  325. return 0;
  326. err_iounmap:
  327. iounmap(jz4740_codec->base);
  328. err_release_mem_region:
  329. release_mem_region(mem->start, resource_size(mem));
  330. err_free_codec:
  331. kfree(jz4740_codec);
  332. return ret;
  333. }
  334. static int __devexit jz4740_codec_remove(struct platform_device *pdev)
  335. {
  336. struct jz4740_codec *jz4740_codec = platform_get_drvdata(pdev);
  337. struct resource *mem = jz4740_codec->mem;
  338. snd_soc_unregister_codec(&pdev->dev);
  339. iounmap(jz4740_codec->base);
  340. release_mem_region(mem->start, resource_size(mem));
  341. platform_set_drvdata(pdev, NULL);
  342. kfree(jz4740_codec);
  343. return 0;
  344. }
  345. static struct platform_driver jz4740_codec_driver = {
  346. .probe = jz4740_codec_probe,
  347. .remove = __devexit_p(jz4740_codec_remove),
  348. .driver = {
  349. .name = "jz4740-codec",
  350. .owner = THIS_MODULE,
  351. },
  352. };
  353. static int __init jz4740_codec_init(void)
  354. {
  355. return platform_driver_register(&jz4740_codec_driver);
  356. }
  357. module_init(jz4740_codec_init);
  358. static void __exit jz4740_codec_exit(void)
  359. {
  360. platform_driver_unregister(&jz4740_codec_driver);
  361. }
  362. module_exit(jz4740_codec_exit);
  363. MODULE_DESCRIPTION("JZ4740 SoC internal codec driver");
  364. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  365. MODULE_LICENSE("GPL v2");
  366. MODULE_ALIAS("platform:jz4740-codec");