events.c 39 KB

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  1. /*
  2. * Xen event channels
  3. *
  4. * Xen models interrupts with abstract event channels. Because each
  5. * domain gets 1024 event channels, but NR_IRQ is not that large, we
  6. * must dynamically map irqs<->event channels. The event channels
  7. * interface with the rest of the kernel by defining a xen interrupt
  8. * chip. When an event is received, it is mapped to an irq and sent
  9. * through the normal interrupt processing path.
  10. *
  11. * There are four kinds of events which can be mapped to an event
  12. * channel:
  13. *
  14. * 1. Inter-domain notifications. This includes all the virtual
  15. * device events, since they're driven by front-ends in another domain
  16. * (typically dom0).
  17. * 2. VIRQs, typically used for timers. These are per-cpu events.
  18. * 3. IPIs.
  19. * 4. PIRQs - Hardware interrupts.
  20. *
  21. * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
  22. */
  23. #include <linux/linkage.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/irq.h>
  26. #include <linux/module.h>
  27. #include <linux/string.h>
  28. #include <linux/bootmem.h>
  29. #include <linux/slab.h>
  30. #include <linux/irqnr.h>
  31. #include <linux/pci.h>
  32. #include <asm/desc.h>
  33. #include <asm/ptrace.h>
  34. #include <asm/irq.h>
  35. #include <asm/idle.h>
  36. #include <asm/io_apic.h>
  37. #include <asm/sync_bitops.h>
  38. #include <asm/xen/pci.h>
  39. #include <asm/xen/hypercall.h>
  40. #include <asm/xen/hypervisor.h>
  41. #include <xen/xen.h>
  42. #include <xen/hvm.h>
  43. #include <xen/xen-ops.h>
  44. #include <xen/events.h>
  45. #include <xen/interface/xen.h>
  46. #include <xen/interface/event_channel.h>
  47. #include <xen/interface/hvm/hvm_op.h>
  48. #include <xen/interface/hvm/params.h>
  49. /*
  50. * This lock protects updates to the following mapping and reference-count
  51. * arrays. The lock does not need to be acquired to read the mapping tables.
  52. */
  53. static DEFINE_SPINLOCK(irq_mapping_update_lock);
  54. static LIST_HEAD(xen_irq_list_head);
  55. /* IRQ <-> VIRQ mapping. */
  56. static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
  57. /* IRQ <-> IPI mapping */
  58. static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
  59. /* Interrupt types. */
  60. enum xen_irq_type {
  61. IRQT_UNBOUND = 0,
  62. IRQT_PIRQ,
  63. IRQT_VIRQ,
  64. IRQT_IPI,
  65. IRQT_EVTCHN
  66. };
  67. /*
  68. * Packed IRQ information:
  69. * type - enum xen_irq_type
  70. * event channel - irq->event channel mapping
  71. * cpu - cpu this event channel is bound to
  72. * index - type-specific information:
  73. * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
  74. * guest, or GSI (real passthrough IRQ) of the device.
  75. * VIRQ - virq number
  76. * IPI - IPI vector
  77. * EVTCHN -
  78. */
  79. struct irq_info
  80. {
  81. struct list_head list;
  82. enum xen_irq_type type; /* type */
  83. unsigned irq;
  84. unsigned short evtchn; /* event channel */
  85. unsigned short cpu; /* cpu bound */
  86. union {
  87. unsigned short virq;
  88. enum ipi_vector ipi;
  89. struct {
  90. unsigned short pirq;
  91. unsigned short gsi;
  92. unsigned char vector;
  93. unsigned char flags;
  94. uint16_t domid;
  95. } pirq;
  96. } u;
  97. };
  98. #define PIRQ_NEEDS_EOI (1 << 0)
  99. #define PIRQ_SHAREABLE (1 << 1)
  100. static int *evtchn_to_irq;
  101. static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG],
  102. cpu_evtchn_mask);
  103. /* Xen will never allocate port zero for any purpose. */
  104. #define VALID_EVTCHN(chn) ((chn) != 0)
  105. static struct irq_chip xen_dynamic_chip;
  106. static struct irq_chip xen_percpu_chip;
  107. static struct irq_chip xen_pirq_chip;
  108. static void enable_dynirq(struct irq_data *data);
  109. static void disable_dynirq(struct irq_data *data);
  110. /* Get info for IRQ */
  111. static struct irq_info *info_for_irq(unsigned irq)
  112. {
  113. return irq_get_handler_data(irq);
  114. }
  115. /* Constructors for packed IRQ information. */
  116. static void xen_irq_info_common_init(struct irq_info *info,
  117. unsigned irq,
  118. enum xen_irq_type type,
  119. unsigned short evtchn,
  120. unsigned short cpu)
  121. {
  122. BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
  123. info->type = type;
  124. info->irq = irq;
  125. info->evtchn = evtchn;
  126. info->cpu = cpu;
  127. evtchn_to_irq[evtchn] = irq;
  128. }
  129. static void xen_irq_info_evtchn_init(unsigned irq,
  130. unsigned short evtchn)
  131. {
  132. struct irq_info *info = info_for_irq(irq);
  133. xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
  134. }
  135. static void xen_irq_info_ipi_init(unsigned cpu,
  136. unsigned irq,
  137. unsigned short evtchn,
  138. enum ipi_vector ipi)
  139. {
  140. struct irq_info *info = info_for_irq(irq);
  141. xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
  142. info->u.ipi = ipi;
  143. per_cpu(ipi_to_irq, cpu)[ipi] = irq;
  144. }
  145. static void xen_irq_info_virq_init(unsigned cpu,
  146. unsigned irq,
  147. unsigned short evtchn,
  148. unsigned short virq)
  149. {
  150. struct irq_info *info = info_for_irq(irq);
  151. xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
  152. info->u.virq = virq;
  153. per_cpu(virq_to_irq, cpu)[virq] = irq;
  154. }
  155. static void xen_irq_info_pirq_init(unsigned irq,
  156. unsigned short evtchn,
  157. unsigned short pirq,
  158. unsigned short gsi,
  159. unsigned short vector,
  160. uint16_t domid,
  161. unsigned char flags)
  162. {
  163. struct irq_info *info = info_for_irq(irq);
  164. xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
  165. info->u.pirq.pirq = pirq;
  166. info->u.pirq.gsi = gsi;
  167. info->u.pirq.vector = vector;
  168. info->u.pirq.domid = domid;
  169. info->u.pirq.flags = flags;
  170. }
  171. /*
  172. * Accessors for packed IRQ information.
  173. */
  174. static unsigned int evtchn_from_irq(unsigned irq)
  175. {
  176. if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
  177. return 0;
  178. return info_for_irq(irq)->evtchn;
  179. }
  180. unsigned irq_from_evtchn(unsigned int evtchn)
  181. {
  182. return evtchn_to_irq[evtchn];
  183. }
  184. EXPORT_SYMBOL_GPL(irq_from_evtchn);
  185. static enum ipi_vector ipi_from_irq(unsigned irq)
  186. {
  187. struct irq_info *info = info_for_irq(irq);
  188. BUG_ON(info == NULL);
  189. BUG_ON(info->type != IRQT_IPI);
  190. return info->u.ipi;
  191. }
  192. static unsigned virq_from_irq(unsigned irq)
  193. {
  194. struct irq_info *info = info_for_irq(irq);
  195. BUG_ON(info == NULL);
  196. BUG_ON(info->type != IRQT_VIRQ);
  197. return info->u.virq;
  198. }
  199. static unsigned pirq_from_irq(unsigned irq)
  200. {
  201. struct irq_info *info = info_for_irq(irq);
  202. BUG_ON(info == NULL);
  203. BUG_ON(info->type != IRQT_PIRQ);
  204. return info->u.pirq.pirq;
  205. }
  206. static enum xen_irq_type type_from_irq(unsigned irq)
  207. {
  208. return info_for_irq(irq)->type;
  209. }
  210. static unsigned cpu_from_irq(unsigned irq)
  211. {
  212. return info_for_irq(irq)->cpu;
  213. }
  214. static unsigned int cpu_from_evtchn(unsigned int evtchn)
  215. {
  216. int irq = evtchn_to_irq[evtchn];
  217. unsigned ret = 0;
  218. if (irq != -1)
  219. ret = cpu_from_irq(irq);
  220. return ret;
  221. }
  222. static bool pirq_needs_eoi(unsigned irq)
  223. {
  224. struct irq_info *info = info_for_irq(irq);
  225. BUG_ON(info->type != IRQT_PIRQ);
  226. return info->u.pirq.flags & PIRQ_NEEDS_EOI;
  227. }
  228. static inline unsigned long active_evtchns(unsigned int cpu,
  229. struct shared_info *sh,
  230. unsigned int idx)
  231. {
  232. return (sh->evtchn_pending[idx] &
  233. per_cpu(cpu_evtchn_mask, cpu)[idx] &
  234. ~sh->evtchn_mask[idx]);
  235. }
  236. static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
  237. {
  238. int irq = evtchn_to_irq[chn];
  239. BUG_ON(irq == -1);
  240. #ifdef CONFIG_SMP
  241. cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
  242. #endif
  243. clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq)));
  244. set_bit(chn, per_cpu(cpu_evtchn_mask, cpu));
  245. info_for_irq(irq)->cpu = cpu;
  246. }
  247. static void init_evtchn_cpu_bindings(void)
  248. {
  249. int i;
  250. #ifdef CONFIG_SMP
  251. struct irq_info *info;
  252. /* By default all event channels notify CPU#0. */
  253. list_for_each_entry(info, &xen_irq_list_head, list) {
  254. struct irq_desc *desc = irq_to_desc(info->irq);
  255. cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
  256. }
  257. #endif
  258. for_each_possible_cpu(i)
  259. memset(per_cpu(cpu_evtchn_mask, i),
  260. (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
  261. }
  262. static inline void clear_evtchn(int port)
  263. {
  264. struct shared_info *s = HYPERVISOR_shared_info;
  265. sync_clear_bit(port, &s->evtchn_pending[0]);
  266. }
  267. static inline void set_evtchn(int port)
  268. {
  269. struct shared_info *s = HYPERVISOR_shared_info;
  270. sync_set_bit(port, &s->evtchn_pending[0]);
  271. }
  272. static inline int test_evtchn(int port)
  273. {
  274. struct shared_info *s = HYPERVISOR_shared_info;
  275. return sync_test_bit(port, &s->evtchn_pending[0]);
  276. }
  277. /**
  278. * notify_remote_via_irq - send event to remote end of event channel via irq
  279. * @irq: irq of event channel to send event to
  280. *
  281. * Unlike notify_remote_via_evtchn(), this is safe to use across
  282. * save/restore. Notifications on a broken connection are silently
  283. * dropped.
  284. */
  285. void notify_remote_via_irq(int irq)
  286. {
  287. int evtchn = evtchn_from_irq(irq);
  288. if (VALID_EVTCHN(evtchn))
  289. notify_remote_via_evtchn(evtchn);
  290. }
  291. EXPORT_SYMBOL_GPL(notify_remote_via_irq);
  292. static void mask_evtchn(int port)
  293. {
  294. struct shared_info *s = HYPERVISOR_shared_info;
  295. sync_set_bit(port, &s->evtchn_mask[0]);
  296. }
  297. static void unmask_evtchn(int port)
  298. {
  299. struct shared_info *s = HYPERVISOR_shared_info;
  300. unsigned int cpu = get_cpu();
  301. BUG_ON(!irqs_disabled());
  302. /* Slow path (hypercall) if this is a non-local port. */
  303. if (unlikely(cpu != cpu_from_evtchn(port))) {
  304. struct evtchn_unmask unmask = { .port = port };
  305. (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
  306. } else {
  307. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  308. sync_clear_bit(port, &s->evtchn_mask[0]);
  309. /*
  310. * The following is basically the equivalent of
  311. * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
  312. * the interrupt edge' if the channel is masked.
  313. */
  314. if (sync_test_bit(port, &s->evtchn_pending[0]) &&
  315. !sync_test_and_set_bit(port / BITS_PER_LONG,
  316. &vcpu_info->evtchn_pending_sel))
  317. vcpu_info->evtchn_upcall_pending = 1;
  318. }
  319. put_cpu();
  320. }
  321. static void xen_irq_init(unsigned irq)
  322. {
  323. struct irq_info *info;
  324. #ifdef CONFIG_SMP
  325. struct irq_desc *desc = irq_to_desc(irq);
  326. /* By default all event channels notify CPU#0. */
  327. cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
  328. #endif
  329. info = kzalloc(sizeof(*info), GFP_KERNEL);
  330. if (info == NULL)
  331. panic("Unable to allocate metadata for IRQ%d\n", irq);
  332. info->type = IRQT_UNBOUND;
  333. irq_set_handler_data(irq, info);
  334. list_add_tail(&info->list, &xen_irq_list_head);
  335. }
  336. static int __must_check xen_allocate_irq_dynamic(void)
  337. {
  338. int first = 0;
  339. int irq;
  340. #ifdef CONFIG_X86_IO_APIC
  341. /*
  342. * For an HVM guest or domain 0 which see "real" (emulated or
  343. * actual respectively) GSIs we allocate dynamic IRQs
  344. * e.g. those corresponding to event channels or MSIs
  345. * etc. from the range above those "real" GSIs to avoid
  346. * collisions.
  347. */
  348. if (xen_initial_domain() || xen_hvm_domain())
  349. first = get_nr_irqs_gsi();
  350. #endif
  351. irq = irq_alloc_desc_from(first, -1);
  352. xen_irq_init(irq);
  353. return irq;
  354. }
  355. static int __must_check xen_allocate_irq_gsi(unsigned gsi)
  356. {
  357. int irq;
  358. /*
  359. * A PV guest has no concept of a GSI (since it has no ACPI
  360. * nor access to/knowledge of the physical APICs). Therefore
  361. * all IRQs are dynamically allocated from the entire IRQ
  362. * space.
  363. */
  364. if (xen_pv_domain() && !xen_initial_domain())
  365. return xen_allocate_irq_dynamic();
  366. /* Legacy IRQ descriptors are already allocated by the arch. */
  367. if (gsi < NR_IRQS_LEGACY)
  368. irq = gsi;
  369. else
  370. irq = irq_alloc_desc_at(gsi, -1);
  371. xen_irq_init(irq);
  372. return irq;
  373. }
  374. static void xen_free_irq(unsigned irq)
  375. {
  376. struct irq_info *info = irq_get_handler_data(irq);
  377. list_del(&info->list);
  378. irq_set_handler_data(irq, NULL);
  379. kfree(info);
  380. /* Legacy IRQ descriptors are managed by the arch. */
  381. if (irq < NR_IRQS_LEGACY)
  382. return;
  383. irq_free_desc(irq);
  384. }
  385. static void pirq_query_unmask(int irq)
  386. {
  387. struct physdev_irq_status_query irq_status;
  388. struct irq_info *info = info_for_irq(irq);
  389. BUG_ON(info->type != IRQT_PIRQ);
  390. irq_status.irq = pirq_from_irq(irq);
  391. if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
  392. irq_status.flags = 0;
  393. info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
  394. if (irq_status.flags & XENIRQSTAT_needs_eoi)
  395. info->u.pirq.flags |= PIRQ_NEEDS_EOI;
  396. }
  397. static bool probing_irq(int irq)
  398. {
  399. struct irq_desc *desc = irq_to_desc(irq);
  400. return desc && desc->action == NULL;
  401. }
  402. static void eoi_pirq(struct irq_data *data)
  403. {
  404. int evtchn = evtchn_from_irq(data->irq);
  405. struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
  406. int rc = 0;
  407. irq_move_irq(data);
  408. if (VALID_EVTCHN(evtchn))
  409. clear_evtchn(evtchn);
  410. if (pirq_needs_eoi(data->irq)) {
  411. rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
  412. WARN_ON(rc);
  413. }
  414. }
  415. static void mask_ack_pirq(struct irq_data *data)
  416. {
  417. disable_dynirq(data);
  418. eoi_pirq(data);
  419. }
  420. static unsigned int __startup_pirq(unsigned int irq)
  421. {
  422. struct evtchn_bind_pirq bind_pirq;
  423. struct irq_info *info = info_for_irq(irq);
  424. int evtchn = evtchn_from_irq(irq);
  425. int rc;
  426. BUG_ON(info->type != IRQT_PIRQ);
  427. if (VALID_EVTCHN(evtchn))
  428. goto out;
  429. bind_pirq.pirq = pirq_from_irq(irq);
  430. /* NB. We are happy to share unless we are probing. */
  431. bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
  432. BIND_PIRQ__WILL_SHARE : 0;
  433. rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
  434. if (rc != 0) {
  435. if (!probing_irq(irq))
  436. printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
  437. irq);
  438. return 0;
  439. }
  440. evtchn = bind_pirq.port;
  441. pirq_query_unmask(irq);
  442. evtchn_to_irq[evtchn] = irq;
  443. bind_evtchn_to_cpu(evtchn, 0);
  444. info->evtchn = evtchn;
  445. out:
  446. unmask_evtchn(evtchn);
  447. eoi_pirq(irq_get_irq_data(irq));
  448. return 0;
  449. }
  450. static unsigned int startup_pirq(struct irq_data *data)
  451. {
  452. return __startup_pirq(data->irq);
  453. }
  454. static void shutdown_pirq(struct irq_data *data)
  455. {
  456. struct evtchn_close close;
  457. unsigned int irq = data->irq;
  458. struct irq_info *info = info_for_irq(irq);
  459. int evtchn = evtchn_from_irq(irq);
  460. BUG_ON(info->type != IRQT_PIRQ);
  461. if (!VALID_EVTCHN(evtchn))
  462. return;
  463. mask_evtchn(evtchn);
  464. close.port = evtchn;
  465. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  466. BUG();
  467. bind_evtchn_to_cpu(evtchn, 0);
  468. evtchn_to_irq[evtchn] = -1;
  469. info->evtchn = 0;
  470. }
  471. static void enable_pirq(struct irq_data *data)
  472. {
  473. startup_pirq(data);
  474. }
  475. static void disable_pirq(struct irq_data *data)
  476. {
  477. disable_dynirq(data);
  478. }
  479. static int find_irq_by_gsi(unsigned gsi)
  480. {
  481. struct irq_info *info;
  482. list_for_each_entry(info, &xen_irq_list_head, list) {
  483. if (info->type != IRQT_PIRQ)
  484. continue;
  485. if (info->u.pirq.gsi == gsi)
  486. return info->irq;
  487. }
  488. return -1;
  489. }
  490. int xen_allocate_pirq_gsi(unsigned gsi)
  491. {
  492. return gsi;
  493. }
  494. /*
  495. * Do not make any assumptions regarding the relationship between the
  496. * IRQ number returned here and the Xen pirq argument.
  497. *
  498. * Note: We don't assign an event channel until the irq actually started
  499. * up. Return an existing irq if we've already got one for the gsi.
  500. *
  501. * Shareable implies level triggered, not shareable implies edge
  502. * triggered here.
  503. */
  504. int xen_bind_pirq_gsi_to_irq(unsigned gsi,
  505. unsigned pirq, int shareable, char *name)
  506. {
  507. int irq = -1;
  508. struct physdev_irq irq_op;
  509. spin_lock(&irq_mapping_update_lock);
  510. irq = find_irq_by_gsi(gsi);
  511. if (irq != -1) {
  512. printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
  513. irq, gsi);
  514. goto out; /* XXX need refcount? */
  515. }
  516. irq = xen_allocate_irq_gsi(gsi);
  517. if (irq < 0)
  518. goto out;
  519. irq_op.irq = irq;
  520. irq_op.vector = 0;
  521. /* Only the privileged domain can do this. For non-priv, the pcifront
  522. * driver provides a PCI bus that does the call to do exactly
  523. * this in the priv domain. */
  524. if (xen_initial_domain() &&
  525. HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
  526. xen_free_irq(irq);
  527. irq = -ENOSPC;
  528. goto out;
  529. }
  530. xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector, DOMID_SELF,
  531. shareable ? PIRQ_SHAREABLE : 0);
  532. pirq_query_unmask(irq);
  533. /* We try to use the handler with the appropriate semantic for the
  534. * type of interrupt: if the interrupt is an edge triggered
  535. * interrupt we use handle_edge_irq.
  536. *
  537. * On the other hand if the interrupt is level triggered we use
  538. * handle_fasteoi_irq like the native code does for this kind of
  539. * interrupts.
  540. *
  541. * Depending on the Xen version, pirq_needs_eoi might return true
  542. * not only for level triggered interrupts but for edge triggered
  543. * interrupts too. In any case Xen always honors the eoi mechanism,
  544. * not injecting any more pirqs of the same kind if the first one
  545. * hasn't received an eoi yet. Therefore using the fasteoi handler
  546. * is the right choice either way.
  547. */
  548. if (shareable)
  549. irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
  550. handle_fasteoi_irq, name);
  551. else
  552. irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
  553. handle_edge_irq, name);
  554. out:
  555. spin_unlock(&irq_mapping_update_lock);
  556. return irq;
  557. }
  558. #ifdef CONFIG_PCI_MSI
  559. int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
  560. {
  561. int rc;
  562. struct physdev_get_free_pirq op_get_free_pirq;
  563. op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
  564. rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
  565. WARN_ONCE(rc == -ENOSYS,
  566. "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
  567. return rc ? -1 : op_get_free_pirq.pirq;
  568. }
  569. int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
  570. int pirq, int vector, const char *name,
  571. domid_t domid)
  572. {
  573. int irq, ret;
  574. spin_lock(&irq_mapping_update_lock);
  575. irq = xen_allocate_irq_dynamic();
  576. if (irq == -1)
  577. goto out;
  578. irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
  579. name);
  580. xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, domid, 0);
  581. ret = irq_set_msi_desc(irq, msidesc);
  582. if (ret < 0)
  583. goto error_irq;
  584. out:
  585. spin_unlock(&irq_mapping_update_lock);
  586. return irq;
  587. error_irq:
  588. spin_unlock(&irq_mapping_update_lock);
  589. xen_free_irq(irq);
  590. return -1;
  591. }
  592. #endif
  593. int xen_destroy_irq(int irq)
  594. {
  595. struct irq_desc *desc;
  596. struct physdev_unmap_pirq unmap_irq;
  597. struct irq_info *info = info_for_irq(irq);
  598. int rc = -ENOENT;
  599. spin_lock(&irq_mapping_update_lock);
  600. desc = irq_to_desc(irq);
  601. if (!desc)
  602. goto out;
  603. if (xen_initial_domain()) {
  604. unmap_irq.pirq = info->u.pirq.pirq;
  605. unmap_irq.domid = info->u.pirq.domid;
  606. rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
  607. /* If another domain quits without making the pci_disable_msix
  608. * call, the Xen hypervisor takes care of freeing the PIRQs
  609. * (free_domain_pirqs).
  610. */
  611. if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
  612. printk(KERN_INFO "domain %d does not have %d anymore\n",
  613. info->u.pirq.domid, info->u.pirq.pirq);
  614. else if (rc) {
  615. printk(KERN_WARNING "unmap irq failed %d\n", rc);
  616. goto out;
  617. }
  618. }
  619. xen_free_irq(irq);
  620. out:
  621. spin_unlock(&irq_mapping_update_lock);
  622. return rc;
  623. }
  624. int xen_irq_from_pirq(unsigned pirq)
  625. {
  626. int irq;
  627. struct irq_info *info;
  628. spin_lock(&irq_mapping_update_lock);
  629. list_for_each_entry(info, &xen_irq_list_head, list) {
  630. if (info == NULL || info->type != IRQT_PIRQ)
  631. continue;
  632. irq = info->irq;
  633. if (info->u.pirq.pirq == pirq)
  634. goto out;
  635. }
  636. irq = -1;
  637. out:
  638. spin_unlock(&irq_mapping_update_lock);
  639. return irq;
  640. }
  641. int xen_pirq_from_irq(unsigned irq)
  642. {
  643. return pirq_from_irq(irq);
  644. }
  645. EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
  646. int bind_evtchn_to_irq(unsigned int evtchn)
  647. {
  648. int irq;
  649. spin_lock(&irq_mapping_update_lock);
  650. irq = evtchn_to_irq[evtchn];
  651. if (irq == -1) {
  652. irq = xen_allocate_irq_dynamic();
  653. if (irq == -1)
  654. goto out;
  655. irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
  656. handle_edge_irq, "event");
  657. xen_irq_info_evtchn_init(irq, evtchn);
  658. }
  659. out:
  660. spin_unlock(&irq_mapping_update_lock);
  661. return irq;
  662. }
  663. EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
  664. static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
  665. {
  666. struct evtchn_bind_ipi bind_ipi;
  667. int evtchn, irq;
  668. spin_lock(&irq_mapping_update_lock);
  669. irq = per_cpu(ipi_to_irq, cpu)[ipi];
  670. if (irq == -1) {
  671. irq = xen_allocate_irq_dynamic();
  672. if (irq < 0)
  673. goto out;
  674. irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
  675. handle_percpu_irq, "ipi");
  676. bind_ipi.vcpu = cpu;
  677. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  678. &bind_ipi) != 0)
  679. BUG();
  680. evtchn = bind_ipi.port;
  681. xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
  682. bind_evtchn_to_cpu(evtchn, cpu);
  683. }
  684. out:
  685. spin_unlock(&irq_mapping_update_lock);
  686. return irq;
  687. }
  688. static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
  689. unsigned int remote_port)
  690. {
  691. struct evtchn_bind_interdomain bind_interdomain;
  692. int err;
  693. bind_interdomain.remote_dom = remote_domain;
  694. bind_interdomain.remote_port = remote_port;
  695. err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
  696. &bind_interdomain);
  697. return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
  698. }
  699. int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
  700. {
  701. struct evtchn_bind_virq bind_virq;
  702. int evtchn, irq;
  703. spin_lock(&irq_mapping_update_lock);
  704. irq = per_cpu(virq_to_irq, cpu)[virq];
  705. if (irq == -1) {
  706. irq = xen_allocate_irq_dynamic();
  707. if (irq == -1)
  708. goto out;
  709. irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
  710. handle_percpu_irq, "virq");
  711. bind_virq.virq = virq;
  712. bind_virq.vcpu = cpu;
  713. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  714. &bind_virq) != 0)
  715. BUG();
  716. evtchn = bind_virq.port;
  717. xen_irq_info_virq_init(cpu, irq, evtchn, virq);
  718. bind_evtchn_to_cpu(evtchn, cpu);
  719. }
  720. out:
  721. spin_unlock(&irq_mapping_update_lock);
  722. return irq;
  723. }
  724. static void unbind_from_irq(unsigned int irq)
  725. {
  726. struct evtchn_close close;
  727. int evtchn = evtchn_from_irq(irq);
  728. spin_lock(&irq_mapping_update_lock);
  729. if (VALID_EVTCHN(evtchn)) {
  730. close.port = evtchn;
  731. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  732. BUG();
  733. switch (type_from_irq(irq)) {
  734. case IRQT_VIRQ:
  735. per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
  736. [virq_from_irq(irq)] = -1;
  737. break;
  738. case IRQT_IPI:
  739. per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
  740. [ipi_from_irq(irq)] = -1;
  741. break;
  742. default:
  743. break;
  744. }
  745. /* Closed ports are implicitly re-bound to VCPU0. */
  746. bind_evtchn_to_cpu(evtchn, 0);
  747. evtchn_to_irq[evtchn] = -1;
  748. }
  749. BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
  750. xen_free_irq(irq);
  751. spin_unlock(&irq_mapping_update_lock);
  752. }
  753. int bind_evtchn_to_irqhandler(unsigned int evtchn,
  754. irq_handler_t handler,
  755. unsigned long irqflags,
  756. const char *devname, void *dev_id)
  757. {
  758. int irq, retval;
  759. irq = bind_evtchn_to_irq(evtchn);
  760. if (irq < 0)
  761. return irq;
  762. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  763. if (retval != 0) {
  764. unbind_from_irq(irq);
  765. return retval;
  766. }
  767. return irq;
  768. }
  769. EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
  770. int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
  771. unsigned int remote_port,
  772. irq_handler_t handler,
  773. unsigned long irqflags,
  774. const char *devname,
  775. void *dev_id)
  776. {
  777. int irq, retval;
  778. irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
  779. if (irq < 0)
  780. return irq;
  781. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  782. if (retval != 0) {
  783. unbind_from_irq(irq);
  784. return retval;
  785. }
  786. return irq;
  787. }
  788. EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
  789. int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
  790. irq_handler_t handler,
  791. unsigned long irqflags, const char *devname, void *dev_id)
  792. {
  793. int irq, retval;
  794. irq = bind_virq_to_irq(virq, cpu);
  795. if (irq < 0)
  796. return irq;
  797. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  798. if (retval != 0) {
  799. unbind_from_irq(irq);
  800. return retval;
  801. }
  802. return irq;
  803. }
  804. EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
  805. int bind_ipi_to_irqhandler(enum ipi_vector ipi,
  806. unsigned int cpu,
  807. irq_handler_t handler,
  808. unsigned long irqflags,
  809. const char *devname,
  810. void *dev_id)
  811. {
  812. int irq, retval;
  813. irq = bind_ipi_to_irq(ipi, cpu);
  814. if (irq < 0)
  815. return irq;
  816. irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
  817. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  818. if (retval != 0) {
  819. unbind_from_irq(irq);
  820. return retval;
  821. }
  822. return irq;
  823. }
  824. void unbind_from_irqhandler(unsigned int irq, void *dev_id)
  825. {
  826. free_irq(irq, dev_id);
  827. unbind_from_irq(irq);
  828. }
  829. EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
  830. void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
  831. {
  832. int irq = per_cpu(ipi_to_irq, cpu)[vector];
  833. BUG_ON(irq < 0);
  834. notify_remote_via_irq(irq);
  835. }
  836. irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
  837. {
  838. struct shared_info *sh = HYPERVISOR_shared_info;
  839. int cpu = smp_processor_id();
  840. unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
  841. int i;
  842. unsigned long flags;
  843. static DEFINE_SPINLOCK(debug_lock);
  844. struct vcpu_info *v;
  845. spin_lock_irqsave(&debug_lock, flags);
  846. printk("\nvcpu %d\n ", cpu);
  847. for_each_online_cpu(i) {
  848. int pending;
  849. v = per_cpu(xen_vcpu, i);
  850. pending = (get_irq_regs() && i == cpu)
  851. ? xen_irqs_disabled(get_irq_regs())
  852. : v->evtchn_upcall_mask;
  853. printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
  854. pending, v->evtchn_upcall_pending,
  855. (int)(sizeof(v->evtchn_pending_sel)*2),
  856. v->evtchn_pending_sel);
  857. }
  858. v = per_cpu(xen_vcpu, cpu);
  859. printk("\npending:\n ");
  860. for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
  861. printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
  862. sh->evtchn_pending[i],
  863. i % 8 == 0 ? "\n " : " ");
  864. printk("\nglobal mask:\n ");
  865. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  866. printk("%0*lx%s",
  867. (int)(sizeof(sh->evtchn_mask[0])*2),
  868. sh->evtchn_mask[i],
  869. i % 8 == 0 ? "\n " : " ");
  870. printk("\nglobally unmasked:\n ");
  871. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  872. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  873. sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
  874. i % 8 == 0 ? "\n " : " ");
  875. printk("\nlocal cpu%d mask:\n ", cpu);
  876. for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
  877. printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
  878. cpu_evtchn[i],
  879. i % 8 == 0 ? "\n " : " ");
  880. printk("\nlocally unmasked:\n ");
  881. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
  882. unsigned long pending = sh->evtchn_pending[i]
  883. & ~sh->evtchn_mask[i]
  884. & cpu_evtchn[i];
  885. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  886. pending, i % 8 == 0 ? "\n " : " ");
  887. }
  888. printk("\npending list:\n");
  889. for (i = 0; i < NR_EVENT_CHANNELS; i++) {
  890. if (sync_test_bit(i, sh->evtchn_pending)) {
  891. int word_idx = i / BITS_PER_LONG;
  892. printk(" %d: event %d -> irq %d%s%s%s\n",
  893. cpu_from_evtchn(i), i,
  894. evtchn_to_irq[i],
  895. sync_test_bit(word_idx, &v->evtchn_pending_sel)
  896. ? "" : " l2-clear",
  897. !sync_test_bit(i, sh->evtchn_mask)
  898. ? "" : " globally-masked",
  899. sync_test_bit(i, cpu_evtchn)
  900. ? "" : " locally-masked");
  901. }
  902. }
  903. spin_unlock_irqrestore(&debug_lock, flags);
  904. return IRQ_HANDLED;
  905. }
  906. static DEFINE_PER_CPU(unsigned, xed_nesting_count);
  907. static DEFINE_PER_CPU(unsigned int, current_word_idx);
  908. static DEFINE_PER_CPU(unsigned int, current_bit_idx);
  909. /*
  910. * Mask out the i least significant bits of w
  911. */
  912. #define MASK_LSBS(w, i) (w & ((~0UL) << i))
  913. /*
  914. * Search the CPUs pending events bitmasks. For each one found, map
  915. * the event number to an irq, and feed it into do_IRQ() for
  916. * handling.
  917. *
  918. * Xen uses a two-level bitmap to speed searching. The first level is
  919. * a bitset of words which contain pending event bits. The second
  920. * level is a bitset of pending events themselves.
  921. */
  922. static void __xen_evtchn_do_upcall(void)
  923. {
  924. int start_word_idx, start_bit_idx;
  925. int word_idx, bit_idx;
  926. int i;
  927. int cpu = get_cpu();
  928. struct shared_info *s = HYPERVISOR_shared_info;
  929. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  930. unsigned count;
  931. do {
  932. unsigned long pending_words;
  933. vcpu_info->evtchn_upcall_pending = 0;
  934. if (__this_cpu_inc_return(xed_nesting_count) - 1)
  935. goto out;
  936. #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
  937. /* Clear master flag /before/ clearing selector flag. */
  938. wmb();
  939. #endif
  940. pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
  941. start_word_idx = __this_cpu_read(current_word_idx);
  942. start_bit_idx = __this_cpu_read(current_bit_idx);
  943. word_idx = start_word_idx;
  944. for (i = 0; pending_words != 0; i++) {
  945. unsigned long pending_bits;
  946. unsigned long words;
  947. words = MASK_LSBS(pending_words, word_idx);
  948. /*
  949. * If we masked out all events, wrap to beginning.
  950. */
  951. if (words == 0) {
  952. word_idx = 0;
  953. bit_idx = 0;
  954. continue;
  955. }
  956. word_idx = __ffs(words);
  957. pending_bits = active_evtchns(cpu, s, word_idx);
  958. bit_idx = 0; /* usually scan entire word from start */
  959. if (word_idx == start_word_idx) {
  960. /* We scan the starting word in two parts */
  961. if (i == 0)
  962. /* 1st time: start in the middle */
  963. bit_idx = start_bit_idx;
  964. else
  965. /* 2nd time: mask bits done already */
  966. bit_idx &= (1UL << start_bit_idx) - 1;
  967. }
  968. do {
  969. unsigned long bits;
  970. int port, irq;
  971. struct irq_desc *desc;
  972. bits = MASK_LSBS(pending_bits, bit_idx);
  973. /* If we masked out all events, move on. */
  974. if (bits == 0)
  975. break;
  976. bit_idx = __ffs(bits);
  977. /* Process port. */
  978. port = (word_idx * BITS_PER_LONG) + bit_idx;
  979. irq = evtchn_to_irq[port];
  980. if (irq != -1) {
  981. desc = irq_to_desc(irq);
  982. if (desc)
  983. generic_handle_irq_desc(irq, desc);
  984. }
  985. bit_idx = (bit_idx + 1) % BITS_PER_LONG;
  986. /* Next caller starts at last processed + 1 */
  987. __this_cpu_write(current_word_idx,
  988. bit_idx ? word_idx :
  989. (word_idx+1) % BITS_PER_LONG);
  990. __this_cpu_write(current_bit_idx, bit_idx);
  991. } while (bit_idx != 0);
  992. /* Scan start_l1i twice; all others once. */
  993. if ((word_idx != start_word_idx) || (i != 0))
  994. pending_words &= ~(1UL << word_idx);
  995. word_idx = (word_idx + 1) % BITS_PER_LONG;
  996. }
  997. BUG_ON(!irqs_disabled());
  998. count = __this_cpu_read(xed_nesting_count);
  999. __this_cpu_write(xed_nesting_count, 0);
  1000. } while (count != 1 || vcpu_info->evtchn_upcall_pending);
  1001. out:
  1002. put_cpu();
  1003. }
  1004. void xen_evtchn_do_upcall(struct pt_regs *regs)
  1005. {
  1006. struct pt_regs *old_regs = set_irq_regs(regs);
  1007. exit_idle();
  1008. irq_enter();
  1009. __xen_evtchn_do_upcall();
  1010. irq_exit();
  1011. set_irq_regs(old_regs);
  1012. }
  1013. void xen_hvm_evtchn_do_upcall(void)
  1014. {
  1015. __xen_evtchn_do_upcall();
  1016. }
  1017. EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
  1018. /* Rebind a new event channel to an existing irq. */
  1019. void rebind_evtchn_irq(int evtchn, int irq)
  1020. {
  1021. struct irq_info *info = info_for_irq(irq);
  1022. /* Make sure the irq is masked, since the new event channel
  1023. will also be masked. */
  1024. disable_irq(irq);
  1025. spin_lock(&irq_mapping_update_lock);
  1026. /* After resume the irq<->evtchn mappings are all cleared out */
  1027. BUG_ON(evtchn_to_irq[evtchn] != -1);
  1028. /* Expect irq to have been bound before,
  1029. so there should be a proper type */
  1030. BUG_ON(info->type == IRQT_UNBOUND);
  1031. xen_irq_info_evtchn_init(irq, evtchn);
  1032. spin_unlock(&irq_mapping_update_lock);
  1033. /* new event channels are always bound to cpu 0 */
  1034. irq_set_affinity(irq, cpumask_of(0));
  1035. /* Unmask the event channel. */
  1036. enable_irq(irq);
  1037. }
  1038. /* Rebind an evtchn so that it gets delivered to a specific cpu */
  1039. static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
  1040. {
  1041. struct evtchn_bind_vcpu bind_vcpu;
  1042. int evtchn = evtchn_from_irq(irq);
  1043. if (!VALID_EVTCHN(evtchn))
  1044. return -1;
  1045. /*
  1046. * Events delivered via platform PCI interrupts are always
  1047. * routed to vcpu 0 and hence cannot be rebound.
  1048. */
  1049. if (xen_hvm_domain() && !xen_have_vector_callback)
  1050. return -1;
  1051. /* Send future instances of this interrupt to other vcpu. */
  1052. bind_vcpu.port = evtchn;
  1053. bind_vcpu.vcpu = tcpu;
  1054. /*
  1055. * If this fails, it usually just indicates that we're dealing with a
  1056. * virq or IPI channel, which don't actually need to be rebound. Ignore
  1057. * it, but don't do the xenlinux-level rebind in that case.
  1058. */
  1059. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
  1060. bind_evtchn_to_cpu(evtchn, tcpu);
  1061. return 0;
  1062. }
  1063. static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
  1064. bool force)
  1065. {
  1066. unsigned tcpu = cpumask_first(dest);
  1067. return rebind_irq_to_cpu(data->irq, tcpu);
  1068. }
  1069. int resend_irq_on_evtchn(unsigned int irq)
  1070. {
  1071. int masked, evtchn = evtchn_from_irq(irq);
  1072. struct shared_info *s = HYPERVISOR_shared_info;
  1073. if (!VALID_EVTCHN(evtchn))
  1074. return 1;
  1075. masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
  1076. sync_set_bit(evtchn, s->evtchn_pending);
  1077. if (!masked)
  1078. unmask_evtchn(evtchn);
  1079. return 1;
  1080. }
  1081. static void enable_dynirq(struct irq_data *data)
  1082. {
  1083. int evtchn = evtchn_from_irq(data->irq);
  1084. if (VALID_EVTCHN(evtchn))
  1085. unmask_evtchn(evtchn);
  1086. }
  1087. static void disable_dynirq(struct irq_data *data)
  1088. {
  1089. int evtchn = evtchn_from_irq(data->irq);
  1090. if (VALID_EVTCHN(evtchn))
  1091. mask_evtchn(evtchn);
  1092. }
  1093. static void ack_dynirq(struct irq_data *data)
  1094. {
  1095. int evtchn = evtchn_from_irq(data->irq);
  1096. irq_move_irq(data);
  1097. if (VALID_EVTCHN(evtchn))
  1098. clear_evtchn(evtchn);
  1099. }
  1100. static void mask_ack_dynirq(struct irq_data *data)
  1101. {
  1102. disable_dynirq(data);
  1103. ack_dynirq(data);
  1104. }
  1105. static int retrigger_dynirq(struct irq_data *data)
  1106. {
  1107. int evtchn = evtchn_from_irq(data->irq);
  1108. struct shared_info *sh = HYPERVISOR_shared_info;
  1109. int ret = 0;
  1110. if (VALID_EVTCHN(evtchn)) {
  1111. int masked;
  1112. masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
  1113. sync_set_bit(evtchn, sh->evtchn_pending);
  1114. if (!masked)
  1115. unmask_evtchn(evtchn);
  1116. ret = 1;
  1117. }
  1118. return ret;
  1119. }
  1120. static void restore_pirqs(void)
  1121. {
  1122. int pirq, rc, irq, gsi;
  1123. struct physdev_map_pirq map_irq;
  1124. struct irq_info *info;
  1125. list_for_each_entry(info, &xen_irq_list_head, list) {
  1126. if (info->type != IRQT_PIRQ)
  1127. continue;
  1128. pirq = info->u.pirq.pirq;
  1129. gsi = info->u.pirq.gsi;
  1130. irq = info->irq;
  1131. /* save/restore of PT devices doesn't work, so at this point the
  1132. * only devices present are GSI based emulated devices */
  1133. if (!gsi)
  1134. continue;
  1135. map_irq.domid = DOMID_SELF;
  1136. map_irq.type = MAP_PIRQ_TYPE_GSI;
  1137. map_irq.index = gsi;
  1138. map_irq.pirq = pirq;
  1139. rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
  1140. if (rc) {
  1141. printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
  1142. gsi, irq, pirq, rc);
  1143. xen_free_irq(irq);
  1144. continue;
  1145. }
  1146. printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
  1147. __startup_pirq(irq);
  1148. }
  1149. }
  1150. static void restore_cpu_virqs(unsigned int cpu)
  1151. {
  1152. struct evtchn_bind_virq bind_virq;
  1153. int virq, irq, evtchn;
  1154. for (virq = 0; virq < NR_VIRQS; virq++) {
  1155. if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
  1156. continue;
  1157. BUG_ON(virq_from_irq(irq) != virq);
  1158. /* Get a new binding from Xen. */
  1159. bind_virq.virq = virq;
  1160. bind_virq.vcpu = cpu;
  1161. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  1162. &bind_virq) != 0)
  1163. BUG();
  1164. evtchn = bind_virq.port;
  1165. /* Record the new mapping. */
  1166. xen_irq_info_virq_init(cpu, irq, evtchn, virq);
  1167. bind_evtchn_to_cpu(evtchn, cpu);
  1168. }
  1169. }
  1170. static void restore_cpu_ipis(unsigned int cpu)
  1171. {
  1172. struct evtchn_bind_ipi bind_ipi;
  1173. int ipi, irq, evtchn;
  1174. for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
  1175. if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
  1176. continue;
  1177. BUG_ON(ipi_from_irq(irq) != ipi);
  1178. /* Get a new binding from Xen. */
  1179. bind_ipi.vcpu = cpu;
  1180. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  1181. &bind_ipi) != 0)
  1182. BUG();
  1183. evtchn = bind_ipi.port;
  1184. /* Record the new mapping. */
  1185. xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
  1186. bind_evtchn_to_cpu(evtchn, cpu);
  1187. }
  1188. }
  1189. /* Clear an irq's pending state, in preparation for polling on it */
  1190. void xen_clear_irq_pending(int irq)
  1191. {
  1192. int evtchn = evtchn_from_irq(irq);
  1193. if (VALID_EVTCHN(evtchn))
  1194. clear_evtchn(evtchn);
  1195. }
  1196. EXPORT_SYMBOL(xen_clear_irq_pending);
  1197. void xen_set_irq_pending(int irq)
  1198. {
  1199. int evtchn = evtchn_from_irq(irq);
  1200. if (VALID_EVTCHN(evtchn))
  1201. set_evtchn(evtchn);
  1202. }
  1203. bool xen_test_irq_pending(int irq)
  1204. {
  1205. int evtchn = evtchn_from_irq(irq);
  1206. bool ret = false;
  1207. if (VALID_EVTCHN(evtchn))
  1208. ret = test_evtchn(evtchn);
  1209. return ret;
  1210. }
  1211. /* Poll waiting for an irq to become pending with timeout. In the usual case,
  1212. * the irq will be disabled so it won't deliver an interrupt. */
  1213. void xen_poll_irq_timeout(int irq, u64 timeout)
  1214. {
  1215. evtchn_port_t evtchn = evtchn_from_irq(irq);
  1216. if (VALID_EVTCHN(evtchn)) {
  1217. struct sched_poll poll;
  1218. poll.nr_ports = 1;
  1219. poll.timeout = timeout;
  1220. set_xen_guest_handle(poll.ports, &evtchn);
  1221. if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
  1222. BUG();
  1223. }
  1224. }
  1225. EXPORT_SYMBOL(xen_poll_irq_timeout);
  1226. /* Poll waiting for an irq to become pending. In the usual case, the
  1227. * irq will be disabled so it won't deliver an interrupt. */
  1228. void xen_poll_irq(int irq)
  1229. {
  1230. xen_poll_irq_timeout(irq, 0 /* no timeout */);
  1231. }
  1232. /* Check whether the IRQ line is shared with other guests. */
  1233. int xen_test_irq_shared(int irq)
  1234. {
  1235. struct irq_info *info = info_for_irq(irq);
  1236. struct physdev_irq_status_query irq_status = { .irq = info->u.pirq.pirq };
  1237. if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
  1238. return 0;
  1239. return !(irq_status.flags & XENIRQSTAT_shared);
  1240. }
  1241. EXPORT_SYMBOL_GPL(xen_test_irq_shared);
  1242. void xen_irq_resume(void)
  1243. {
  1244. unsigned int cpu, evtchn;
  1245. struct irq_info *info;
  1246. init_evtchn_cpu_bindings();
  1247. /* New event-channel space is not 'live' yet. */
  1248. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1249. mask_evtchn(evtchn);
  1250. /* No IRQ <-> event-channel mappings. */
  1251. list_for_each_entry(info, &xen_irq_list_head, list)
  1252. info->evtchn = 0; /* zap event-channel binding */
  1253. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1254. evtchn_to_irq[evtchn] = -1;
  1255. for_each_possible_cpu(cpu) {
  1256. restore_cpu_virqs(cpu);
  1257. restore_cpu_ipis(cpu);
  1258. }
  1259. restore_pirqs();
  1260. }
  1261. static struct irq_chip xen_dynamic_chip __read_mostly = {
  1262. .name = "xen-dyn",
  1263. .irq_disable = disable_dynirq,
  1264. .irq_mask = disable_dynirq,
  1265. .irq_unmask = enable_dynirq,
  1266. .irq_ack = ack_dynirq,
  1267. .irq_mask_ack = mask_ack_dynirq,
  1268. .irq_set_affinity = set_affinity_irq,
  1269. .irq_retrigger = retrigger_dynirq,
  1270. };
  1271. static struct irq_chip xen_pirq_chip __read_mostly = {
  1272. .name = "xen-pirq",
  1273. .irq_startup = startup_pirq,
  1274. .irq_shutdown = shutdown_pirq,
  1275. .irq_enable = enable_pirq,
  1276. .irq_disable = disable_pirq,
  1277. .irq_mask = disable_dynirq,
  1278. .irq_unmask = enable_dynirq,
  1279. .irq_ack = eoi_pirq,
  1280. .irq_eoi = eoi_pirq,
  1281. .irq_mask_ack = mask_ack_pirq,
  1282. .irq_set_affinity = set_affinity_irq,
  1283. .irq_retrigger = retrigger_dynirq,
  1284. };
  1285. static struct irq_chip xen_percpu_chip __read_mostly = {
  1286. .name = "xen-percpu",
  1287. .irq_disable = disable_dynirq,
  1288. .irq_mask = disable_dynirq,
  1289. .irq_unmask = enable_dynirq,
  1290. .irq_ack = ack_dynirq,
  1291. };
  1292. int xen_set_callback_via(uint64_t via)
  1293. {
  1294. struct xen_hvm_param a;
  1295. a.domid = DOMID_SELF;
  1296. a.index = HVM_PARAM_CALLBACK_IRQ;
  1297. a.value = via;
  1298. return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
  1299. }
  1300. EXPORT_SYMBOL_GPL(xen_set_callback_via);
  1301. #ifdef CONFIG_XEN_PVHVM
  1302. /* Vector callbacks are better than PCI interrupts to receive event
  1303. * channel notifications because we can receive vector callbacks on any
  1304. * vcpu and we don't need PCI support or APIC interactions. */
  1305. void xen_callback_vector(void)
  1306. {
  1307. int rc;
  1308. uint64_t callback_via;
  1309. if (xen_have_vector_callback) {
  1310. callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
  1311. rc = xen_set_callback_via(callback_via);
  1312. if (rc) {
  1313. printk(KERN_ERR "Request for Xen HVM callback vector"
  1314. " failed.\n");
  1315. xen_have_vector_callback = 0;
  1316. return;
  1317. }
  1318. printk(KERN_INFO "Xen HVM callback vector for event delivery is "
  1319. "enabled\n");
  1320. /* in the restore case the vector has already been allocated */
  1321. if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
  1322. alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
  1323. }
  1324. }
  1325. #else
  1326. void xen_callback_vector(void) {}
  1327. #endif
  1328. void __init xen_init_IRQ(void)
  1329. {
  1330. int i;
  1331. evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
  1332. GFP_KERNEL);
  1333. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1334. evtchn_to_irq[i] = -1;
  1335. init_evtchn_cpu_bindings();
  1336. /* No event channels are 'live' right now. */
  1337. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1338. mask_evtchn(i);
  1339. if (xen_hvm_domain()) {
  1340. xen_callback_vector();
  1341. native_init_IRQ();
  1342. /* pci_xen_hvm_init must be called after native_init_IRQ so that
  1343. * __acpi_register_gsi can point at the right function */
  1344. pci_xen_hvm_init();
  1345. } else {
  1346. irq_ctx_init(smp_processor_id());
  1347. if (xen_initial_domain())
  1348. xen_setup_pirqs();
  1349. }
  1350. }