savagefb.h 10 KB

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  1. /*
  2. * linux/drivers/video/savagefb.h -- S3 Savage Framebuffer Driver
  3. *
  4. * Copyright (c) 2001 Denis Oliver Kropp <dok@convergence.de>
  5. *
  6. * This file is subject to the terms and conditions of the GNU General
  7. * Public License. See the file COPYING in the main directory of this
  8. * archive for more details.
  9. */
  10. #ifndef __SAVAGEFB_H__
  11. #define __SAVAGEFB_H__
  12. #include <linux/i2c.h>
  13. #include <linux/i2c-algo-bit.h>
  14. #include <linux/mutex.h>
  15. #include <video/vga.h>
  16. #include "../edid.h"
  17. #ifdef SAVAGEFB_DEBUG
  18. # define DBG(x) printk (KERN_DEBUG "savagefb: %s\n", (x));
  19. #else
  20. # define DBG(x)
  21. # define SavagePrintRegs(...)
  22. #endif
  23. #define PCI_CHIP_SAVAGE4 0x8a22
  24. #define PCI_CHIP_SAVAGE3D 0x8a20
  25. #define PCI_CHIP_SAVAGE3D_MV 0x8a21
  26. #define PCI_CHIP_SAVAGE2000 0x9102
  27. #define PCI_CHIP_SAVAGE_MX_MV 0x8c10
  28. #define PCI_CHIP_SAVAGE_MX 0x8c11
  29. #define PCI_CHIP_SAVAGE_IX_MV 0x8c12
  30. #define PCI_CHIP_SAVAGE_IX 0x8c13
  31. #define PCI_CHIP_PROSAVAGE_PM 0x8a25
  32. #define PCI_CHIP_PROSAVAGE_KM 0x8a26
  33. #define PCI_CHIP_S3TWISTER_P 0x8d01
  34. #define PCI_CHIP_S3TWISTER_K 0x8d02
  35. #define PCI_CHIP_PROSAVAGE_DDR 0x8d03
  36. #define PCI_CHIP_PROSAVAGE_DDRK 0x8d04
  37. #define PCI_CHIP_SUPSAV_MX128 0x8c22
  38. #define PCI_CHIP_SUPSAV_MX64 0x8c24
  39. #define PCI_CHIP_SUPSAV_MX64C 0x8c26
  40. #define PCI_CHIP_SUPSAV_IX128SDR 0x8c2a
  41. #define PCI_CHIP_SUPSAV_IX128DDR 0x8c2b
  42. #define PCI_CHIP_SUPSAV_IX64SDR 0x8c2c
  43. #define PCI_CHIP_SUPSAV_IX64DDR 0x8c2d
  44. #define PCI_CHIP_SUPSAV_IXCSDR 0x8c2e
  45. #define PCI_CHIP_SUPSAV_IXCDDR 0x8c2f
  46. #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
  47. #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
  48. #define S3_SAVAGE4_SERIES(chip) ((chip>=S3_SAVAGE4) && (chip<=S3_PROSAVAGEDDR))
  49. #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))
  50. #define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) || (chip==S3_PROSAVAGEDDR))
  51. /* Chip tags. These are used to group the adapters into
  52. * related families.
  53. */
  54. typedef enum {
  55. S3_UNKNOWN = 0,
  56. S3_SAVAGE3D,
  57. S3_SAVAGE_MX,
  58. S3_SAVAGE4,
  59. S3_PROSAVAGE,
  60. S3_TWISTER,
  61. S3_PROSAVAGEDDR,
  62. S3_SUPERSAVAGE,
  63. S3_SAVAGE2000,
  64. S3_LAST
  65. } savage_chipset;
  66. #define BIOS_BSIZE 1024
  67. #define BIOS_BASE 0xc0000
  68. #define SAVAGE_NEWMMIO_REGBASE_S3 0x1000000 /* 16MB */
  69. #define SAVAGE_NEWMMIO_REGBASE_S4 0x0000000
  70. #define SAVAGE_NEWMMIO_REGSIZE 0x0080000 /* 512kb */
  71. #define SAVAGE_NEWMMIO_VGABASE 0x8000
  72. #define BASE_FREQ 14318
  73. #define HALF_BASE_FREQ 7159
  74. #define FIFO_CONTROL_REG 0x8200
  75. #define MIU_CONTROL_REG 0x8204
  76. #define STREAMS_TIMEOUT_REG 0x8208
  77. #define MISC_TIMEOUT_REG 0x820c
  78. #define MONO_PAT_0 0xa4e8
  79. #define MONO_PAT_1 0xa4ec
  80. #define MAXFIFO 0x7f00
  81. #define BCI_CMD_NOP 0x40000000
  82. #define BCI_CMD_SETREG 0x96000000
  83. #define BCI_CMD_RECT 0x48000000
  84. #define BCI_CMD_RECT_XP 0x01000000
  85. #define BCI_CMD_RECT_YP 0x02000000
  86. #define BCI_CMD_SEND_COLOR 0x00008000
  87. #define BCI_CMD_DEST_GBD 0x00000000
  88. #define BCI_CMD_SRC_GBD 0x00000020
  89. #define BCI_CMD_SRC_SOLID 0x00000000
  90. #define BCI_CMD_SRC_MONO 0x00000060
  91. #define BCI_CMD_CLIP_NEW 0x00006000
  92. #define BCI_CMD_CLIP_LR 0x00004000
  93. #define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF)
  94. #define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF)
  95. #define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF)
  96. #define BCI_W_H(w, h) (((h) << 16) | ((w) & 0xFFF))
  97. #define BCI_X_Y(x, y) (((y) << 16) | ((x) & 0xFFF))
  98. #define BCI_GBD1 0xE0
  99. #define BCI_GBD2 0xE1
  100. #define BCI_BUFFER_OFFSET 0x10000
  101. #define BCI_SIZE 0x4000
  102. #define BCI_SEND(dw) writel(dw, par->bci_base + par->bci_ptr++)
  103. #define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF)
  104. #define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16))
  105. #define BCI_CMD_SEND_COLOR 0x00008000
  106. #define DISP_CRT 1
  107. #define DISP_LCD 2
  108. #define DISP_DFP 3
  109. struct xtimings {
  110. unsigned int Clock;
  111. unsigned int HDisplay;
  112. unsigned int HSyncStart;
  113. unsigned int HSyncEnd;
  114. unsigned int HTotal;
  115. unsigned int HAdjusted;
  116. unsigned int VDisplay;
  117. unsigned int VSyncStart;
  118. unsigned int VSyncEnd;
  119. unsigned int VTotal;
  120. unsigned int sync;
  121. int dblscan;
  122. int interlaced;
  123. };
  124. struct savage_reg {
  125. unsigned char MiscOutReg; /* Misc */
  126. unsigned char CRTC[25]; /* Crtc Controller */
  127. unsigned char Sequencer[5]; /* Video Sequencer */
  128. unsigned char Graphics[9]; /* Video Graphics */
  129. unsigned char Attribute[21]; /* Video Attribute */
  130. unsigned int mode, refresh;
  131. unsigned char SR08, SR0E, SR0F;
  132. unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR29, SR30;
  133. unsigned char SR54[8];
  134. unsigned char Clock;
  135. unsigned char CR31, CR32, CR33, CR34, CR36, CR3A, CR3B, CR3C;
  136. unsigned char CR40, CR41, CR42, CR43, CR45;
  137. unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E;
  138. unsigned char CR60, CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F;
  139. unsigned char CR86, CR88;
  140. unsigned char CR90, CR91, CRB0;
  141. unsigned int STREAMS[22]; /* yuck, streams regs */
  142. unsigned int MMPR0, MMPR1, MMPR2, MMPR3;
  143. };
  144. /* --------------------------------------------------------------------- */
  145. #define NR_PALETTE 256
  146. struct savagefb_par;
  147. struct savagefb_i2c_chan {
  148. struct savagefb_par *par;
  149. struct i2c_adapter adapter;
  150. struct i2c_algo_bit_data algo;
  151. volatile u8 __iomem *ioaddr;
  152. u32 reg;
  153. };
  154. struct savagefb_par {
  155. struct pci_dev *pcidev;
  156. savage_chipset chip;
  157. struct savagefb_i2c_chan chan;
  158. struct savage_reg state;
  159. struct savage_reg save;
  160. struct savage_reg initial;
  161. struct vgastate vgastate;
  162. struct mutex open_lock;
  163. unsigned char *edid;
  164. u32 pseudo_palette[16];
  165. u32 open_count;
  166. int paletteEnabled;
  167. int pm_state;
  168. int display_type;
  169. int dvi;
  170. int crtonly;
  171. int dacSpeedBpp;
  172. int maxClock;
  173. int minClock;
  174. int numClocks;
  175. int clock[4];
  176. int MCLK, REFCLK, LCDclk;
  177. struct {
  178. void __iomem *vbase;
  179. u32 pbase;
  180. u32 len;
  181. #ifdef CONFIG_MTRR
  182. int mtrr;
  183. #endif
  184. } video;
  185. struct {
  186. void __iomem *vbase;
  187. u32 pbase;
  188. u32 len;
  189. } mmio;
  190. volatile u32 __iomem *bci_base;
  191. unsigned int bci_ptr;
  192. u32 cob_offset;
  193. u32 cob_size;
  194. int cob_index;
  195. void (*SavageWaitIdle) (struct savagefb_par *par);
  196. void (*SavageWaitFifo) (struct savagefb_par *par, int space);
  197. int HorizScaleFactor;
  198. /* Panels size */
  199. int SavagePanelWidth;
  200. int SavagePanelHeight;
  201. struct {
  202. u16 red, green, blue, transp;
  203. } palette[NR_PALETTE];
  204. int depth;
  205. int vwidth;
  206. };
  207. #define BCI_BD_BW_DISABLE 0x10000000
  208. #define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16))
  209. #define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF))
  210. /* IO functions */
  211. static inline u8 savage_in8(u32 addr, struct savagefb_par *par)
  212. {
  213. return readb(par->mmio.vbase + addr);
  214. }
  215. static inline u16 savage_in16(u32 addr, struct savagefb_par *par)
  216. {
  217. return readw(par->mmio.vbase + addr);
  218. }
  219. static inline u32 savage_in32(u32 addr, struct savagefb_par *par)
  220. {
  221. return readl(par->mmio.vbase + addr);
  222. }
  223. static inline void savage_out8(u32 addr, u8 val, struct savagefb_par *par)
  224. {
  225. writeb(val, par->mmio.vbase + addr);
  226. }
  227. static inline void savage_out16(u32 addr, u16 val, struct savagefb_par *par)
  228. {
  229. writew(val, par->mmio.vbase + addr);
  230. }
  231. static inline void savage_out32(u32 addr, u32 val, struct savagefb_par *par)
  232. {
  233. writel(val, par->mmio.vbase + addr);
  234. }
  235. static inline u8 vga_in8(int addr, struct savagefb_par *par)
  236. {
  237. return savage_in8(0x8000 + addr, par);
  238. }
  239. static inline u16 vga_in16(int addr, struct savagefb_par *par)
  240. {
  241. return savage_in16(0x8000 + addr, par);
  242. }
  243. static inline u8 vga_in32(int addr, struct savagefb_par *par)
  244. {
  245. return savage_in32(0x8000 + addr, par);
  246. }
  247. static inline void vga_out8(int addr, u8 val, struct savagefb_par *par)
  248. {
  249. savage_out8(0x8000 + addr, val, par);
  250. }
  251. static inline void vga_out16(int addr, u16 val, struct savagefb_par *par)
  252. {
  253. savage_out16(0x8000 + addr, val, par);
  254. }
  255. static inline void vga_out32(int addr, u32 val, struct savagefb_par *par)
  256. {
  257. savage_out32(0x8000 + addr, val, par);
  258. }
  259. static inline u8 VGArCR (u8 index, struct savagefb_par *par)
  260. {
  261. vga_out8(0x3d4, index, par);
  262. return vga_in8(0x3d5, par);
  263. }
  264. static inline u8 VGArGR (u8 index, struct savagefb_par *par)
  265. {
  266. vga_out8(0x3ce, index, par);
  267. return vga_in8(0x3cf, par);
  268. }
  269. static inline u8 VGArSEQ (u8 index, struct savagefb_par *par)
  270. {
  271. vga_out8(0x3c4, index, par);
  272. return vga_in8(0x3c5, par);
  273. }
  274. static inline void VGAwCR(u8 index, u8 val, struct savagefb_par *par)
  275. {
  276. vga_out8(0x3d4, index, par);
  277. vga_out8(0x3d5, val, par);
  278. }
  279. static inline void VGAwGR(u8 index, u8 val, struct savagefb_par *par)
  280. {
  281. vga_out8(0x3ce, index, par);
  282. vga_out8(0x3cf, val, par);
  283. }
  284. static inline void VGAwSEQ(u8 index, u8 val, struct savagefb_par *par)
  285. {
  286. vga_out8(0x3c4, index, par);
  287. vga_out8 (0x3c5, val, par);
  288. }
  289. static inline void VGAenablePalette(struct savagefb_par *par)
  290. {
  291. u8 tmp;
  292. tmp = vga_in8(0x3da, par);
  293. vga_out8(0x3c0, 0x00, par);
  294. par->paletteEnabled = 1;
  295. }
  296. static inline void VGAdisablePalette(struct savagefb_par *par)
  297. {
  298. u8 tmp;
  299. tmp = vga_in8(0x3da, par);
  300. vga_out8(0x3c0, 0x20, par);
  301. par->paletteEnabled = 0;
  302. }
  303. static inline void VGAwATTR(u8 index, u8 value, struct savagefb_par *par)
  304. {
  305. u8 tmp;
  306. if (par->paletteEnabled)
  307. index &= ~0x20;
  308. else
  309. index |= 0x20;
  310. tmp = vga_in8(0x3da, par);
  311. vga_out8(0x3c0, index, par);
  312. vga_out8 (0x3c0, value, par);
  313. }
  314. static inline void VGAwMISC(u8 value, struct savagefb_par *par)
  315. {
  316. vga_out8(0x3c2, value, par);
  317. }
  318. #ifndef CONFIG_FB_SAVAGE_ACCEL
  319. #define savagefb_set_clip(x)
  320. #endif
  321. static inline void VerticalRetraceWait(struct savagefb_par *par)
  322. {
  323. vga_out8(0x3d4, 0x17, par);
  324. if (vga_in8(0x3d5, par) & 0x80) {
  325. while ((vga_in8(0x3da, par) & 0x08) == 0x08);
  326. while ((vga_in8(0x3da, par) & 0x08) == 0x00);
  327. }
  328. }
  329. extern int savagefb_probe_i2c_connector(struct fb_info *info,
  330. u8 **out_edid);
  331. extern void savagefb_create_i2c_busses(struct fb_info *info);
  332. extern void savagefb_delete_i2c_busses(struct fb_info *info);
  333. extern int savagefb_sync(struct fb_info *info);
  334. extern void savagefb_copyarea(struct fb_info *info,
  335. const struct fb_copyarea *region);
  336. extern void savagefb_fillrect(struct fb_info *info,
  337. const struct fb_fillrect *rect);
  338. extern void savagefb_imageblit(struct fb_info *info,
  339. const struct fb_image *image);
  340. #endif /* __SAVAGEFB_H__ */