uhci-q.c 46 KB

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  1. /*
  2. * Universal Host Controller Interface driver for USB.
  3. *
  4. * Maintainer: Alan Stern <stern@rowland.harvard.edu>
  5. *
  6. * (C) Copyright 1999 Linus Torvalds
  7. * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
  8. * (C) Copyright 1999 Randy Dunlap
  9. * (C) Copyright 1999 Georg Acher, acher@in.tum.de
  10. * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
  11. * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
  12. * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
  13. * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
  14. * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
  15. * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
  16. * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu
  17. */
  18. /*
  19. * Technically, updating td->status here is a race, but it's not really a
  20. * problem. The worst that can happen is that we set the IOC bit again
  21. * generating a spurious interrupt. We could fix this by creating another
  22. * QH and leaving the IOC bit always set, but then we would have to play
  23. * games with the FSBR code to make sure we get the correct order in all
  24. * the cases. I don't think it's worth the effort
  25. */
  26. static void uhci_set_next_interrupt(struct uhci_hcd *uhci)
  27. {
  28. if (uhci->is_stopped)
  29. mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies);
  30. uhci->term_td->status |= cpu_to_hc32(uhci, TD_CTRL_IOC);
  31. }
  32. static inline void uhci_clear_next_interrupt(struct uhci_hcd *uhci)
  33. {
  34. uhci->term_td->status &= ~cpu_to_hc32(uhci, TD_CTRL_IOC);
  35. }
  36. /*
  37. * Full-Speed Bandwidth Reclamation (FSBR).
  38. * We turn on FSBR whenever a queue that wants it is advancing,
  39. * and leave it on for a short time thereafter.
  40. */
  41. static void uhci_fsbr_on(struct uhci_hcd *uhci)
  42. {
  43. struct uhci_qh *lqh;
  44. /* The terminating skeleton QH always points back to the first
  45. * FSBR QH. Make the last async QH point to the terminating
  46. * skeleton QH. */
  47. uhci->fsbr_is_on = 1;
  48. lqh = list_entry(uhci->skel_async_qh->node.prev,
  49. struct uhci_qh, node);
  50. lqh->link = LINK_TO_QH(uhci, uhci->skel_term_qh);
  51. }
  52. static void uhci_fsbr_off(struct uhci_hcd *uhci)
  53. {
  54. struct uhci_qh *lqh;
  55. /* Remove the link from the last async QH to the terminating
  56. * skeleton QH. */
  57. uhci->fsbr_is_on = 0;
  58. lqh = list_entry(uhci->skel_async_qh->node.prev,
  59. struct uhci_qh, node);
  60. lqh->link = UHCI_PTR_TERM(uhci);
  61. }
  62. static void uhci_add_fsbr(struct uhci_hcd *uhci, struct urb *urb)
  63. {
  64. struct urb_priv *urbp = urb->hcpriv;
  65. if (!(urb->transfer_flags & URB_NO_FSBR))
  66. urbp->fsbr = 1;
  67. }
  68. static void uhci_urbp_wants_fsbr(struct uhci_hcd *uhci, struct urb_priv *urbp)
  69. {
  70. if (urbp->fsbr) {
  71. uhci->fsbr_is_wanted = 1;
  72. if (!uhci->fsbr_is_on)
  73. uhci_fsbr_on(uhci);
  74. else if (uhci->fsbr_expiring) {
  75. uhci->fsbr_expiring = 0;
  76. del_timer(&uhci->fsbr_timer);
  77. }
  78. }
  79. }
  80. static void uhci_fsbr_timeout(unsigned long _uhci)
  81. {
  82. struct uhci_hcd *uhci = (struct uhci_hcd *) _uhci;
  83. unsigned long flags;
  84. spin_lock_irqsave(&uhci->lock, flags);
  85. if (uhci->fsbr_expiring) {
  86. uhci->fsbr_expiring = 0;
  87. uhci_fsbr_off(uhci);
  88. }
  89. spin_unlock_irqrestore(&uhci->lock, flags);
  90. }
  91. static struct uhci_td *uhci_alloc_td(struct uhci_hcd *uhci)
  92. {
  93. dma_addr_t dma_handle;
  94. struct uhci_td *td;
  95. td = dma_pool_alloc(uhci->td_pool, GFP_ATOMIC, &dma_handle);
  96. if (!td)
  97. return NULL;
  98. td->dma_handle = dma_handle;
  99. td->frame = -1;
  100. INIT_LIST_HEAD(&td->list);
  101. INIT_LIST_HEAD(&td->fl_list);
  102. return td;
  103. }
  104. static void uhci_free_td(struct uhci_hcd *uhci, struct uhci_td *td)
  105. {
  106. if (!list_empty(&td->list))
  107. dev_WARN(uhci_dev(uhci), "td %p still in list!\n", td);
  108. if (!list_empty(&td->fl_list))
  109. dev_WARN(uhci_dev(uhci), "td %p still in fl_list!\n", td);
  110. dma_pool_free(uhci->td_pool, td, td->dma_handle);
  111. }
  112. static inline void uhci_fill_td(struct uhci_hcd *uhci, struct uhci_td *td,
  113. u32 status, u32 token, u32 buffer)
  114. {
  115. td->status = cpu_to_hc32(uhci, status);
  116. td->token = cpu_to_hc32(uhci, token);
  117. td->buffer = cpu_to_hc32(uhci, buffer);
  118. }
  119. static void uhci_add_td_to_urbp(struct uhci_td *td, struct urb_priv *urbp)
  120. {
  121. list_add_tail(&td->list, &urbp->td_list);
  122. }
  123. static void uhci_remove_td_from_urbp(struct uhci_td *td)
  124. {
  125. list_del_init(&td->list);
  126. }
  127. /*
  128. * We insert Isochronous URBs directly into the frame list at the beginning
  129. */
  130. static inline void uhci_insert_td_in_frame_list(struct uhci_hcd *uhci,
  131. struct uhci_td *td, unsigned framenum)
  132. {
  133. framenum &= (UHCI_NUMFRAMES - 1);
  134. td->frame = framenum;
  135. /* Is there a TD already mapped there? */
  136. if (uhci->frame_cpu[framenum]) {
  137. struct uhci_td *ftd, *ltd;
  138. ftd = uhci->frame_cpu[framenum];
  139. ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list);
  140. list_add_tail(&td->fl_list, &ftd->fl_list);
  141. td->link = ltd->link;
  142. wmb();
  143. ltd->link = LINK_TO_TD(uhci, td);
  144. } else {
  145. td->link = uhci->frame[framenum];
  146. wmb();
  147. uhci->frame[framenum] = LINK_TO_TD(uhci, td);
  148. uhci->frame_cpu[framenum] = td;
  149. }
  150. }
  151. static inline void uhci_remove_td_from_frame_list(struct uhci_hcd *uhci,
  152. struct uhci_td *td)
  153. {
  154. /* If it's not inserted, don't remove it */
  155. if (td->frame == -1) {
  156. WARN_ON(!list_empty(&td->fl_list));
  157. return;
  158. }
  159. if (uhci->frame_cpu[td->frame] == td) {
  160. if (list_empty(&td->fl_list)) {
  161. uhci->frame[td->frame] = td->link;
  162. uhci->frame_cpu[td->frame] = NULL;
  163. } else {
  164. struct uhci_td *ntd;
  165. ntd = list_entry(td->fl_list.next,
  166. struct uhci_td,
  167. fl_list);
  168. uhci->frame[td->frame] = LINK_TO_TD(uhci, ntd);
  169. uhci->frame_cpu[td->frame] = ntd;
  170. }
  171. } else {
  172. struct uhci_td *ptd;
  173. ptd = list_entry(td->fl_list.prev, struct uhci_td, fl_list);
  174. ptd->link = td->link;
  175. }
  176. list_del_init(&td->fl_list);
  177. td->frame = -1;
  178. }
  179. static inline void uhci_remove_tds_from_frame(struct uhci_hcd *uhci,
  180. unsigned int framenum)
  181. {
  182. struct uhci_td *ftd, *ltd;
  183. framenum &= (UHCI_NUMFRAMES - 1);
  184. ftd = uhci->frame_cpu[framenum];
  185. if (ftd) {
  186. ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list);
  187. uhci->frame[framenum] = ltd->link;
  188. uhci->frame_cpu[framenum] = NULL;
  189. while (!list_empty(&ftd->fl_list))
  190. list_del_init(ftd->fl_list.prev);
  191. }
  192. }
  193. /*
  194. * Remove all the TDs for an Isochronous URB from the frame list
  195. */
  196. static void uhci_unlink_isochronous_tds(struct uhci_hcd *uhci, struct urb *urb)
  197. {
  198. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  199. struct uhci_td *td;
  200. list_for_each_entry(td, &urbp->td_list, list)
  201. uhci_remove_td_from_frame_list(uhci, td);
  202. }
  203. static struct uhci_qh *uhci_alloc_qh(struct uhci_hcd *uhci,
  204. struct usb_device *udev, struct usb_host_endpoint *hep)
  205. {
  206. dma_addr_t dma_handle;
  207. struct uhci_qh *qh;
  208. qh = dma_pool_alloc(uhci->qh_pool, GFP_ATOMIC, &dma_handle);
  209. if (!qh)
  210. return NULL;
  211. memset(qh, 0, sizeof(*qh));
  212. qh->dma_handle = dma_handle;
  213. qh->element = UHCI_PTR_TERM(uhci);
  214. qh->link = UHCI_PTR_TERM(uhci);
  215. INIT_LIST_HEAD(&qh->queue);
  216. INIT_LIST_HEAD(&qh->node);
  217. if (udev) { /* Normal QH */
  218. qh->type = usb_endpoint_type(&hep->desc);
  219. if (qh->type != USB_ENDPOINT_XFER_ISOC) {
  220. qh->dummy_td = uhci_alloc_td(uhci);
  221. if (!qh->dummy_td) {
  222. dma_pool_free(uhci->qh_pool, qh, dma_handle);
  223. return NULL;
  224. }
  225. }
  226. qh->state = QH_STATE_IDLE;
  227. qh->hep = hep;
  228. qh->udev = udev;
  229. hep->hcpriv = qh;
  230. if (qh->type == USB_ENDPOINT_XFER_INT ||
  231. qh->type == USB_ENDPOINT_XFER_ISOC)
  232. qh->load = usb_calc_bus_time(udev->speed,
  233. usb_endpoint_dir_in(&hep->desc),
  234. qh->type == USB_ENDPOINT_XFER_ISOC,
  235. le16_to_cpu(hep->desc.wMaxPacketSize))
  236. / 1000 + 1;
  237. } else { /* Skeleton QH */
  238. qh->state = QH_STATE_ACTIVE;
  239. qh->type = -1;
  240. }
  241. return qh;
  242. }
  243. static void uhci_free_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  244. {
  245. WARN_ON(qh->state != QH_STATE_IDLE && qh->udev);
  246. if (!list_empty(&qh->queue))
  247. dev_WARN(uhci_dev(uhci), "qh %p list not empty!\n", qh);
  248. list_del(&qh->node);
  249. if (qh->udev) {
  250. qh->hep->hcpriv = NULL;
  251. if (qh->dummy_td)
  252. uhci_free_td(uhci, qh->dummy_td);
  253. }
  254. dma_pool_free(uhci->qh_pool, qh, qh->dma_handle);
  255. }
  256. /*
  257. * When a queue is stopped and a dequeued URB is given back, adjust
  258. * the previous TD link (if the URB isn't first on the queue) or
  259. * save its toggle value (if it is first and is currently executing).
  260. *
  261. * Returns 0 if the URB should not yet be given back, 1 otherwise.
  262. */
  263. static int uhci_cleanup_queue(struct uhci_hcd *uhci, struct uhci_qh *qh,
  264. struct urb *urb)
  265. {
  266. struct urb_priv *urbp = urb->hcpriv;
  267. struct uhci_td *td;
  268. int ret = 1;
  269. /* Isochronous pipes don't use toggles and their TD link pointers
  270. * get adjusted during uhci_urb_dequeue(). But since their queues
  271. * cannot truly be stopped, we have to watch out for dequeues
  272. * occurring after the nominal unlink frame. */
  273. if (qh->type == USB_ENDPOINT_XFER_ISOC) {
  274. ret = (uhci->frame_number + uhci->is_stopped !=
  275. qh->unlink_frame);
  276. goto done;
  277. }
  278. /* If the URB isn't first on its queue, adjust the link pointer
  279. * of the last TD in the previous URB. The toggle doesn't need
  280. * to be saved since this URB can't be executing yet. */
  281. if (qh->queue.next != &urbp->node) {
  282. struct urb_priv *purbp;
  283. struct uhci_td *ptd;
  284. purbp = list_entry(urbp->node.prev, struct urb_priv, node);
  285. WARN_ON(list_empty(&purbp->td_list));
  286. ptd = list_entry(purbp->td_list.prev, struct uhci_td,
  287. list);
  288. td = list_entry(urbp->td_list.prev, struct uhci_td,
  289. list);
  290. ptd->link = td->link;
  291. goto done;
  292. }
  293. /* If the QH element pointer is UHCI_PTR_TERM then then currently
  294. * executing URB has already been unlinked, so this one isn't it. */
  295. if (qh_element(qh) == UHCI_PTR_TERM(uhci))
  296. goto done;
  297. qh->element = UHCI_PTR_TERM(uhci);
  298. /* Control pipes don't have to worry about toggles */
  299. if (qh->type == USB_ENDPOINT_XFER_CONTROL)
  300. goto done;
  301. /* Save the next toggle value */
  302. WARN_ON(list_empty(&urbp->td_list));
  303. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  304. qh->needs_fixup = 1;
  305. qh->initial_toggle = uhci_toggle(td_token(uhci, td));
  306. done:
  307. return ret;
  308. }
  309. /*
  310. * Fix up the data toggles for URBs in a queue, when one of them
  311. * terminates early (short transfer, error, or dequeued).
  312. */
  313. static void uhci_fixup_toggles(struct uhci_hcd *uhci, struct uhci_qh *qh,
  314. int skip_first)
  315. {
  316. struct urb_priv *urbp = NULL;
  317. struct uhci_td *td;
  318. unsigned int toggle = qh->initial_toggle;
  319. unsigned int pipe;
  320. /* Fixups for a short transfer start with the second URB in the
  321. * queue (the short URB is the first). */
  322. if (skip_first)
  323. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  324. /* When starting with the first URB, if the QH element pointer is
  325. * still valid then we know the URB's toggles are okay. */
  326. else if (qh_element(qh) != UHCI_PTR_TERM(uhci))
  327. toggle = 2;
  328. /* Fix up the toggle for the URBs in the queue. Normally this
  329. * loop won't run more than once: When an error or short transfer
  330. * occurs, the queue usually gets emptied. */
  331. urbp = list_prepare_entry(urbp, &qh->queue, node);
  332. list_for_each_entry_continue(urbp, &qh->queue, node) {
  333. /* If the first TD has the right toggle value, we don't
  334. * need to change any toggles in this URB */
  335. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  336. if (toggle > 1 || uhci_toggle(td_token(uhci, td)) == toggle) {
  337. td = list_entry(urbp->td_list.prev, struct uhci_td,
  338. list);
  339. toggle = uhci_toggle(td_token(uhci, td)) ^ 1;
  340. /* Otherwise all the toggles in the URB have to be switched */
  341. } else {
  342. list_for_each_entry(td, &urbp->td_list, list) {
  343. td->token ^= cpu_to_hc32(uhci,
  344. TD_TOKEN_TOGGLE);
  345. toggle ^= 1;
  346. }
  347. }
  348. }
  349. wmb();
  350. pipe = list_entry(qh->queue.next, struct urb_priv, node)->urb->pipe;
  351. usb_settoggle(qh->udev, usb_pipeendpoint(pipe),
  352. usb_pipeout(pipe), toggle);
  353. qh->needs_fixup = 0;
  354. }
  355. /*
  356. * Link an Isochronous QH into its skeleton's list
  357. */
  358. static inline void link_iso(struct uhci_hcd *uhci, struct uhci_qh *qh)
  359. {
  360. list_add_tail(&qh->node, &uhci->skel_iso_qh->node);
  361. /* Isochronous QHs aren't linked by the hardware */
  362. }
  363. /*
  364. * Link a high-period interrupt QH into the schedule at the end of its
  365. * skeleton's list
  366. */
  367. static void link_interrupt(struct uhci_hcd *uhci, struct uhci_qh *qh)
  368. {
  369. struct uhci_qh *pqh;
  370. list_add_tail(&qh->node, &uhci->skelqh[qh->skel]->node);
  371. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  372. qh->link = pqh->link;
  373. wmb();
  374. pqh->link = LINK_TO_QH(uhci, qh);
  375. }
  376. /*
  377. * Link a period-1 interrupt or async QH into the schedule at the
  378. * correct spot in the async skeleton's list, and update the FSBR link
  379. */
  380. static void link_async(struct uhci_hcd *uhci, struct uhci_qh *qh)
  381. {
  382. struct uhci_qh *pqh;
  383. __hc32 link_to_new_qh;
  384. /* Find the predecessor QH for our new one and insert it in the list.
  385. * The list of QHs is expected to be short, so linear search won't
  386. * take too long. */
  387. list_for_each_entry_reverse(pqh, &uhci->skel_async_qh->node, node) {
  388. if (pqh->skel <= qh->skel)
  389. break;
  390. }
  391. list_add(&qh->node, &pqh->node);
  392. /* Link it into the schedule */
  393. qh->link = pqh->link;
  394. wmb();
  395. link_to_new_qh = LINK_TO_QH(uhci, qh);
  396. pqh->link = link_to_new_qh;
  397. /* If this is now the first FSBR QH, link the terminating skeleton
  398. * QH to it. */
  399. if (pqh->skel < SKEL_FSBR && qh->skel >= SKEL_FSBR)
  400. uhci->skel_term_qh->link = link_to_new_qh;
  401. }
  402. /*
  403. * Put a QH on the schedule in both hardware and software
  404. */
  405. static void uhci_activate_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  406. {
  407. WARN_ON(list_empty(&qh->queue));
  408. /* Set the element pointer if it isn't set already.
  409. * This isn't needed for Isochronous queues, but it doesn't hurt. */
  410. if (qh_element(qh) == UHCI_PTR_TERM(uhci)) {
  411. struct urb_priv *urbp = list_entry(qh->queue.next,
  412. struct urb_priv, node);
  413. struct uhci_td *td = list_entry(urbp->td_list.next,
  414. struct uhci_td, list);
  415. qh->element = LINK_TO_TD(uhci, td);
  416. }
  417. /* Treat the queue as if it has just advanced */
  418. qh->wait_expired = 0;
  419. qh->advance_jiffies = jiffies;
  420. if (qh->state == QH_STATE_ACTIVE)
  421. return;
  422. qh->state = QH_STATE_ACTIVE;
  423. /* Move the QH from its old list to the correct spot in the appropriate
  424. * skeleton's list */
  425. if (qh == uhci->next_qh)
  426. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  427. node);
  428. list_del(&qh->node);
  429. if (qh->skel == SKEL_ISO)
  430. link_iso(uhci, qh);
  431. else if (qh->skel < SKEL_ASYNC)
  432. link_interrupt(uhci, qh);
  433. else
  434. link_async(uhci, qh);
  435. }
  436. /*
  437. * Unlink a high-period interrupt QH from the schedule
  438. */
  439. static void unlink_interrupt(struct uhci_hcd *uhci, struct uhci_qh *qh)
  440. {
  441. struct uhci_qh *pqh;
  442. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  443. pqh->link = qh->link;
  444. mb();
  445. }
  446. /*
  447. * Unlink a period-1 interrupt or async QH from the schedule
  448. */
  449. static void unlink_async(struct uhci_hcd *uhci, struct uhci_qh *qh)
  450. {
  451. struct uhci_qh *pqh;
  452. __hc32 link_to_next_qh = qh->link;
  453. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  454. pqh->link = link_to_next_qh;
  455. /* If this was the old first FSBR QH, link the terminating skeleton
  456. * QH to the next (new first FSBR) QH. */
  457. if (pqh->skel < SKEL_FSBR && qh->skel >= SKEL_FSBR)
  458. uhci->skel_term_qh->link = link_to_next_qh;
  459. mb();
  460. }
  461. /*
  462. * Take a QH off the hardware schedule
  463. */
  464. static void uhci_unlink_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  465. {
  466. if (qh->state == QH_STATE_UNLINKING)
  467. return;
  468. WARN_ON(qh->state != QH_STATE_ACTIVE || !qh->udev);
  469. qh->state = QH_STATE_UNLINKING;
  470. /* Unlink the QH from the schedule and record when we did it */
  471. if (qh->skel == SKEL_ISO)
  472. ;
  473. else if (qh->skel < SKEL_ASYNC)
  474. unlink_interrupt(uhci, qh);
  475. else
  476. unlink_async(uhci, qh);
  477. uhci_get_current_frame_number(uhci);
  478. qh->unlink_frame = uhci->frame_number;
  479. /* Force an interrupt so we know when the QH is fully unlinked */
  480. if (list_empty(&uhci->skel_unlink_qh->node) || uhci->is_stopped)
  481. uhci_set_next_interrupt(uhci);
  482. /* Move the QH from its old list to the end of the unlinking list */
  483. if (qh == uhci->next_qh)
  484. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  485. node);
  486. list_move_tail(&qh->node, &uhci->skel_unlink_qh->node);
  487. }
  488. /*
  489. * When we and the controller are through with a QH, it becomes IDLE.
  490. * This happens when a QH has been off the schedule (on the unlinking
  491. * list) for more than one frame, or when an error occurs while adding
  492. * the first URB onto a new QH.
  493. */
  494. static void uhci_make_qh_idle(struct uhci_hcd *uhci, struct uhci_qh *qh)
  495. {
  496. WARN_ON(qh->state == QH_STATE_ACTIVE);
  497. if (qh == uhci->next_qh)
  498. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  499. node);
  500. list_move(&qh->node, &uhci->idle_qh_list);
  501. qh->state = QH_STATE_IDLE;
  502. /* Now that the QH is idle, its post_td isn't being used */
  503. if (qh->post_td) {
  504. uhci_free_td(uhci, qh->post_td);
  505. qh->post_td = NULL;
  506. }
  507. /* If anyone is waiting for a QH to become idle, wake them up */
  508. if (uhci->num_waiting)
  509. wake_up_all(&uhci->waitqh);
  510. }
  511. /*
  512. * Find the highest existing bandwidth load for a given phase and period.
  513. */
  514. static int uhci_highest_load(struct uhci_hcd *uhci, int phase, int period)
  515. {
  516. int highest_load = uhci->load[phase];
  517. for (phase += period; phase < MAX_PHASE; phase += period)
  518. highest_load = max_t(int, highest_load, uhci->load[phase]);
  519. return highest_load;
  520. }
  521. /*
  522. * Set qh->phase to the optimal phase for a periodic transfer and
  523. * check whether the bandwidth requirement is acceptable.
  524. */
  525. static int uhci_check_bandwidth(struct uhci_hcd *uhci, struct uhci_qh *qh)
  526. {
  527. int minimax_load;
  528. /* Find the optimal phase (unless it is already set) and get
  529. * its load value. */
  530. if (qh->phase >= 0)
  531. minimax_load = uhci_highest_load(uhci, qh->phase, qh->period);
  532. else {
  533. int phase, load;
  534. int max_phase = min_t(int, MAX_PHASE, qh->period);
  535. qh->phase = 0;
  536. minimax_load = uhci_highest_load(uhci, qh->phase, qh->period);
  537. for (phase = 1; phase < max_phase; ++phase) {
  538. load = uhci_highest_load(uhci, phase, qh->period);
  539. if (load < minimax_load) {
  540. minimax_load = load;
  541. qh->phase = phase;
  542. }
  543. }
  544. }
  545. /* Maximum allowable periodic bandwidth is 90%, or 900 us per frame */
  546. if (minimax_load + qh->load > 900) {
  547. dev_dbg(uhci_dev(uhci), "bandwidth allocation failed: "
  548. "period %d, phase %d, %d + %d us\n",
  549. qh->period, qh->phase, minimax_load, qh->load);
  550. return -ENOSPC;
  551. }
  552. return 0;
  553. }
  554. /*
  555. * Reserve a periodic QH's bandwidth in the schedule
  556. */
  557. static void uhci_reserve_bandwidth(struct uhci_hcd *uhci, struct uhci_qh *qh)
  558. {
  559. int i;
  560. int load = qh->load;
  561. char *p = "??";
  562. for (i = qh->phase; i < MAX_PHASE; i += qh->period) {
  563. uhci->load[i] += load;
  564. uhci->total_load += load;
  565. }
  566. uhci_to_hcd(uhci)->self.bandwidth_allocated =
  567. uhci->total_load / MAX_PHASE;
  568. switch (qh->type) {
  569. case USB_ENDPOINT_XFER_INT:
  570. ++uhci_to_hcd(uhci)->self.bandwidth_int_reqs;
  571. p = "INT";
  572. break;
  573. case USB_ENDPOINT_XFER_ISOC:
  574. ++uhci_to_hcd(uhci)->self.bandwidth_isoc_reqs;
  575. p = "ISO";
  576. break;
  577. }
  578. qh->bandwidth_reserved = 1;
  579. dev_dbg(uhci_dev(uhci),
  580. "%s dev %d ep%02x-%s, period %d, phase %d, %d us\n",
  581. "reserve", qh->udev->devnum,
  582. qh->hep->desc.bEndpointAddress, p,
  583. qh->period, qh->phase, load);
  584. }
  585. /*
  586. * Release a periodic QH's bandwidth reservation
  587. */
  588. static void uhci_release_bandwidth(struct uhci_hcd *uhci, struct uhci_qh *qh)
  589. {
  590. int i;
  591. int load = qh->load;
  592. char *p = "??";
  593. for (i = qh->phase; i < MAX_PHASE; i += qh->period) {
  594. uhci->load[i] -= load;
  595. uhci->total_load -= load;
  596. }
  597. uhci_to_hcd(uhci)->self.bandwidth_allocated =
  598. uhci->total_load / MAX_PHASE;
  599. switch (qh->type) {
  600. case USB_ENDPOINT_XFER_INT:
  601. --uhci_to_hcd(uhci)->self.bandwidth_int_reqs;
  602. p = "INT";
  603. break;
  604. case USB_ENDPOINT_XFER_ISOC:
  605. --uhci_to_hcd(uhci)->self.bandwidth_isoc_reqs;
  606. p = "ISO";
  607. break;
  608. }
  609. qh->bandwidth_reserved = 0;
  610. dev_dbg(uhci_dev(uhci),
  611. "%s dev %d ep%02x-%s, period %d, phase %d, %d us\n",
  612. "release", qh->udev->devnum,
  613. qh->hep->desc.bEndpointAddress, p,
  614. qh->period, qh->phase, load);
  615. }
  616. static inline struct urb_priv *uhci_alloc_urb_priv(struct uhci_hcd *uhci,
  617. struct urb *urb)
  618. {
  619. struct urb_priv *urbp;
  620. urbp = kmem_cache_zalloc(uhci_up_cachep, GFP_ATOMIC);
  621. if (!urbp)
  622. return NULL;
  623. urbp->urb = urb;
  624. urb->hcpriv = urbp;
  625. INIT_LIST_HEAD(&urbp->node);
  626. INIT_LIST_HEAD(&urbp->td_list);
  627. return urbp;
  628. }
  629. static void uhci_free_urb_priv(struct uhci_hcd *uhci,
  630. struct urb_priv *urbp)
  631. {
  632. struct uhci_td *td, *tmp;
  633. if (!list_empty(&urbp->node))
  634. dev_WARN(uhci_dev(uhci), "urb %p still on QH's list!\n",
  635. urbp->urb);
  636. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  637. uhci_remove_td_from_urbp(td);
  638. uhci_free_td(uhci, td);
  639. }
  640. kmem_cache_free(uhci_up_cachep, urbp);
  641. }
  642. /*
  643. * Map status to standard result codes
  644. *
  645. * <status> is (td_status(uhci, td) & 0xF60000), a.k.a.
  646. * uhci_status_bits(td_status(uhci, td)).
  647. * Note: <status> does not include the TD_CTRL_NAK bit.
  648. * <dir_out> is True for output TDs and False for input TDs.
  649. */
  650. static int uhci_map_status(int status, int dir_out)
  651. {
  652. if (!status)
  653. return 0;
  654. if (status & TD_CTRL_BITSTUFF) /* Bitstuff error */
  655. return -EPROTO;
  656. if (status & TD_CTRL_CRCTIMEO) { /* CRC/Timeout */
  657. if (dir_out)
  658. return -EPROTO;
  659. else
  660. return -EILSEQ;
  661. }
  662. if (status & TD_CTRL_BABBLE) /* Babble */
  663. return -EOVERFLOW;
  664. if (status & TD_CTRL_DBUFERR) /* Buffer error */
  665. return -ENOSR;
  666. if (status & TD_CTRL_STALLED) /* Stalled */
  667. return -EPIPE;
  668. return 0;
  669. }
  670. /*
  671. * Control transfers
  672. */
  673. static int uhci_submit_control(struct uhci_hcd *uhci, struct urb *urb,
  674. struct uhci_qh *qh)
  675. {
  676. struct uhci_td *td;
  677. unsigned long destination, status;
  678. int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize);
  679. int len = urb->transfer_buffer_length;
  680. dma_addr_t data = urb->transfer_dma;
  681. __hc32 *plink;
  682. struct urb_priv *urbp = urb->hcpriv;
  683. int skel;
  684. /* The "pipe" thing contains the destination in bits 8--18 */
  685. destination = (urb->pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP;
  686. /* 3 errors, dummy TD remains inactive */
  687. status = uhci_maxerr(3);
  688. if (urb->dev->speed == USB_SPEED_LOW)
  689. status |= TD_CTRL_LS;
  690. /*
  691. * Build the TD for the control request setup packet
  692. */
  693. td = qh->dummy_td;
  694. uhci_add_td_to_urbp(td, urbp);
  695. uhci_fill_td(uhci, td, status, destination | uhci_explen(8),
  696. urb->setup_dma);
  697. plink = &td->link;
  698. status |= TD_CTRL_ACTIVE;
  699. /*
  700. * If direction is "send", change the packet ID from SETUP (0x2D)
  701. * to OUT (0xE1). Else change it from SETUP to IN (0x69) and
  702. * set Short Packet Detect (SPD) for all data packets.
  703. *
  704. * 0-length transfers always get treated as "send".
  705. */
  706. if (usb_pipeout(urb->pipe) || len == 0)
  707. destination ^= (USB_PID_SETUP ^ USB_PID_OUT);
  708. else {
  709. destination ^= (USB_PID_SETUP ^ USB_PID_IN);
  710. status |= TD_CTRL_SPD;
  711. }
  712. /*
  713. * Build the DATA TDs
  714. */
  715. while (len > 0) {
  716. int pktsze = maxsze;
  717. if (len <= pktsze) { /* The last data packet */
  718. pktsze = len;
  719. status &= ~TD_CTRL_SPD;
  720. }
  721. td = uhci_alloc_td(uhci);
  722. if (!td)
  723. goto nomem;
  724. *plink = LINK_TO_TD(uhci, td);
  725. /* Alternate Data0/1 (start with Data1) */
  726. destination ^= TD_TOKEN_TOGGLE;
  727. uhci_add_td_to_urbp(td, urbp);
  728. uhci_fill_td(uhci, td, status,
  729. destination | uhci_explen(pktsze), data);
  730. plink = &td->link;
  731. data += pktsze;
  732. len -= pktsze;
  733. }
  734. /*
  735. * Build the final TD for control status
  736. */
  737. td = uhci_alloc_td(uhci);
  738. if (!td)
  739. goto nomem;
  740. *plink = LINK_TO_TD(uhci, td);
  741. /* Change direction for the status transaction */
  742. destination ^= (USB_PID_IN ^ USB_PID_OUT);
  743. destination |= TD_TOKEN_TOGGLE; /* End in Data1 */
  744. uhci_add_td_to_urbp(td, urbp);
  745. uhci_fill_td(uhci, td, status | TD_CTRL_IOC,
  746. destination | uhci_explen(0), 0);
  747. plink = &td->link;
  748. /*
  749. * Build the new dummy TD and activate the old one
  750. */
  751. td = uhci_alloc_td(uhci);
  752. if (!td)
  753. goto nomem;
  754. *plink = LINK_TO_TD(uhci, td);
  755. uhci_fill_td(uhci, td, 0, USB_PID_OUT | uhci_explen(0), 0);
  756. wmb();
  757. qh->dummy_td->status |= cpu_to_hc32(uhci, TD_CTRL_ACTIVE);
  758. qh->dummy_td = td;
  759. /* Low-speed transfers get a different queue, and won't hog the bus.
  760. * Also, some devices enumerate better without FSBR; the easiest way
  761. * to do that is to put URBs on the low-speed queue while the device
  762. * isn't in the CONFIGURED state. */
  763. if (urb->dev->speed == USB_SPEED_LOW ||
  764. urb->dev->state != USB_STATE_CONFIGURED)
  765. skel = SKEL_LS_CONTROL;
  766. else {
  767. skel = SKEL_FS_CONTROL;
  768. uhci_add_fsbr(uhci, urb);
  769. }
  770. if (qh->state != QH_STATE_ACTIVE)
  771. qh->skel = skel;
  772. return 0;
  773. nomem:
  774. /* Remove the dummy TD from the td_list so it doesn't get freed */
  775. uhci_remove_td_from_urbp(qh->dummy_td);
  776. return -ENOMEM;
  777. }
  778. /*
  779. * Common submit for bulk and interrupt
  780. */
  781. static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb,
  782. struct uhci_qh *qh)
  783. {
  784. struct uhci_td *td;
  785. unsigned long destination, status;
  786. int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize);
  787. int len = urb->transfer_buffer_length;
  788. int this_sg_len;
  789. dma_addr_t data;
  790. __hc32 *plink;
  791. struct urb_priv *urbp = urb->hcpriv;
  792. unsigned int toggle;
  793. struct scatterlist *sg;
  794. int i;
  795. if (len < 0)
  796. return -EINVAL;
  797. /* The "pipe" thing contains the destination in bits 8--18 */
  798. destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
  799. toggle = usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  800. usb_pipeout(urb->pipe));
  801. /* 3 errors, dummy TD remains inactive */
  802. status = uhci_maxerr(3);
  803. if (urb->dev->speed == USB_SPEED_LOW)
  804. status |= TD_CTRL_LS;
  805. if (usb_pipein(urb->pipe))
  806. status |= TD_CTRL_SPD;
  807. i = urb->num_mapped_sgs;
  808. if (len > 0 && i > 0) {
  809. sg = urb->sg;
  810. data = sg_dma_address(sg);
  811. /* urb->transfer_buffer_length may be smaller than the
  812. * size of the scatterlist (or vice versa)
  813. */
  814. this_sg_len = min_t(int, sg_dma_len(sg), len);
  815. } else {
  816. sg = NULL;
  817. data = urb->transfer_dma;
  818. this_sg_len = len;
  819. }
  820. /*
  821. * Build the DATA TDs
  822. */
  823. plink = NULL;
  824. td = qh->dummy_td;
  825. for (;;) { /* Allow zero length packets */
  826. int pktsze = maxsze;
  827. if (len <= pktsze) { /* The last packet */
  828. pktsze = len;
  829. if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
  830. status &= ~TD_CTRL_SPD;
  831. }
  832. if (plink) {
  833. td = uhci_alloc_td(uhci);
  834. if (!td)
  835. goto nomem;
  836. *plink = LINK_TO_TD(uhci, td);
  837. }
  838. uhci_add_td_to_urbp(td, urbp);
  839. uhci_fill_td(uhci, td, status,
  840. destination | uhci_explen(pktsze) |
  841. (toggle << TD_TOKEN_TOGGLE_SHIFT),
  842. data);
  843. plink = &td->link;
  844. status |= TD_CTRL_ACTIVE;
  845. toggle ^= 1;
  846. data += pktsze;
  847. this_sg_len -= pktsze;
  848. len -= maxsze;
  849. if (this_sg_len <= 0) {
  850. if (--i <= 0 || len <= 0)
  851. break;
  852. sg = sg_next(sg);
  853. data = sg_dma_address(sg);
  854. this_sg_len = min_t(int, sg_dma_len(sg), len);
  855. }
  856. }
  857. /*
  858. * URB_ZERO_PACKET means adding a 0-length packet, if direction
  859. * is OUT and the transfer_length was an exact multiple of maxsze,
  860. * hence (len = transfer_length - N * maxsze) == 0
  861. * however, if transfer_length == 0, the zero packet was already
  862. * prepared above.
  863. */
  864. if ((urb->transfer_flags & URB_ZERO_PACKET) &&
  865. usb_pipeout(urb->pipe) && len == 0 &&
  866. urb->transfer_buffer_length > 0) {
  867. td = uhci_alloc_td(uhci);
  868. if (!td)
  869. goto nomem;
  870. *plink = LINK_TO_TD(uhci, td);
  871. uhci_add_td_to_urbp(td, urbp);
  872. uhci_fill_td(uhci, td, status,
  873. destination | uhci_explen(0) |
  874. (toggle << TD_TOKEN_TOGGLE_SHIFT),
  875. data);
  876. plink = &td->link;
  877. toggle ^= 1;
  878. }
  879. /* Set the interrupt-on-completion flag on the last packet.
  880. * A more-or-less typical 4 KB URB (= size of one memory page)
  881. * will require about 3 ms to transfer; that's a little on the
  882. * fast side but not enough to justify delaying an interrupt
  883. * more than 2 or 3 URBs, so we will ignore the URB_NO_INTERRUPT
  884. * flag setting. */
  885. td->status |= cpu_to_hc32(uhci, TD_CTRL_IOC);
  886. /*
  887. * Build the new dummy TD and activate the old one
  888. */
  889. td = uhci_alloc_td(uhci);
  890. if (!td)
  891. goto nomem;
  892. *plink = LINK_TO_TD(uhci, td);
  893. uhci_fill_td(uhci, td, 0, USB_PID_OUT | uhci_explen(0), 0);
  894. wmb();
  895. qh->dummy_td->status |= cpu_to_hc32(uhci, TD_CTRL_ACTIVE);
  896. qh->dummy_td = td;
  897. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  898. usb_pipeout(urb->pipe), toggle);
  899. return 0;
  900. nomem:
  901. /* Remove the dummy TD from the td_list so it doesn't get freed */
  902. uhci_remove_td_from_urbp(qh->dummy_td);
  903. return -ENOMEM;
  904. }
  905. static int uhci_submit_bulk(struct uhci_hcd *uhci, struct urb *urb,
  906. struct uhci_qh *qh)
  907. {
  908. int ret;
  909. /* Can't have low-speed bulk transfers */
  910. if (urb->dev->speed == USB_SPEED_LOW)
  911. return -EINVAL;
  912. if (qh->state != QH_STATE_ACTIVE)
  913. qh->skel = SKEL_BULK;
  914. ret = uhci_submit_common(uhci, urb, qh);
  915. if (ret == 0)
  916. uhci_add_fsbr(uhci, urb);
  917. return ret;
  918. }
  919. static int uhci_submit_interrupt(struct uhci_hcd *uhci, struct urb *urb,
  920. struct uhci_qh *qh)
  921. {
  922. int ret;
  923. /* USB 1.1 interrupt transfers only involve one packet per interval.
  924. * Drivers can submit URBs of any length, but longer ones will need
  925. * multiple intervals to complete.
  926. */
  927. if (!qh->bandwidth_reserved) {
  928. int exponent;
  929. /* Figure out which power-of-two queue to use */
  930. for (exponent = 7; exponent >= 0; --exponent) {
  931. if ((1 << exponent) <= urb->interval)
  932. break;
  933. }
  934. if (exponent < 0)
  935. return -EINVAL;
  936. /* If the slot is full, try a lower period */
  937. do {
  938. qh->period = 1 << exponent;
  939. qh->skel = SKEL_INDEX(exponent);
  940. /* For now, interrupt phase is fixed by the layout
  941. * of the QH lists.
  942. */
  943. qh->phase = (qh->period / 2) & (MAX_PHASE - 1);
  944. ret = uhci_check_bandwidth(uhci, qh);
  945. } while (ret != 0 && --exponent >= 0);
  946. if (ret)
  947. return ret;
  948. } else if (qh->period > urb->interval)
  949. return -EINVAL; /* Can't decrease the period */
  950. ret = uhci_submit_common(uhci, urb, qh);
  951. if (ret == 0) {
  952. urb->interval = qh->period;
  953. if (!qh->bandwidth_reserved)
  954. uhci_reserve_bandwidth(uhci, qh);
  955. }
  956. return ret;
  957. }
  958. /*
  959. * Fix up the data structures following a short transfer
  960. */
  961. static int uhci_fixup_short_transfer(struct uhci_hcd *uhci,
  962. struct uhci_qh *qh, struct urb_priv *urbp)
  963. {
  964. struct uhci_td *td;
  965. struct list_head *tmp;
  966. int ret;
  967. td = list_entry(urbp->td_list.prev, struct uhci_td, list);
  968. if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
  969. /* When a control transfer is short, we have to restart
  970. * the queue at the status stage transaction, which is
  971. * the last TD. */
  972. WARN_ON(list_empty(&urbp->td_list));
  973. qh->element = LINK_TO_TD(uhci, td);
  974. tmp = td->list.prev;
  975. ret = -EINPROGRESS;
  976. } else {
  977. /* When a bulk/interrupt transfer is short, we have to
  978. * fix up the toggles of the following URBs on the queue
  979. * before restarting the queue at the next URB. */
  980. qh->initial_toggle =
  981. uhci_toggle(td_token(uhci, qh->post_td)) ^ 1;
  982. uhci_fixup_toggles(uhci, qh, 1);
  983. if (list_empty(&urbp->td_list))
  984. td = qh->post_td;
  985. qh->element = td->link;
  986. tmp = urbp->td_list.prev;
  987. ret = 0;
  988. }
  989. /* Remove all the TDs we skipped over, from tmp back to the start */
  990. while (tmp != &urbp->td_list) {
  991. td = list_entry(tmp, struct uhci_td, list);
  992. tmp = tmp->prev;
  993. uhci_remove_td_from_urbp(td);
  994. uhci_free_td(uhci, td);
  995. }
  996. return ret;
  997. }
  998. /*
  999. * Common result for control, bulk, and interrupt
  1000. */
  1001. static int uhci_result_common(struct uhci_hcd *uhci, struct urb *urb)
  1002. {
  1003. struct urb_priv *urbp = urb->hcpriv;
  1004. struct uhci_qh *qh = urbp->qh;
  1005. struct uhci_td *td, *tmp;
  1006. unsigned status;
  1007. int ret = 0;
  1008. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  1009. unsigned int ctrlstat;
  1010. int len;
  1011. ctrlstat = td_status(uhci, td);
  1012. status = uhci_status_bits(ctrlstat);
  1013. if (status & TD_CTRL_ACTIVE)
  1014. return -EINPROGRESS;
  1015. len = uhci_actual_length(ctrlstat);
  1016. urb->actual_length += len;
  1017. if (status) {
  1018. ret = uhci_map_status(status,
  1019. uhci_packetout(td_token(uhci, td)));
  1020. if ((debug == 1 && ret != -EPIPE) || debug > 1) {
  1021. /* Some debugging code */
  1022. dev_dbg(&urb->dev->dev,
  1023. "%s: failed with status %x\n",
  1024. __func__, status);
  1025. if (debug > 1 && errbuf) {
  1026. /* Print the chain for debugging */
  1027. uhci_show_qh(uhci, urbp->qh, errbuf,
  1028. ERRBUF_LEN, 0);
  1029. lprintk(errbuf);
  1030. }
  1031. }
  1032. /* Did we receive a short packet? */
  1033. } else if (len < uhci_expected_length(td_token(uhci, td))) {
  1034. /* For control transfers, go to the status TD if
  1035. * this isn't already the last data TD */
  1036. if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
  1037. if (td->list.next != urbp->td_list.prev)
  1038. ret = 1;
  1039. }
  1040. /* For bulk and interrupt, this may be an error */
  1041. else if (urb->transfer_flags & URB_SHORT_NOT_OK)
  1042. ret = -EREMOTEIO;
  1043. /* Fixup needed only if this isn't the URB's last TD */
  1044. else if (&td->list != urbp->td_list.prev)
  1045. ret = 1;
  1046. }
  1047. uhci_remove_td_from_urbp(td);
  1048. if (qh->post_td)
  1049. uhci_free_td(uhci, qh->post_td);
  1050. qh->post_td = td;
  1051. if (ret != 0)
  1052. goto err;
  1053. }
  1054. return ret;
  1055. err:
  1056. if (ret < 0) {
  1057. /* Note that the queue has stopped and save
  1058. * the next toggle value */
  1059. qh->element = UHCI_PTR_TERM(uhci);
  1060. qh->is_stopped = 1;
  1061. qh->needs_fixup = (qh->type != USB_ENDPOINT_XFER_CONTROL);
  1062. qh->initial_toggle = uhci_toggle(td_token(uhci, td)) ^
  1063. (ret == -EREMOTEIO);
  1064. } else /* Short packet received */
  1065. ret = uhci_fixup_short_transfer(uhci, qh, urbp);
  1066. return ret;
  1067. }
  1068. /*
  1069. * Isochronous transfers
  1070. */
  1071. static int uhci_submit_isochronous(struct uhci_hcd *uhci, struct urb *urb,
  1072. struct uhci_qh *qh)
  1073. {
  1074. struct uhci_td *td = NULL; /* Since urb->number_of_packets > 0 */
  1075. int i, frame;
  1076. unsigned long destination, status;
  1077. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  1078. /* Values must not be too big (could overflow below) */
  1079. if (urb->interval >= UHCI_NUMFRAMES ||
  1080. urb->number_of_packets >= UHCI_NUMFRAMES)
  1081. return -EFBIG;
  1082. /* Check the period and figure out the starting frame number */
  1083. if (!qh->bandwidth_reserved) {
  1084. qh->period = urb->interval;
  1085. if (urb->transfer_flags & URB_ISO_ASAP) {
  1086. qh->phase = -1; /* Find the best phase */
  1087. i = uhci_check_bandwidth(uhci, qh);
  1088. if (i)
  1089. return i;
  1090. /* Allow a little time to allocate the TDs */
  1091. uhci_get_current_frame_number(uhci);
  1092. frame = uhci->frame_number + 10;
  1093. /* Move forward to the first frame having the
  1094. * correct phase */
  1095. urb->start_frame = frame + ((qh->phase - frame) &
  1096. (qh->period - 1));
  1097. } else {
  1098. i = urb->start_frame - uhci->last_iso_frame;
  1099. if (i <= 0 || i >= UHCI_NUMFRAMES)
  1100. return -EINVAL;
  1101. qh->phase = urb->start_frame & (qh->period - 1);
  1102. i = uhci_check_bandwidth(uhci, qh);
  1103. if (i)
  1104. return i;
  1105. }
  1106. } else if (qh->period != urb->interval) {
  1107. return -EINVAL; /* Can't change the period */
  1108. } else {
  1109. /* Find the next unused frame */
  1110. if (list_empty(&qh->queue)) {
  1111. frame = qh->iso_frame;
  1112. } else {
  1113. struct urb *lurb;
  1114. lurb = list_entry(qh->queue.prev,
  1115. struct urb_priv, node)->urb;
  1116. frame = lurb->start_frame +
  1117. lurb->number_of_packets *
  1118. lurb->interval;
  1119. }
  1120. if (urb->transfer_flags & URB_ISO_ASAP) {
  1121. /* Skip some frames if necessary to insure
  1122. * the start frame is in the future.
  1123. */
  1124. uhci_get_current_frame_number(uhci);
  1125. if (uhci_frame_before_eq(frame, uhci->frame_number)) {
  1126. frame = uhci->frame_number + 1;
  1127. frame += ((qh->phase - frame) &
  1128. (qh->period - 1));
  1129. }
  1130. } /* Otherwise pick up where the last URB leaves off */
  1131. urb->start_frame = frame;
  1132. }
  1133. /* Make sure we won't have to go too far into the future */
  1134. if (uhci_frame_before_eq(uhci->last_iso_frame + UHCI_NUMFRAMES,
  1135. urb->start_frame + urb->number_of_packets *
  1136. urb->interval))
  1137. return -EFBIG;
  1138. status = TD_CTRL_ACTIVE | TD_CTRL_IOS;
  1139. destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
  1140. for (i = 0; i < urb->number_of_packets; i++) {
  1141. td = uhci_alloc_td(uhci);
  1142. if (!td)
  1143. return -ENOMEM;
  1144. uhci_add_td_to_urbp(td, urbp);
  1145. uhci_fill_td(uhci, td, status, destination |
  1146. uhci_explen(urb->iso_frame_desc[i].length),
  1147. urb->transfer_dma +
  1148. urb->iso_frame_desc[i].offset);
  1149. }
  1150. /* Set the interrupt-on-completion flag on the last packet. */
  1151. td->status |= cpu_to_hc32(uhci, TD_CTRL_IOC);
  1152. /* Add the TDs to the frame list */
  1153. frame = urb->start_frame;
  1154. list_for_each_entry(td, &urbp->td_list, list) {
  1155. uhci_insert_td_in_frame_list(uhci, td, frame);
  1156. frame += qh->period;
  1157. }
  1158. if (list_empty(&qh->queue)) {
  1159. qh->iso_packet_desc = &urb->iso_frame_desc[0];
  1160. qh->iso_frame = urb->start_frame;
  1161. }
  1162. qh->skel = SKEL_ISO;
  1163. if (!qh->bandwidth_reserved)
  1164. uhci_reserve_bandwidth(uhci, qh);
  1165. return 0;
  1166. }
  1167. static int uhci_result_isochronous(struct uhci_hcd *uhci, struct urb *urb)
  1168. {
  1169. struct uhci_td *td, *tmp;
  1170. struct urb_priv *urbp = urb->hcpriv;
  1171. struct uhci_qh *qh = urbp->qh;
  1172. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  1173. unsigned int ctrlstat;
  1174. int status;
  1175. int actlength;
  1176. if (uhci_frame_before_eq(uhci->cur_iso_frame, qh->iso_frame))
  1177. return -EINPROGRESS;
  1178. uhci_remove_tds_from_frame(uhci, qh->iso_frame);
  1179. ctrlstat = td_status(uhci, td);
  1180. if (ctrlstat & TD_CTRL_ACTIVE) {
  1181. status = -EXDEV; /* TD was added too late? */
  1182. } else {
  1183. status = uhci_map_status(uhci_status_bits(ctrlstat),
  1184. usb_pipeout(urb->pipe));
  1185. actlength = uhci_actual_length(ctrlstat);
  1186. urb->actual_length += actlength;
  1187. qh->iso_packet_desc->actual_length = actlength;
  1188. qh->iso_packet_desc->status = status;
  1189. }
  1190. if (status)
  1191. urb->error_count++;
  1192. uhci_remove_td_from_urbp(td);
  1193. uhci_free_td(uhci, td);
  1194. qh->iso_frame += qh->period;
  1195. ++qh->iso_packet_desc;
  1196. }
  1197. return 0;
  1198. }
  1199. static int uhci_urb_enqueue(struct usb_hcd *hcd,
  1200. struct urb *urb, gfp_t mem_flags)
  1201. {
  1202. int ret;
  1203. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  1204. unsigned long flags;
  1205. struct urb_priv *urbp;
  1206. struct uhci_qh *qh;
  1207. spin_lock_irqsave(&uhci->lock, flags);
  1208. ret = usb_hcd_link_urb_to_ep(hcd, urb);
  1209. if (ret)
  1210. goto done_not_linked;
  1211. ret = -ENOMEM;
  1212. urbp = uhci_alloc_urb_priv(uhci, urb);
  1213. if (!urbp)
  1214. goto done;
  1215. if (urb->ep->hcpriv)
  1216. qh = urb->ep->hcpriv;
  1217. else {
  1218. qh = uhci_alloc_qh(uhci, urb->dev, urb->ep);
  1219. if (!qh)
  1220. goto err_no_qh;
  1221. }
  1222. urbp->qh = qh;
  1223. switch (qh->type) {
  1224. case USB_ENDPOINT_XFER_CONTROL:
  1225. ret = uhci_submit_control(uhci, urb, qh);
  1226. break;
  1227. case USB_ENDPOINT_XFER_BULK:
  1228. ret = uhci_submit_bulk(uhci, urb, qh);
  1229. break;
  1230. case USB_ENDPOINT_XFER_INT:
  1231. ret = uhci_submit_interrupt(uhci, urb, qh);
  1232. break;
  1233. case USB_ENDPOINT_XFER_ISOC:
  1234. urb->error_count = 0;
  1235. ret = uhci_submit_isochronous(uhci, urb, qh);
  1236. break;
  1237. }
  1238. if (ret != 0)
  1239. goto err_submit_failed;
  1240. /* Add this URB to the QH */
  1241. list_add_tail(&urbp->node, &qh->queue);
  1242. /* If the new URB is the first and only one on this QH then either
  1243. * the QH is new and idle or else it's unlinked and waiting to
  1244. * become idle, so we can activate it right away. But only if the
  1245. * queue isn't stopped. */
  1246. if (qh->queue.next == &urbp->node && !qh->is_stopped) {
  1247. uhci_activate_qh(uhci, qh);
  1248. uhci_urbp_wants_fsbr(uhci, urbp);
  1249. }
  1250. goto done;
  1251. err_submit_failed:
  1252. if (qh->state == QH_STATE_IDLE)
  1253. uhci_make_qh_idle(uhci, qh); /* Reclaim unused QH */
  1254. err_no_qh:
  1255. uhci_free_urb_priv(uhci, urbp);
  1256. done:
  1257. if (ret)
  1258. usb_hcd_unlink_urb_from_ep(hcd, urb);
  1259. done_not_linked:
  1260. spin_unlock_irqrestore(&uhci->lock, flags);
  1261. return ret;
  1262. }
  1263. static int uhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
  1264. {
  1265. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  1266. unsigned long flags;
  1267. struct uhci_qh *qh;
  1268. int rc;
  1269. spin_lock_irqsave(&uhci->lock, flags);
  1270. rc = usb_hcd_check_unlink_urb(hcd, urb, status);
  1271. if (rc)
  1272. goto done;
  1273. qh = ((struct urb_priv *) urb->hcpriv)->qh;
  1274. /* Remove Isochronous TDs from the frame list ASAP */
  1275. if (qh->type == USB_ENDPOINT_XFER_ISOC) {
  1276. uhci_unlink_isochronous_tds(uhci, urb);
  1277. mb();
  1278. /* If the URB has already started, update the QH unlink time */
  1279. uhci_get_current_frame_number(uhci);
  1280. if (uhci_frame_before_eq(urb->start_frame, uhci->frame_number))
  1281. qh->unlink_frame = uhci->frame_number;
  1282. }
  1283. uhci_unlink_qh(uhci, qh);
  1284. done:
  1285. spin_unlock_irqrestore(&uhci->lock, flags);
  1286. return rc;
  1287. }
  1288. /*
  1289. * Finish unlinking an URB and give it back
  1290. */
  1291. static void uhci_giveback_urb(struct uhci_hcd *uhci, struct uhci_qh *qh,
  1292. struct urb *urb, int status)
  1293. __releases(uhci->lock)
  1294. __acquires(uhci->lock)
  1295. {
  1296. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  1297. if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
  1298. /* Subtract off the length of the SETUP packet from
  1299. * urb->actual_length.
  1300. */
  1301. urb->actual_length -= min_t(u32, 8, urb->actual_length);
  1302. }
  1303. /* When giving back the first URB in an Isochronous queue,
  1304. * reinitialize the QH's iso-related members for the next URB. */
  1305. else if (qh->type == USB_ENDPOINT_XFER_ISOC &&
  1306. urbp->node.prev == &qh->queue &&
  1307. urbp->node.next != &qh->queue) {
  1308. struct urb *nurb = list_entry(urbp->node.next,
  1309. struct urb_priv, node)->urb;
  1310. qh->iso_packet_desc = &nurb->iso_frame_desc[0];
  1311. qh->iso_frame = nurb->start_frame;
  1312. }
  1313. /* Take the URB off the QH's queue. If the queue is now empty,
  1314. * this is a perfect time for a toggle fixup. */
  1315. list_del_init(&urbp->node);
  1316. if (list_empty(&qh->queue) && qh->needs_fixup) {
  1317. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  1318. usb_pipeout(urb->pipe), qh->initial_toggle);
  1319. qh->needs_fixup = 0;
  1320. }
  1321. uhci_free_urb_priv(uhci, urbp);
  1322. usb_hcd_unlink_urb_from_ep(uhci_to_hcd(uhci), urb);
  1323. spin_unlock(&uhci->lock);
  1324. usb_hcd_giveback_urb(uhci_to_hcd(uhci), urb, status);
  1325. spin_lock(&uhci->lock);
  1326. /* If the queue is now empty, we can unlink the QH and give up its
  1327. * reserved bandwidth. */
  1328. if (list_empty(&qh->queue)) {
  1329. uhci_unlink_qh(uhci, qh);
  1330. if (qh->bandwidth_reserved)
  1331. uhci_release_bandwidth(uhci, qh);
  1332. }
  1333. }
  1334. /*
  1335. * Scan the URBs in a QH's queue
  1336. */
  1337. #define QH_FINISHED_UNLINKING(qh) \
  1338. (qh->state == QH_STATE_UNLINKING && \
  1339. uhci->frame_number + uhci->is_stopped != qh->unlink_frame)
  1340. static void uhci_scan_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  1341. {
  1342. struct urb_priv *urbp;
  1343. struct urb *urb;
  1344. int status;
  1345. while (!list_empty(&qh->queue)) {
  1346. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1347. urb = urbp->urb;
  1348. if (qh->type == USB_ENDPOINT_XFER_ISOC)
  1349. status = uhci_result_isochronous(uhci, urb);
  1350. else
  1351. status = uhci_result_common(uhci, urb);
  1352. if (status == -EINPROGRESS)
  1353. break;
  1354. /* Dequeued but completed URBs can't be given back unless
  1355. * the QH is stopped or has finished unlinking. */
  1356. if (urb->unlinked) {
  1357. if (QH_FINISHED_UNLINKING(qh))
  1358. qh->is_stopped = 1;
  1359. else if (!qh->is_stopped)
  1360. return;
  1361. }
  1362. uhci_giveback_urb(uhci, qh, urb, status);
  1363. if (status < 0)
  1364. break;
  1365. }
  1366. /* If the QH is neither stopped nor finished unlinking (normal case),
  1367. * our work here is done. */
  1368. if (QH_FINISHED_UNLINKING(qh))
  1369. qh->is_stopped = 1;
  1370. else if (!qh->is_stopped)
  1371. return;
  1372. /* Otherwise give back each of the dequeued URBs */
  1373. restart:
  1374. list_for_each_entry(urbp, &qh->queue, node) {
  1375. urb = urbp->urb;
  1376. if (urb->unlinked) {
  1377. /* Fix up the TD links and save the toggles for
  1378. * non-Isochronous queues. For Isochronous queues,
  1379. * test for too-recent dequeues. */
  1380. if (!uhci_cleanup_queue(uhci, qh, urb)) {
  1381. qh->is_stopped = 0;
  1382. return;
  1383. }
  1384. uhci_giveback_urb(uhci, qh, urb, 0);
  1385. goto restart;
  1386. }
  1387. }
  1388. qh->is_stopped = 0;
  1389. /* There are no more dequeued URBs. If there are still URBs on the
  1390. * queue, the QH can now be re-activated. */
  1391. if (!list_empty(&qh->queue)) {
  1392. if (qh->needs_fixup)
  1393. uhci_fixup_toggles(uhci, qh, 0);
  1394. /* If the first URB on the queue wants FSBR but its time
  1395. * limit has expired, set the next TD to interrupt on
  1396. * completion before reactivating the QH. */
  1397. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1398. if (urbp->fsbr && qh->wait_expired) {
  1399. struct uhci_td *td = list_entry(urbp->td_list.next,
  1400. struct uhci_td, list);
  1401. td->status |= cpu_to_hc32(uhci, TD_CTRL_IOC);
  1402. }
  1403. uhci_activate_qh(uhci, qh);
  1404. }
  1405. /* The queue is empty. The QH can become idle if it is fully
  1406. * unlinked. */
  1407. else if (QH_FINISHED_UNLINKING(qh))
  1408. uhci_make_qh_idle(uhci, qh);
  1409. }
  1410. /*
  1411. * Check for queues that have made some forward progress.
  1412. * Returns 0 if the queue is not Isochronous, is ACTIVE, and
  1413. * has not advanced since last examined; 1 otherwise.
  1414. *
  1415. * Early Intel controllers have a bug which causes qh->element sometimes
  1416. * not to advance when a TD completes successfully. The queue remains
  1417. * stuck on the inactive completed TD. We detect such cases and advance
  1418. * the element pointer by hand.
  1419. */
  1420. static int uhci_advance_check(struct uhci_hcd *uhci, struct uhci_qh *qh)
  1421. {
  1422. struct urb_priv *urbp = NULL;
  1423. struct uhci_td *td;
  1424. int ret = 1;
  1425. unsigned status;
  1426. if (qh->type == USB_ENDPOINT_XFER_ISOC)
  1427. goto done;
  1428. /* Treat an UNLINKING queue as though it hasn't advanced.
  1429. * This is okay because reactivation will treat it as though
  1430. * it has advanced, and if it is going to become IDLE then
  1431. * this doesn't matter anyway. Furthermore it's possible
  1432. * for an UNLINKING queue not to have any URBs at all, or
  1433. * for its first URB not to have any TDs (if it was dequeued
  1434. * just as it completed). So it's not easy in any case to
  1435. * test whether such queues have advanced. */
  1436. if (qh->state != QH_STATE_ACTIVE) {
  1437. urbp = NULL;
  1438. status = 0;
  1439. } else {
  1440. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1441. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  1442. status = td_status(uhci, td);
  1443. if (!(status & TD_CTRL_ACTIVE)) {
  1444. /* We're okay, the queue has advanced */
  1445. qh->wait_expired = 0;
  1446. qh->advance_jiffies = jiffies;
  1447. goto done;
  1448. }
  1449. ret = uhci->is_stopped;
  1450. }
  1451. /* The queue hasn't advanced; check for timeout */
  1452. if (qh->wait_expired)
  1453. goto done;
  1454. if (time_after(jiffies, qh->advance_jiffies + QH_WAIT_TIMEOUT)) {
  1455. /* Detect the Intel bug and work around it */
  1456. if (qh->post_td && qh_element(qh) ==
  1457. LINK_TO_TD(uhci, qh->post_td)) {
  1458. qh->element = qh->post_td->link;
  1459. qh->advance_jiffies = jiffies;
  1460. ret = 1;
  1461. goto done;
  1462. }
  1463. qh->wait_expired = 1;
  1464. /* If the current URB wants FSBR, unlink it temporarily
  1465. * so that we can safely set the next TD to interrupt on
  1466. * completion. That way we'll know as soon as the queue
  1467. * starts moving again. */
  1468. if (urbp && urbp->fsbr && !(status & TD_CTRL_IOC))
  1469. uhci_unlink_qh(uhci, qh);
  1470. } else {
  1471. /* Unmoving but not-yet-expired queues keep FSBR alive */
  1472. if (urbp)
  1473. uhci_urbp_wants_fsbr(uhci, urbp);
  1474. }
  1475. done:
  1476. return ret;
  1477. }
  1478. /*
  1479. * Process events in the schedule, but only in one thread at a time
  1480. */
  1481. static void uhci_scan_schedule(struct uhci_hcd *uhci)
  1482. {
  1483. int i;
  1484. struct uhci_qh *qh;
  1485. /* Don't allow re-entrant calls */
  1486. if (uhci->scan_in_progress) {
  1487. uhci->need_rescan = 1;
  1488. return;
  1489. }
  1490. uhci->scan_in_progress = 1;
  1491. rescan:
  1492. uhci->need_rescan = 0;
  1493. uhci->fsbr_is_wanted = 0;
  1494. uhci_clear_next_interrupt(uhci);
  1495. uhci_get_current_frame_number(uhci);
  1496. uhci->cur_iso_frame = uhci->frame_number;
  1497. /* Go through all the QH queues and process the URBs in each one */
  1498. for (i = 0; i < UHCI_NUM_SKELQH - 1; ++i) {
  1499. uhci->next_qh = list_entry(uhci->skelqh[i]->node.next,
  1500. struct uhci_qh, node);
  1501. while ((qh = uhci->next_qh) != uhci->skelqh[i]) {
  1502. uhci->next_qh = list_entry(qh->node.next,
  1503. struct uhci_qh, node);
  1504. if (uhci_advance_check(uhci, qh)) {
  1505. uhci_scan_qh(uhci, qh);
  1506. if (qh->state == QH_STATE_ACTIVE) {
  1507. uhci_urbp_wants_fsbr(uhci,
  1508. list_entry(qh->queue.next, struct urb_priv, node));
  1509. }
  1510. }
  1511. }
  1512. }
  1513. uhci->last_iso_frame = uhci->cur_iso_frame;
  1514. if (uhci->need_rescan)
  1515. goto rescan;
  1516. uhci->scan_in_progress = 0;
  1517. if (uhci->fsbr_is_on && !uhci->fsbr_is_wanted &&
  1518. !uhci->fsbr_expiring) {
  1519. uhci->fsbr_expiring = 1;
  1520. mod_timer(&uhci->fsbr_timer, jiffies + FSBR_OFF_DELAY);
  1521. }
  1522. if (list_empty(&uhci->skel_unlink_qh->node))
  1523. uhci_clear_next_interrupt(uhci);
  1524. else
  1525. uhci_set_next_interrupt(uhci);
  1526. }