r8a66597.h 8.4 KB

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  1. /*
  2. * R8A66597 HCD (Host Controller Driver)
  3. *
  4. * Copyright (C) 2006-2007 Renesas Solutions Corp.
  5. * Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
  6. * Portions Copyright (C) 2004-2005 David Brownell
  7. * Portions Copyright (C) 1999 Roman Weissgaerber
  8. *
  9. * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; version 2 of the License.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  23. *
  24. */
  25. #ifndef __R8A66597_H__
  26. #define __R8A66597_H__
  27. #ifdef CONFIG_HAVE_CLK
  28. #include <linux/clk.h>
  29. #endif
  30. #include <linux/usb/r8a66597.h>
  31. #define R8A66597_MAX_NUM_PIPE 10
  32. #define R8A66597_BUF_BSIZE 8
  33. #define R8A66597_MAX_DEVICE 10
  34. #define R8A66597_MAX_ROOT_HUB 2
  35. #define R8A66597_MAX_SAMPLING 5
  36. #define R8A66597_RH_POLL_TIME 10
  37. #define R8A66597_MAX_DMA_CHANNEL 2
  38. #define R8A66597_PIPE_NO_DMA R8A66597_MAX_DMA_CHANNEL
  39. #define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
  40. #define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9))
  41. #define make_devsel(addr) (addr << 12)
  42. struct r8a66597_pipe_info {
  43. unsigned long timer_interval;
  44. u16 pipenum;
  45. u16 address; /* R8A66597 HCD usb address */
  46. u16 epnum;
  47. u16 maxpacket;
  48. u16 type;
  49. u16 bufnum;
  50. u16 buf_bsize;
  51. u16 interval;
  52. u16 dir_in;
  53. };
  54. struct r8a66597_pipe {
  55. struct r8a66597_pipe_info info;
  56. unsigned long fifoaddr;
  57. unsigned long fifosel;
  58. unsigned long fifoctr;
  59. unsigned long pipectr;
  60. unsigned long pipetre;
  61. unsigned long pipetrn;
  62. };
  63. struct r8a66597_td {
  64. struct r8a66597_pipe *pipe;
  65. struct urb *urb;
  66. struct list_head queue;
  67. u16 type;
  68. u16 pipenum;
  69. int iso_cnt;
  70. u16 address; /* R8A66597's USB address */
  71. u16 maxpacket;
  72. unsigned zero_packet:1;
  73. unsigned short_packet:1;
  74. unsigned set_address:1;
  75. };
  76. struct r8a66597_device {
  77. u16 address; /* R8A66597's USB address */
  78. u16 hub_port;
  79. u16 root_port;
  80. unsigned short ep_in_toggle;
  81. unsigned short ep_out_toggle;
  82. unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
  83. unsigned char dma_map;
  84. enum usb_device_state state;
  85. struct usb_device *udev;
  86. int usb_address;
  87. struct list_head device_list;
  88. };
  89. struct r8a66597_root_hub {
  90. u32 port;
  91. u16 old_syssts;
  92. int scount;
  93. struct r8a66597_device *dev;
  94. };
  95. struct r8a66597 {
  96. spinlock_t lock;
  97. void __iomem *reg;
  98. #ifdef CONFIG_HAVE_CLK
  99. struct clk *clk;
  100. #endif
  101. struct r8a66597_platdata *pdata;
  102. struct r8a66597_device device0;
  103. struct r8a66597_root_hub root_hub[R8A66597_MAX_ROOT_HUB];
  104. struct list_head pipe_queue[R8A66597_MAX_NUM_PIPE];
  105. struct timer_list rh_timer;
  106. struct timer_list td_timer[R8A66597_MAX_NUM_PIPE];
  107. struct timer_list interval_timer[R8A66597_MAX_NUM_PIPE];
  108. unsigned short address_map;
  109. unsigned short timeout_map;
  110. unsigned short interval_map;
  111. unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
  112. unsigned char dma_map;
  113. unsigned int max_root_hub;
  114. struct list_head child_device;
  115. unsigned long child_connect_map[4];
  116. unsigned bus_suspended:1;
  117. unsigned irq_sense_low:1;
  118. };
  119. static inline struct r8a66597 *hcd_to_r8a66597(struct usb_hcd *hcd)
  120. {
  121. return (struct r8a66597 *)(hcd->hcd_priv);
  122. }
  123. static inline struct usb_hcd *r8a66597_to_hcd(struct r8a66597 *r8a66597)
  124. {
  125. return container_of((void *)r8a66597, struct usb_hcd, hcd_priv);
  126. }
  127. static inline struct r8a66597_td *r8a66597_get_td(struct r8a66597 *r8a66597,
  128. u16 pipenum)
  129. {
  130. if (unlikely(list_empty(&r8a66597->pipe_queue[pipenum])))
  131. return NULL;
  132. return list_entry(r8a66597->pipe_queue[pipenum].next,
  133. struct r8a66597_td, queue);
  134. }
  135. static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597,
  136. u16 pipenum)
  137. {
  138. struct r8a66597_td *td;
  139. td = r8a66597_get_td(r8a66597, pipenum);
  140. return (td ? td->urb : NULL);
  141. }
  142. static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
  143. {
  144. return ioread16(r8a66597->reg + offset);
  145. }
  146. static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
  147. unsigned long offset, u16 *buf,
  148. int len)
  149. {
  150. void __iomem *fifoaddr = r8a66597->reg + offset;
  151. unsigned long count;
  152. if (r8a66597->pdata->on_chip) {
  153. count = len / 4;
  154. ioread32_rep(fifoaddr, buf, count);
  155. if (len & 0x00000003) {
  156. unsigned long tmp = ioread32(fifoaddr);
  157. memcpy((unsigned char *)buf + count * 4, &tmp,
  158. len & 0x03);
  159. }
  160. } else {
  161. len = (len + 1) / 2;
  162. ioread16_rep(fifoaddr, buf, len);
  163. }
  164. }
  165. static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
  166. unsigned long offset)
  167. {
  168. iowrite16(val, r8a66597->reg + offset);
  169. }
  170. static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
  171. unsigned long offset, u16 *buf,
  172. int len)
  173. {
  174. void __iomem *fifoaddr = r8a66597->reg + offset;
  175. unsigned long count;
  176. unsigned char *pb;
  177. int i;
  178. if (r8a66597->pdata->on_chip) {
  179. count = len / 4;
  180. iowrite32_rep(fifoaddr, buf, count);
  181. if (len & 0x00000003) {
  182. pb = (unsigned char *)buf + count * 4;
  183. for (i = 0; i < (len & 0x00000003); i++) {
  184. if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
  185. iowrite8(pb[i], fifoaddr + i);
  186. else
  187. iowrite8(pb[i], fifoaddr + 3 - i);
  188. }
  189. }
  190. } else {
  191. int odd = len & 0x0001;
  192. len = len / 2;
  193. iowrite16_rep(fifoaddr, buf, len);
  194. if (unlikely(odd)) {
  195. buf = &buf[len];
  196. iowrite8((unsigned char)*buf, fifoaddr);
  197. }
  198. }
  199. }
  200. static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
  201. u16 val, u16 pat, unsigned long offset)
  202. {
  203. u16 tmp;
  204. tmp = r8a66597_read(r8a66597, offset);
  205. tmp = tmp & (~pat);
  206. tmp = tmp | val;
  207. r8a66597_write(r8a66597, tmp, offset);
  208. }
  209. #define r8a66597_bclr(r8a66597, val, offset) \
  210. r8a66597_mdfy(r8a66597, 0, val, offset)
  211. #define r8a66597_bset(r8a66597, val, offset) \
  212. r8a66597_mdfy(r8a66597, val, 0, offset)
  213. static inline unsigned long get_syscfg_reg(int port)
  214. {
  215. return port == 0 ? SYSCFG0 : SYSCFG1;
  216. }
  217. static inline unsigned long get_syssts_reg(int port)
  218. {
  219. return port == 0 ? SYSSTS0 : SYSSTS1;
  220. }
  221. static inline unsigned long get_dvstctr_reg(int port)
  222. {
  223. return port == 0 ? DVSTCTR0 : DVSTCTR1;
  224. }
  225. static inline unsigned long get_dmacfg_reg(int port)
  226. {
  227. return port == 0 ? DMA0CFG : DMA1CFG;
  228. }
  229. static inline unsigned long get_intenb_reg(int port)
  230. {
  231. return port == 0 ? INTENB1 : INTENB2;
  232. }
  233. static inline unsigned long get_intsts_reg(int port)
  234. {
  235. return port == 0 ? INTSTS1 : INTSTS2;
  236. }
  237. static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
  238. {
  239. unsigned long dvstctr_reg = get_dvstctr_reg(port);
  240. return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
  241. }
  242. static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
  243. int power)
  244. {
  245. unsigned long dvstctr_reg = get_dvstctr_reg(port);
  246. if (r8a66597->pdata->port_power) {
  247. r8a66597->pdata->port_power(port, power);
  248. } else {
  249. if (power)
  250. r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
  251. else
  252. r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
  253. }
  254. }
  255. static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
  256. {
  257. u16 clock = 0;
  258. switch (pdata->xtal) {
  259. case R8A66597_PLATDATA_XTAL_12MHZ:
  260. clock = XTAL12;
  261. break;
  262. case R8A66597_PLATDATA_XTAL_24MHZ:
  263. clock = XTAL24;
  264. break;
  265. case R8A66597_PLATDATA_XTAL_48MHZ:
  266. clock = XTAL48;
  267. break;
  268. default:
  269. printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
  270. break;
  271. }
  272. return clock;
  273. }
  274. #define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
  275. #define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
  276. #define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
  277. #define get_devadd_addr(address) (DEVADD0 + address * 2)
  278. #define enable_irq_ready(r8a66597, pipenum) \
  279. enable_pipe_irq(r8a66597, pipenum, BRDYENB)
  280. #define disable_irq_ready(r8a66597, pipenum) \
  281. disable_pipe_irq(r8a66597, pipenum, BRDYENB)
  282. #define enable_irq_empty(r8a66597, pipenum) \
  283. enable_pipe_irq(r8a66597, pipenum, BEMPENB)
  284. #define disable_irq_empty(r8a66597, pipenum) \
  285. disable_pipe_irq(r8a66597, pipenum, BEMPENB)
  286. #define enable_irq_nrdy(r8a66597, pipenum) \
  287. enable_pipe_irq(r8a66597, pipenum, NRDYENB)
  288. #define disable_irq_nrdy(r8a66597, pipenum) \
  289. disable_pipe_irq(r8a66597, pipenum, NRDYENB)
  290. #endif /* __R8A66597_H__ */