ohci-pci.c 10 KB

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  1. /*
  2. * OHCI HCD (Host Controller Driver) for USB.
  3. *
  4. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  5. * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
  6. *
  7. * [ Initialisation is based on Linus' ]
  8. * [ uhci code and gregs ohci fragments ]
  9. * [ (C) Copyright 1999 Linus Torvalds ]
  10. * [ (C) Copyright 1999 Gregory P. Smith]
  11. *
  12. * PCI Bus Glue
  13. *
  14. * This file is licenced under the GPL.
  15. */
  16. #ifndef CONFIG_PCI
  17. #error "This file is PCI bus glue. CONFIG_PCI must be defined."
  18. #endif
  19. #include <linux/pci.h>
  20. #include <linux/io.h>
  21. /*-------------------------------------------------------------------------*/
  22. static int broken_suspend(struct usb_hcd *hcd)
  23. {
  24. device_init_wakeup(&hcd->self.root_hub->dev, 0);
  25. return 0;
  26. }
  27. /* AMD 756, for most chips (early revs), corrupts register
  28. * values on read ... so enable the vendor workaround.
  29. */
  30. static int ohci_quirk_amd756(struct usb_hcd *hcd)
  31. {
  32. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  33. ohci->flags = OHCI_QUIRK_AMD756;
  34. ohci_dbg (ohci, "AMD756 erratum 4 workaround\n");
  35. /* also erratum 10 (suspend/resume issues) */
  36. return broken_suspend(hcd);
  37. }
  38. /* Apple's OHCI driver has a lot of bizarre workarounds
  39. * for this chip. Evidently control and bulk lists
  40. * can get confused. (B&W G3 models, and ...)
  41. */
  42. static int ohci_quirk_opti(struct usb_hcd *hcd)
  43. {
  44. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  45. ohci_dbg (ohci, "WARNING: OPTi workarounds unavailable\n");
  46. return 0;
  47. }
  48. /* Check for NSC87560. We have to look at the bridge (fn1) to
  49. * identify the USB (fn2). This quirk might apply to more or
  50. * even all NSC stuff.
  51. */
  52. static int ohci_quirk_ns(struct usb_hcd *hcd)
  53. {
  54. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  55. struct pci_dev *b;
  56. b = pci_get_slot (pdev->bus, PCI_DEVFN (PCI_SLOT (pdev->devfn), 1));
  57. if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO
  58. && b->vendor == PCI_VENDOR_ID_NS) {
  59. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  60. ohci->flags |= OHCI_QUIRK_SUPERIO;
  61. ohci_dbg (ohci, "Using NSC SuperIO setup\n");
  62. }
  63. pci_dev_put(b);
  64. return 0;
  65. }
  66. /* Check for Compaq's ZFMicro chipset, which needs short
  67. * delays before control or bulk queues get re-activated
  68. * in finish_unlinks()
  69. */
  70. static int ohci_quirk_zfmicro(struct usb_hcd *hcd)
  71. {
  72. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  73. ohci->flags |= OHCI_QUIRK_ZFMICRO;
  74. ohci_dbg(ohci, "enabled Compaq ZFMicro chipset quirks\n");
  75. return 0;
  76. }
  77. /* Check for Toshiba SCC OHCI which has big endian registers
  78. * and little endian in memory data structures
  79. */
  80. static int ohci_quirk_toshiba_scc(struct usb_hcd *hcd)
  81. {
  82. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  83. /* That chip is only present in the southbridge of some
  84. * cell based platforms which are supposed to select
  85. * CONFIG_USB_OHCI_BIG_ENDIAN_MMIO. We verify here if
  86. * that was the case though.
  87. */
  88. #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
  89. ohci->flags |= OHCI_QUIRK_BE_MMIO;
  90. ohci_dbg (ohci, "enabled big endian Toshiba quirk\n");
  91. return 0;
  92. #else
  93. ohci_err (ohci, "unsupported big endian Toshiba quirk\n");
  94. return -ENXIO;
  95. #endif
  96. }
  97. /* Check for NEC chip and apply quirk for allegedly lost interrupts.
  98. */
  99. static void ohci_quirk_nec_worker(struct work_struct *work)
  100. {
  101. struct ohci_hcd *ohci = container_of(work, struct ohci_hcd, nec_work);
  102. int status;
  103. status = ohci_init(ohci);
  104. if (status != 0) {
  105. ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
  106. "ohci_init", status);
  107. return;
  108. }
  109. status = ohci_restart(ohci);
  110. if (status != 0)
  111. ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
  112. "ohci_restart", status);
  113. }
  114. static int ohci_quirk_nec(struct usb_hcd *hcd)
  115. {
  116. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  117. ohci->flags |= OHCI_QUIRK_NEC;
  118. INIT_WORK(&ohci->nec_work, ohci_quirk_nec_worker);
  119. ohci_dbg (ohci, "enabled NEC chipset lost interrupt quirk\n");
  120. return 0;
  121. }
  122. static int ohci_quirk_amd700(struct usb_hcd *hcd)
  123. {
  124. struct ohci_hcd *ohci = hcd_to_ohci(hcd);
  125. struct pci_dev *amd_smbus_dev;
  126. u8 rev;
  127. if (usb_amd_find_chipset_info())
  128. ohci->flags |= OHCI_QUIRK_AMD_PLL;
  129. amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI,
  130. PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL);
  131. if (!amd_smbus_dev)
  132. return 0;
  133. rev = amd_smbus_dev->revision;
  134. /* SB800 needs pre-fetch fix */
  135. if ((rev >= 0x40) && (rev <= 0x4f)) {
  136. ohci->flags |= OHCI_QUIRK_AMD_PREFETCH;
  137. ohci_dbg(ohci, "enabled AMD prefetch quirk\n");
  138. }
  139. pci_dev_put(amd_smbus_dev);
  140. amd_smbus_dev = NULL;
  141. return 0;
  142. }
  143. static void sb800_prefetch(struct ohci_hcd *ohci, int on)
  144. {
  145. struct pci_dev *pdev;
  146. u16 misc;
  147. pdev = to_pci_dev(ohci_to_hcd(ohci)->self.controller);
  148. pci_read_config_word(pdev, 0x50, &misc);
  149. if (on == 0)
  150. pci_write_config_word(pdev, 0x50, misc & 0xfcff);
  151. else
  152. pci_write_config_word(pdev, 0x50, misc | 0x0300);
  153. }
  154. /* List of quirks for OHCI */
  155. static const struct pci_device_id ohci_pci_quirks[] = {
  156. {
  157. PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x740c),
  158. .driver_data = (unsigned long)ohci_quirk_amd756,
  159. },
  160. {
  161. PCI_DEVICE(PCI_VENDOR_ID_OPTI, 0xc861),
  162. .driver_data = (unsigned long)ohci_quirk_opti,
  163. },
  164. {
  165. PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_ANY_ID),
  166. .driver_data = (unsigned long)ohci_quirk_ns,
  167. },
  168. {
  169. PCI_DEVICE(PCI_VENDOR_ID_COMPAQ, 0xa0f8),
  170. .driver_data = (unsigned long)ohci_quirk_zfmicro,
  171. },
  172. {
  173. PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, 0x01b6),
  174. .driver_data = (unsigned long)ohci_quirk_toshiba_scc,
  175. },
  176. {
  177. PCI_DEVICE(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB),
  178. .driver_data = (unsigned long)ohci_quirk_nec,
  179. },
  180. {
  181. /* Toshiba portege 4000 */
  182. .vendor = PCI_VENDOR_ID_AL,
  183. .device = 0x5237,
  184. .subvendor = PCI_VENDOR_ID_TOSHIBA,
  185. .subdevice = 0x0004,
  186. .driver_data = (unsigned long) broken_suspend,
  187. },
  188. {
  189. PCI_DEVICE(PCI_VENDOR_ID_ITE, 0x8152),
  190. .driver_data = (unsigned long) broken_suspend,
  191. },
  192. {
  193. PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4397),
  194. .driver_data = (unsigned long)ohci_quirk_amd700,
  195. },
  196. {
  197. PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4398),
  198. .driver_data = (unsigned long)ohci_quirk_amd700,
  199. },
  200. {
  201. PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4399),
  202. .driver_data = (unsigned long)ohci_quirk_amd700,
  203. },
  204. /* FIXME for some of the early AMD 760 southbridges, OHCI
  205. * won't work at all. blacklist them.
  206. */
  207. {},
  208. };
  209. static int ohci_pci_reset (struct usb_hcd *hcd)
  210. {
  211. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  212. int ret = 0;
  213. if (hcd->self.controller) {
  214. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  215. const struct pci_device_id *quirk_id;
  216. quirk_id = pci_match_id(ohci_pci_quirks, pdev);
  217. if (quirk_id != NULL) {
  218. int (*quirk)(struct usb_hcd *ohci);
  219. quirk = (void *)quirk_id->driver_data;
  220. ret = quirk(hcd);
  221. }
  222. }
  223. if (ret == 0) {
  224. ohci_hcd_init (ohci);
  225. return ohci_init (ohci);
  226. }
  227. return ret;
  228. }
  229. static int __devinit ohci_pci_start (struct usb_hcd *hcd)
  230. {
  231. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  232. int ret;
  233. #ifdef CONFIG_PM /* avoid warnings about unused pdev */
  234. if (hcd->self.controller) {
  235. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  236. /* RWC may not be set for add-in PCI cards, since boot
  237. * firmware probably ignored them. This transfers PCI
  238. * PM wakeup capabilities.
  239. */
  240. if (device_can_wakeup(&pdev->dev))
  241. ohci->hc_control |= OHCI_CTRL_RWC;
  242. }
  243. #endif /* CONFIG_PM */
  244. ret = ohci_run (ohci);
  245. if (ret < 0) {
  246. ohci_err (ohci, "can't start\n");
  247. ohci_stop (hcd);
  248. }
  249. return ret;
  250. }
  251. #ifdef CONFIG_PM
  252. static int ohci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
  253. {
  254. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  255. unsigned long flags;
  256. int rc = 0;
  257. /* Root hub was already suspended. Disable irq emission and
  258. * mark HW unaccessible, bail out if RH has been resumed. Use
  259. * the spinlock to properly synchronize with possible pending
  260. * RH suspend or resume activity.
  261. *
  262. * This is still racy as hcd->state is manipulated outside of
  263. * any locks =P But that will be a different fix.
  264. */
  265. spin_lock_irqsave (&ohci->lock, flags);
  266. if (hcd->state != HC_STATE_SUSPENDED) {
  267. rc = -EINVAL;
  268. goto bail;
  269. }
  270. ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
  271. (void)ohci_readl(ohci, &ohci->regs->intrdisable);
  272. clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  273. bail:
  274. spin_unlock_irqrestore (&ohci->lock, flags);
  275. return rc;
  276. }
  277. static int ohci_pci_resume(struct usb_hcd *hcd, bool hibernated)
  278. {
  279. set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  280. /* Make sure resume from hibernation re-enumerates everything */
  281. if (hibernated)
  282. ohci_usb_reset(hcd_to_ohci(hcd));
  283. ohci_finish_controller_resume(hcd);
  284. return 0;
  285. }
  286. #endif /* CONFIG_PM */
  287. /*-------------------------------------------------------------------------*/
  288. static const struct hc_driver ohci_pci_hc_driver = {
  289. .description = hcd_name,
  290. .product_desc = "OHCI Host Controller",
  291. .hcd_priv_size = sizeof(struct ohci_hcd),
  292. /*
  293. * generic hardware linkage
  294. */
  295. .irq = ohci_irq,
  296. .flags = HCD_MEMORY | HCD_USB11,
  297. /*
  298. * basic lifecycle operations
  299. */
  300. .reset = ohci_pci_reset,
  301. .start = ohci_pci_start,
  302. .stop = ohci_stop,
  303. .shutdown = ohci_shutdown,
  304. #ifdef CONFIG_PM
  305. .pci_suspend = ohci_pci_suspend,
  306. .pci_resume = ohci_pci_resume,
  307. #endif
  308. /*
  309. * managing i/o requests and associated device resources
  310. */
  311. .urb_enqueue = ohci_urb_enqueue,
  312. .urb_dequeue = ohci_urb_dequeue,
  313. .endpoint_disable = ohci_endpoint_disable,
  314. /*
  315. * scheduling support
  316. */
  317. .get_frame_number = ohci_get_frame,
  318. /*
  319. * root hub support
  320. */
  321. .hub_status_data = ohci_hub_status_data,
  322. .hub_control = ohci_hub_control,
  323. #ifdef CONFIG_PM
  324. .bus_suspend = ohci_bus_suspend,
  325. .bus_resume = ohci_bus_resume,
  326. #endif
  327. .start_port_reset = ohci_start_port_reset,
  328. };
  329. /*-------------------------------------------------------------------------*/
  330. static const struct pci_device_id pci_ids [] = { {
  331. /* handle any USB OHCI controller */
  332. PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0),
  333. .driver_data = (unsigned long) &ohci_pci_hc_driver,
  334. }, { /* end: all zeroes */ }
  335. };
  336. MODULE_DEVICE_TABLE (pci, pci_ids);
  337. /* pci driver glue; this is a "new style" PCI driver module */
  338. static struct pci_driver ohci_pci_driver = {
  339. .name = (char *) hcd_name,
  340. .id_table = pci_ids,
  341. .probe = usb_hcd_pci_probe,
  342. .remove = usb_hcd_pci_remove,
  343. .shutdown = usb_hcd_pci_shutdown,
  344. #ifdef CONFIG_PM_SLEEP
  345. .driver = {
  346. .pm = &usb_hcd_pci_pm_ops
  347. },
  348. #endif
  349. };