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ehci-fsl.h

ehci-fsl.h 2.0 KB
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  1. /* Copyright (C) 2005-2010 Freescale Semiconductor, Inc.
    2. 

  2.  * Copyright (c) 2005 MontaVista Software
    3. 

  3.  *
    4. 

  4.  * This program is free software; you can redistribute  it and/or modify it
    5. 

  5.  * under  the terms of  the GNU General  Public License as published by the
    6. 

  6.  * Free Software Foundation;  either version 2 of the  License, or (at your
    7. 

  7.  * option) any later version.
    8. 

  8.  *
    9. 

  9.  * This program is distributed in the hope that it will be useful, but
    10. 

  10.  * WITHOUT ANY WARRANTY; without even the implied warranty of
    11. 

  11.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
    12. 

  12.  * General Public License for more details.
    13. 

  13.  *
    14. 

  14.  * You should have received a copy of the  GNU General Public License along
    15. 

  15.  * with this program; if not, write  to the Free Software Foundation, Inc.,
    16. 

  16.  * 675 Mass Ave, Cambridge, MA 02139, USA.
    17. 

  17.  */
    18. 

  18. #ifndef _EHCI_FSL_H
    19. 

  19. #define _EHCI_FSL_H
    20. 

  20. 

  21. /* offsets for the non-ehci registers in the FSL SOC USB controller */
    22. 

  22. #define FSL_SOC_USB_ULPIVP	0x170
    23. 

  23. #define FSL_SOC_USB_PORTSC1	0x184
    24. 

  24. #define PORT_PTS_MSK		(3<<30)
    25. 

  25. #define PORT_PTS_UTMI		(0<<30)
    26. 

  26. #define PORT_PTS_ULPI		(2<<30)
    27. 

  27. #define	PORT_PTS_SERIAL		(3<<30)
    28. 

  28. #define PORT_PTS_PTW		(1<<28)
    29. 

  29. #define FSL_SOC_USB_PORTSC2	0x188
    30. 

  30. #define FSL_SOC_USB_USBMODE	0x1a8
    31. 

  31. #define USBMODE_CM_MASK		(3 << 0)	/* controller mode mask */
    32. 

  32. #define USBMODE_CM_HOST		(3 << 0)	/* controller mode: host */
    33. 

  33. #define USBMODE_ES		(1 << 2)	/* (Big) Endian Select */
    34. 

  34. 

  35. #define FSL_SOC_USB_USBGENCTRL	0x200
    36. 

  36. #define USBGENCTRL_PPP		(1 << 3)
    37. 

  37. #define USBGENCTRL_PFP		(1 << 2)
    38. 

  38. #define FSL_SOC_USB_ISIPHYCTRL	0x204
    39. 

  39. #define ISIPHYCTRL_PXE		(1)
    40. 

  40. #define ISIPHYCTRL_PHYE		(1 << 4)
    41. 

  41. 

  42. #define FSL_SOC_USB_SNOOP1	0x400	/* NOTE: big-endian */
    43. 

  43. #define FSL_SOC_USB_SNOOP2	0x404	/* NOTE: big-endian */
    44. 

  44. #define FSL_SOC_USB_AGECNTTHRSH	0x408	/* NOTE: big-endian */
    45. 

  45. #define FSL_SOC_USB_PRICTRL	0x40c	/* NOTE: big-endian */
    46. 

  46. #define FSL_SOC_USB_SICTRL	0x410	/* NOTE: big-endian */
    47. 

  47. #define FSL_SOC_USB_CTRL	0x500	/* NOTE: big-endian */
    48. 

  48. #define CTRL_UTMI_PHY_EN	(1<<9)
    49. 

  49. #define SNOOP_SIZE_2GB		0x1e
    50. 

  50. #endif				/* _EHCI_FSL_H */
    51. 

  51.