fsl_mxc_udc.c 2.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125
  1. /*
  2. * Copyright (C) 2009
  3. * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
  4. *
  5. * Description:
  6. * Helper routines for i.MX3x SoCs from Freescale, needed by the fsl_usb2_udc.c
  7. * driver to function correctly on these systems.
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. */
  14. #include <linux/clk.h>
  15. #include <linux/delay.h>
  16. #include <linux/err.h>
  17. #include <linux/fsl_devices.h>
  18. #include <linux/platform_device.h>
  19. #include <mach/hardware.h>
  20. static struct clk *mxc_ahb_clk;
  21. static struct clk *mxc_usb_clk;
  22. /* workaround ENGcm09152 for i.MX35 */
  23. #define USBPHYCTRL_OTGBASE_OFFSET 0x608
  24. #define USBPHYCTRL_EVDO (1 << 23)
  25. int fsl_udc_clk_init(struct platform_device *pdev)
  26. {
  27. struct fsl_usb2_platform_data *pdata;
  28. unsigned long freq;
  29. int ret;
  30. pdata = pdev->dev.platform_data;
  31. if (!cpu_is_mx35() && !cpu_is_mx25()) {
  32. mxc_ahb_clk = clk_get(&pdev->dev, "usb_ahb");
  33. if (IS_ERR(mxc_ahb_clk))
  34. return PTR_ERR(mxc_ahb_clk);
  35. ret = clk_enable(mxc_ahb_clk);
  36. if (ret < 0) {
  37. dev_err(&pdev->dev, "clk_enable(\"usb_ahb\") failed\n");
  38. goto eenahb;
  39. }
  40. }
  41. /* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */
  42. mxc_usb_clk = clk_get(&pdev->dev, "usb");
  43. if (IS_ERR(mxc_usb_clk)) {
  44. dev_err(&pdev->dev, "clk_get(\"usb\") failed\n");
  45. ret = PTR_ERR(mxc_usb_clk);
  46. goto egusb;
  47. }
  48. if (!cpu_is_mx51()) {
  49. freq = clk_get_rate(mxc_usb_clk);
  50. if (pdata->phy_mode != FSL_USB2_PHY_ULPI &&
  51. (freq < 59999000 || freq > 60001000)) {
  52. dev_err(&pdev->dev, "USB_CLK=%lu, should be 60MHz\n", freq);
  53. ret = -EINVAL;
  54. goto eclkrate;
  55. }
  56. }
  57. ret = clk_enable(mxc_usb_clk);
  58. if (ret < 0) {
  59. dev_err(&pdev->dev, "clk_enable(\"usb_clk\") failed\n");
  60. goto eenusb;
  61. }
  62. return 0;
  63. eenusb:
  64. eclkrate:
  65. clk_put(mxc_usb_clk);
  66. mxc_usb_clk = NULL;
  67. egusb:
  68. if (!cpu_is_mx35())
  69. clk_disable(mxc_ahb_clk);
  70. eenahb:
  71. if (!cpu_is_mx35())
  72. clk_put(mxc_ahb_clk);
  73. return ret;
  74. }
  75. void fsl_udc_clk_finalize(struct platform_device *pdev)
  76. {
  77. struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
  78. #if defined(CONFIG_SOC_IMX35)
  79. if (cpu_is_mx35()) {
  80. unsigned int v;
  81. /* workaround ENGcm09152 for i.MX35 */
  82. if (pdata->workaround & FLS_USB2_WORKAROUND_ENGCM09152) {
  83. v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
  84. USBPHYCTRL_OTGBASE_OFFSET));
  85. writel(v | USBPHYCTRL_EVDO,
  86. MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
  87. USBPHYCTRL_OTGBASE_OFFSET));
  88. }
  89. }
  90. #endif
  91. /* ULPI transceivers don't need usbpll */
  92. if (pdata->phy_mode == FSL_USB2_PHY_ULPI) {
  93. clk_disable(mxc_usb_clk);
  94. clk_put(mxc_usb_clk);
  95. mxc_usb_clk = NULL;
  96. }
  97. }
  98. void fsl_udc_clk_release(void)
  99. {
  100. if (mxc_usb_clk) {
  101. clk_disable(mxc_usb_clk);
  102. clk_put(mxc_usb_clk);
  103. }
  104. if (!cpu_is_mx35()) {
  105. clk_disable(mxc_ahb_clk);
  106. clk_put(mxc_ahb_clk);
  107. }
  108. }