sb1250-duart.c 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975
  1. /*
  2. * Support for the asynchronous serial interface (DUART) included
  3. * in the BCM1250 and derived System-On-a-Chip (SOC) devices.
  4. *
  5. * Copyright (c) 2007 Maciej W. Rozycki
  6. *
  7. * Derived from drivers/char/sb1250_duart.c for which the following
  8. * copyright applies:
  9. *
  10. * Copyright (c) 2000, 2001, 2002, 2003, 2004 Broadcom Corporation
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License
  14. * as published by the Free Software Foundation; either version
  15. * 2 of the License, or (at your option) any later version.
  16. *
  17. * References:
  18. *
  19. * "BCM1250/BCM1125/BCM1125H User Manual", Broadcom Corporation
  20. */
  21. #if defined(CONFIG_SERIAL_SB1250_DUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  22. #define SUPPORT_SYSRQ
  23. #endif
  24. #include <linux/compiler.h>
  25. #include <linux/console.h>
  26. #include <linux/delay.h>
  27. #include <linux/errno.h>
  28. #include <linux/init.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/ioport.h>
  31. #include <linux/kernel.h>
  32. #include <linux/major.h>
  33. #include <linux/serial.h>
  34. #include <linux/serial_core.h>
  35. #include <linux/spinlock.h>
  36. #include <linux/sysrq.h>
  37. #include <linux/tty.h>
  38. #include <linux/types.h>
  39. #include <asm/atomic.h>
  40. #include <asm/io.h>
  41. #include <asm/war.h>
  42. #include <asm/sibyte/sb1250.h>
  43. #include <asm/sibyte/sb1250_uart.h>
  44. #include <asm/sibyte/swarm.h>
  45. #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
  46. #include <asm/sibyte/bcm1480_regs.h>
  47. #include <asm/sibyte/bcm1480_int.h>
  48. #define SBD_CHANREGS(line) A_BCM1480_DUART_CHANREG((line), 0)
  49. #define SBD_CTRLREGS(line) A_BCM1480_DUART_CTRLREG((line), 0)
  50. #define SBD_INT(line) (K_BCM1480_INT_UART_0 + (line))
  51. #define DUART_CHANREG_SPACING BCM1480_DUART_CHANREG_SPACING
  52. #define R_DUART_IMRREG(line) R_BCM1480_DUART_IMRREG(line)
  53. #define R_DUART_INCHREG(line) R_BCM1480_DUART_INCHREG(line)
  54. #define R_DUART_ISRREG(line) R_BCM1480_DUART_ISRREG(line)
  55. #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
  56. #include <asm/sibyte/sb1250_regs.h>
  57. #include <asm/sibyte/sb1250_int.h>
  58. #define SBD_CHANREGS(line) A_DUART_CHANREG((line), 0)
  59. #define SBD_CTRLREGS(line) A_DUART_CTRLREG(0)
  60. #define SBD_INT(line) (K_INT_UART_0 + (line))
  61. #else
  62. #error invalid SB1250 UART configuration
  63. #endif
  64. MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>");
  65. MODULE_DESCRIPTION("BCM1xxx on-chip DUART serial driver");
  66. MODULE_LICENSE("GPL");
  67. #define DUART_MAX_CHIP 2
  68. #define DUART_MAX_SIDE 2
  69. /*
  70. * Per-port state.
  71. */
  72. struct sbd_port {
  73. struct sbd_duart *duart;
  74. struct uart_port port;
  75. unsigned char __iomem *memctrl;
  76. int tx_stopped;
  77. int initialised;
  78. };
  79. /*
  80. * Per-DUART state for the shared register space.
  81. */
  82. struct sbd_duart {
  83. struct sbd_port sport[2];
  84. unsigned long mapctrl;
  85. atomic_t map_guard;
  86. };
  87. #define to_sport(uport) container_of(uport, struct sbd_port, port)
  88. static struct sbd_duart sbd_duarts[DUART_MAX_CHIP];
  89. /*
  90. * Reading and writing SB1250 DUART registers.
  91. *
  92. * There are three register spaces: two per-channel ones and
  93. * a shared one. We have to define accessors appropriately.
  94. * All registers are 64-bit and all but the Baud Rate Clock
  95. * registers only define 8 least significant bits. There is
  96. * also a workaround to take into account. Raw accessors use
  97. * the full register width, but cooked ones truncate it
  98. * intentionally so that the rest of the driver does not care.
  99. */
  100. static u64 __read_sbdchn(struct sbd_port *sport, int reg)
  101. {
  102. void __iomem *csr = sport->port.membase + reg;
  103. return __raw_readq(csr);
  104. }
  105. static u64 __read_sbdshr(struct sbd_port *sport, int reg)
  106. {
  107. void __iomem *csr = sport->memctrl + reg;
  108. return __raw_readq(csr);
  109. }
  110. static void __write_sbdchn(struct sbd_port *sport, int reg, u64 value)
  111. {
  112. void __iomem *csr = sport->port.membase + reg;
  113. __raw_writeq(value, csr);
  114. }
  115. static void __write_sbdshr(struct sbd_port *sport, int reg, u64 value)
  116. {
  117. void __iomem *csr = sport->memctrl + reg;
  118. __raw_writeq(value, csr);
  119. }
  120. /*
  121. * In bug 1956, we get glitches that can mess up uart registers. This
  122. * "read-mode-reg after any register access" is an accepted workaround.
  123. */
  124. static void __war_sbd1956(struct sbd_port *sport)
  125. {
  126. __read_sbdchn(sport, R_DUART_MODE_REG_1);
  127. __read_sbdchn(sport, R_DUART_MODE_REG_2);
  128. }
  129. static unsigned char read_sbdchn(struct sbd_port *sport, int reg)
  130. {
  131. unsigned char retval;
  132. retval = __read_sbdchn(sport, reg);
  133. if (SIBYTE_1956_WAR)
  134. __war_sbd1956(sport);
  135. return retval;
  136. }
  137. static unsigned char read_sbdshr(struct sbd_port *sport, int reg)
  138. {
  139. unsigned char retval;
  140. retval = __read_sbdshr(sport, reg);
  141. if (SIBYTE_1956_WAR)
  142. __war_sbd1956(sport);
  143. return retval;
  144. }
  145. static void write_sbdchn(struct sbd_port *sport, int reg, unsigned int value)
  146. {
  147. __write_sbdchn(sport, reg, value);
  148. if (SIBYTE_1956_WAR)
  149. __war_sbd1956(sport);
  150. }
  151. static void write_sbdshr(struct sbd_port *sport, int reg, unsigned int value)
  152. {
  153. __write_sbdshr(sport, reg, value);
  154. if (SIBYTE_1956_WAR)
  155. __war_sbd1956(sport);
  156. }
  157. static int sbd_receive_ready(struct sbd_port *sport)
  158. {
  159. return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_RX_RDY;
  160. }
  161. static int sbd_receive_drain(struct sbd_port *sport)
  162. {
  163. int loops = 10000;
  164. while (sbd_receive_ready(sport) && --loops)
  165. read_sbdchn(sport, R_DUART_RX_HOLD);
  166. return loops;
  167. }
  168. static int __maybe_unused sbd_transmit_ready(struct sbd_port *sport)
  169. {
  170. return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_RDY;
  171. }
  172. static int __maybe_unused sbd_transmit_drain(struct sbd_port *sport)
  173. {
  174. int loops = 10000;
  175. while (!sbd_transmit_ready(sport) && --loops)
  176. udelay(2);
  177. return loops;
  178. }
  179. static int sbd_transmit_empty(struct sbd_port *sport)
  180. {
  181. return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_EMT;
  182. }
  183. static int sbd_line_drain(struct sbd_port *sport)
  184. {
  185. int loops = 10000;
  186. while (!sbd_transmit_empty(sport) && --loops)
  187. udelay(2);
  188. return loops;
  189. }
  190. static unsigned int sbd_tx_empty(struct uart_port *uport)
  191. {
  192. struct sbd_port *sport = to_sport(uport);
  193. return sbd_transmit_empty(sport) ? TIOCSER_TEMT : 0;
  194. }
  195. static unsigned int sbd_get_mctrl(struct uart_port *uport)
  196. {
  197. struct sbd_port *sport = to_sport(uport);
  198. unsigned int mctrl, status;
  199. status = read_sbdshr(sport, R_DUART_IN_PORT);
  200. status >>= (uport->line) % 2;
  201. mctrl = (!(status & M_DUART_IN_PIN0_VAL) ? TIOCM_CTS : 0) |
  202. (!(status & M_DUART_IN_PIN4_VAL) ? TIOCM_CAR : 0) |
  203. (!(status & M_DUART_RIN0_PIN) ? TIOCM_RNG : 0) |
  204. (!(status & M_DUART_IN_PIN2_VAL) ? TIOCM_DSR : 0);
  205. return mctrl;
  206. }
  207. static void sbd_set_mctrl(struct uart_port *uport, unsigned int mctrl)
  208. {
  209. struct sbd_port *sport = to_sport(uport);
  210. unsigned int clr = 0, set = 0, mode2;
  211. if (mctrl & TIOCM_DTR)
  212. set |= M_DUART_SET_OPR2;
  213. else
  214. clr |= M_DUART_CLR_OPR2;
  215. if (mctrl & TIOCM_RTS)
  216. set |= M_DUART_SET_OPR0;
  217. else
  218. clr |= M_DUART_CLR_OPR0;
  219. clr <<= (uport->line) % 2;
  220. set <<= (uport->line) % 2;
  221. mode2 = read_sbdchn(sport, R_DUART_MODE_REG_2);
  222. mode2 &= ~M_DUART_CHAN_MODE;
  223. if (mctrl & TIOCM_LOOP)
  224. mode2 |= V_DUART_CHAN_MODE_LCL_LOOP;
  225. else
  226. mode2 |= V_DUART_CHAN_MODE_NORMAL;
  227. write_sbdshr(sport, R_DUART_CLEAR_OPR, clr);
  228. write_sbdshr(sport, R_DUART_SET_OPR, set);
  229. write_sbdchn(sport, R_DUART_MODE_REG_2, mode2);
  230. }
  231. static void sbd_stop_tx(struct uart_port *uport)
  232. {
  233. struct sbd_port *sport = to_sport(uport);
  234. write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS);
  235. sport->tx_stopped = 1;
  236. };
  237. static void sbd_start_tx(struct uart_port *uport)
  238. {
  239. struct sbd_port *sport = to_sport(uport);
  240. unsigned int mask;
  241. /* Enable tx interrupts. */
  242. mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
  243. mask |= M_DUART_IMR_TX;
  244. write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
  245. /* Go!, go!, go!... */
  246. write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN);
  247. sport->tx_stopped = 0;
  248. };
  249. static void sbd_stop_rx(struct uart_port *uport)
  250. {
  251. struct sbd_port *sport = to_sport(uport);
  252. write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0);
  253. };
  254. static void sbd_enable_ms(struct uart_port *uport)
  255. {
  256. struct sbd_port *sport = to_sport(uport);
  257. write_sbdchn(sport, R_DUART_AUXCTL_X,
  258. M_DUART_CIN_CHNG_ENA | M_DUART_CTS_CHNG_ENA);
  259. }
  260. static void sbd_break_ctl(struct uart_port *uport, int break_state)
  261. {
  262. struct sbd_port *sport = to_sport(uport);
  263. if (break_state == -1)
  264. write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_START_BREAK);
  265. else
  266. write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_STOP_BREAK);
  267. }
  268. static void sbd_receive_chars(struct sbd_port *sport)
  269. {
  270. struct uart_port *uport = &sport->port;
  271. struct uart_icount *icount;
  272. unsigned int status, ch, flag;
  273. int count;
  274. for (count = 16; count; count--) {
  275. status = read_sbdchn(sport, R_DUART_STATUS);
  276. if (!(status & M_DUART_RX_RDY))
  277. break;
  278. ch = read_sbdchn(sport, R_DUART_RX_HOLD);
  279. flag = TTY_NORMAL;
  280. icount = &uport->icount;
  281. icount->rx++;
  282. if (unlikely(status &
  283. (M_DUART_RCVD_BRK | M_DUART_FRM_ERR |
  284. M_DUART_PARITY_ERR | M_DUART_OVRUN_ERR))) {
  285. if (status & M_DUART_RCVD_BRK) {
  286. icount->brk++;
  287. if (uart_handle_break(uport))
  288. continue;
  289. } else if (status & M_DUART_FRM_ERR)
  290. icount->frame++;
  291. else if (status & M_DUART_PARITY_ERR)
  292. icount->parity++;
  293. if (status & M_DUART_OVRUN_ERR)
  294. icount->overrun++;
  295. status &= uport->read_status_mask;
  296. if (status & M_DUART_RCVD_BRK)
  297. flag = TTY_BREAK;
  298. else if (status & M_DUART_FRM_ERR)
  299. flag = TTY_FRAME;
  300. else if (status & M_DUART_PARITY_ERR)
  301. flag = TTY_PARITY;
  302. }
  303. if (uart_handle_sysrq_char(uport, ch))
  304. continue;
  305. uart_insert_char(uport, status, M_DUART_OVRUN_ERR, ch, flag);
  306. }
  307. tty_flip_buffer_push(uport->state->port.tty);
  308. }
  309. static void sbd_transmit_chars(struct sbd_port *sport)
  310. {
  311. struct uart_port *uport = &sport->port;
  312. struct circ_buf *xmit = &sport->port.state->xmit;
  313. unsigned int mask;
  314. int stop_tx;
  315. /* XON/XOFF chars. */
  316. if (sport->port.x_char) {
  317. write_sbdchn(sport, R_DUART_TX_HOLD, sport->port.x_char);
  318. sport->port.icount.tx++;
  319. sport->port.x_char = 0;
  320. return;
  321. }
  322. /* If nothing to do or stopped or hardware stopped. */
  323. stop_tx = (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port));
  324. /* Send char. */
  325. if (!stop_tx) {
  326. write_sbdchn(sport, R_DUART_TX_HOLD, xmit->buf[xmit->tail]);
  327. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  328. sport->port.icount.tx++;
  329. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  330. uart_write_wakeup(&sport->port);
  331. }
  332. /* Are we are done? */
  333. if (stop_tx || uart_circ_empty(xmit)) {
  334. /* Disable tx interrupts. */
  335. mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
  336. mask &= ~M_DUART_IMR_TX;
  337. write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
  338. }
  339. }
  340. static void sbd_status_handle(struct sbd_port *sport)
  341. {
  342. struct uart_port *uport = &sport->port;
  343. unsigned int delta;
  344. delta = read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2));
  345. delta >>= (uport->line) % 2;
  346. if (delta & (M_DUART_IN_PIN0_VAL << S_DUART_IN_PIN_CHNG))
  347. uart_handle_cts_change(uport, !(delta & M_DUART_IN_PIN0_VAL));
  348. if (delta & (M_DUART_IN_PIN2_VAL << S_DUART_IN_PIN_CHNG))
  349. uport->icount.dsr++;
  350. if (delta & ((M_DUART_IN_PIN2_VAL | M_DUART_IN_PIN0_VAL) <<
  351. S_DUART_IN_PIN_CHNG))
  352. wake_up_interruptible(&uport->state->port.delta_msr_wait);
  353. }
  354. static irqreturn_t sbd_interrupt(int irq, void *dev_id)
  355. {
  356. struct sbd_port *sport = dev_id;
  357. struct uart_port *uport = &sport->port;
  358. irqreturn_t status = IRQ_NONE;
  359. unsigned int intstat;
  360. int count;
  361. for (count = 16; count; count--) {
  362. intstat = read_sbdshr(sport,
  363. R_DUART_ISRREG((uport->line) % 2));
  364. intstat &= read_sbdshr(sport,
  365. R_DUART_IMRREG((uport->line) % 2));
  366. intstat &= M_DUART_ISR_ALL;
  367. if (!intstat)
  368. break;
  369. if (intstat & M_DUART_ISR_RX)
  370. sbd_receive_chars(sport);
  371. if (intstat & M_DUART_ISR_IN)
  372. sbd_status_handle(sport);
  373. if (intstat & M_DUART_ISR_TX)
  374. sbd_transmit_chars(sport);
  375. status = IRQ_HANDLED;
  376. }
  377. return status;
  378. }
  379. static int sbd_startup(struct uart_port *uport)
  380. {
  381. struct sbd_port *sport = to_sport(uport);
  382. unsigned int mode1;
  383. int ret;
  384. ret = request_irq(sport->port.irq, sbd_interrupt,
  385. IRQF_SHARED, "sb1250-duart", sport);
  386. if (ret)
  387. return ret;
  388. /* Clear the receive FIFO. */
  389. sbd_receive_drain(sport);
  390. /* Clear the interrupt registers. */
  391. write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT);
  392. read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2));
  393. /* Set rx/tx interrupt to FIFO available. */
  394. mode1 = read_sbdchn(sport, R_DUART_MODE_REG_1);
  395. mode1 &= ~(M_DUART_RX_IRQ_SEL_RXFULL | M_DUART_TX_IRQ_SEL_TXEMPT);
  396. write_sbdchn(sport, R_DUART_MODE_REG_1, mode1);
  397. /* Disable tx, enable rx. */
  398. write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_EN);
  399. sport->tx_stopped = 1;
  400. /* Enable interrupts. */
  401. write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2),
  402. M_DUART_IMR_IN | M_DUART_IMR_RX);
  403. return 0;
  404. }
  405. static void sbd_shutdown(struct uart_port *uport)
  406. {
  407. struct sbd_port *sport = to_sport(uport);
  408. write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS);
  409. sport->tx_stopped = 1;
  410. free_irq(sport->port.irq, sport);
  411. }
  412. static void sbd_init_port(struct sbd_port *sport)
  413. {
  414. struct uart_port *uport = &sport->port;
  415. if (sport->initialised)
  416. return;
  417. /* There is no DUART reset feature, so just set some sane defaults. */
  418. write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_TX);
  419. write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_RX);
  420. write_sbdchn(sport, R_DUART_MODE_REG_1, V_DUART_BITS_PER_CHAR_8);
  421. write_sbdchn(sport, R_DUART_MODE_REG_2, 0);
  422. write_sbdchn(sport, R_DUART_FULL_CTL,
  423. V_DUART_INT_TIME(0) | V_DUART_SIG_FULL(15));
  424. write_sbdchn(sport, R_DUART_OPCR_X, 0);
  425. write_sbdchn(sport, R_DUART_AUXCTL_X, 0);
  426. write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0);
  427. sport->initialised = 1;
  428. }
  429. static void sbd_set_termios(struct uart_port *uport, struct ktermios *termios,
  430. struct ktermios *old_termios)
  431. {
  432. struct sbd_port *sport = to_sport(uport);
  433. unsigned int mode1 = 0, mode2 = 0, aux = 0;
  434. unsigned int mode1mask = 0, mode2mask = 0, auxmask = 0;
  435. unsigned int oldmode1, oldmode2, oldaux;
  436. unsigned int baud, brg;
  437. unsigned int command;
  438. mode1mask |= ~(M_DUART_PARITY_MODE | M_DUART_PARITY_TYPE_ODD |
  439. M_DUART_BITS_PER_CHAR);
  440. mode2mask |= ~M_DUART_STOP_BIT_LEN_2;
  441. auxmask |= ~M_DUART_CTS_CHNG_ENA;
  442. /* Byte size. */
  443. switch (termios->c_cflag & CSIZE) {
  444. case CS5:
  445. case CS6:
  446. /* Unsupported, leave unchanged. */
  447. mode1mask |= M_DUART_PARITY_MODE;
  448. break;
  449. case CS7:
  450. mode1 |= V_DUART_BITS_PER_CHAR_7;
  451. break;
  452. case CS8:
  453. default:
  454. mode1 |= V_DUART_BITS_PER_CHAR_8;
  455. break;
  456. }
  457. /* Parity and stop bits. */
  458. if (termios->c_cflag & CSTOPB)
  459. mode2 |= M_DUART_STOP_BIT_LEN_2;
  460. else
  461. mode2 |= M_DUART_STOP_BIT_LEN_1;
  462. if (termios->c_cflag & PARENB)
  463. mode1 |= V_DUART_PARITY_MODE_ADD;
  464. else
  465. mode1 |= V_DUART_PARITY_MODE_NONE;
  466. if (termios->c_cflag & PARODD)
  467. mode1 |= M_DUART_PARITY_TYPE_ODD;
  468. else
  469. mode1 |= M_DUART_PARITY_TYPE_EVEN;
  470. baud = uart_get_baud_rate(uport, termios, old_termios, 1200, 5000000);
  471. brg = V_DUART_BAUD_RATE(baud);
  472. /* The actual lower bound is 1221bps, so compensate. */
  473. if (brg > M_DUART_CLK_COUNTER)
  474. brg = M_DUART_CLK_COUNTER;
  475. uart_update_timeout(uport, termios->c_cflag, baud);
  476. uport->read_status_mask = M_DUART_OVRUN_ERR;
  477. if (termios->c_iflag & INPCK)
  478. uport->read_status_mask |= M_DUART_FRM_ERR |
  479. M_DUART_PARITY_ERR;
  480. if (termios->c_iflag & (BRKINT | PARMRK))
  481. uport->read_status_mask |= M_DUART_RCVD_BRK;
  482. uport->ignore_status_mask = 0;
  483. if (termios->c_iflag & IGNPAR)
  484. uport->ignore_status_mask |= M_DUART_FRM_ERR |
  485. M_DUART_PARITY_ERR;
  486. if (termios->c_iflag & IGNBRK) {
  487. uport->ignore_status_mask |= M_DUART_RCVD_BRK;
  488. if (termios->c_iflag & IGNPAR)
  489. uport->ignore_status_mask |= M_DUART_OVRUN_ERR;
  490. }
  491. if (termios->c_cflag & CREAD)
  492. command = M_DUART_RX_EN;
  493. else
  494. command = M_DUART_RX_DIS;
  495. if (termios->c_cflag & CRTSCTS)
  496. aux |= M_DUART_CTS_CHNG_ENA;
  497. else
  498. aux &= ~M_DUART_CTS_CHNG_ENA;
  499. spin_lock(&uport->lock);
  500. if (sport->tx_stopped)
  501. command |= M_DUART_TX_DIS;
  502. else
  503. command |= M_DUART_TX_EN;
  504. oldmode1 = read_sbdchn(sport, R_DUART_MODE_REG_1) & mode1mask;
  505. oldmode2 = read_sbdchn(sport, R_DUART_MODE_REG_2) & mode2mask;
  506. oldaux = read_sbdchn(sport, R_DUART_AUXCTL_X) & auxmask;
  507. if (!sport->tx_stopped)
  508. sbd_line_drain(sport);
  509. write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS);
  510. write_sbdchn(sport, R_DUART_MODE_REG_1, mode1 | oldmode1);
  511. write_sbdchn(sport, R_DUART_MODE_REG_2, mode2 | oldmode2);
  512. write_sbdchn(sport, R_DUART_CLK_SEL, brg);
  513. write_sbdchn(sport, R_DUART_AUXCTL_X, aux | oldaux);
  514. write_sbdchn(sport, R_DUART_CMD, command);
  515. spin_unlock(&uport->lock);
  516. }
  517. static const char *sbd_type(struct uart_port *uport)
  518. {
  519. return "SB1250 DUART";
  520. }
  521. static void sbd_release_port(struct uart_port *uport)
  522. {
  523. struct sbd_port *sport = to_sport(uport);
  524. struct sbd_duart *duart = sport->duart;
  525. int map_guard;
  526. iounmap(sport->memctrl);
  527. sport->memctrl = NULL;
  528. iounmap(uport->membase);
  529. uport->membase = NULL;
  530. map_guard = atomic_add_return(-1, &duart->map_guard);
  531. if (!map_guard)
  532. release_mem_region(duart->mapctrl, DUART_CHANREG_SPACING);
  533. release_mem_region(uport->mapbase, DUART_CHANREG_SPACING);
  534. }
  535. static int sbd_map_port(struct uart_port *uport)
  536. {
  537. const char *err = KERN_ERR "sbd: Cannot map MMIO\n";
  538. struct sbd_port *sport = to_sport(uport);
  539. struct sbd_duart *duart = sport->duart;
  540. if (!uport->membase)
  541. uport->membase = ioremap_nocache(uport->mapbase,
  542. DUART_CHANREG_SPACING);
  543. if (!uport->membase) {
  544. printk(err);
  545. return -ENOMEM;
  546. }
  547. if (!sport->memctrl)
  548. sport->memctrl = ioremap_nocache(duart->mapctrl,
  549. DUART_CHANREG_SPACING);
  550. if (!sport->memctrl) {
  551. printk(err);
  552. iounmap(uport->membase);
  553. uport->membase = NULL;
  554. return -ENOMEM;
  555. }
  556. return 0;
  557. }
  558. static int sbd_request_port(struct uart_port *uport)
  559. {
  560. const char *err = KERN_ERR "sbd: Unable to reserve MMIO resource\n";
  561. struct sbd_duart *duart = to_sport(uport)->duart;
  562. int map_guard;
  563. int ret = 0;
  564. if (!request_mem_region(uport->mapbase, DUART_CHANREG_SPACING,
  565. "sb1250-duart")) {
  566. printk(err);
  567. return -EBUSY;
  568. }
  569. map_guard = atomic_add_return(1, &duart->map_guard);
  570. if (map_guard == 1) {
  571. if (!request_mem_region(duart->mapctrl, DUART_CHANREG_SPACING,
  572. "sb1250-duart")) {
  573. atomic_add(-1, &duart->map_guard);
  574. printk(err);
  575. ret = -EBUSY;
  576. }
  577. }
  578. if (!ret) {
  579. ret = sbd_map_port(uport);
  580. if (ret) {
  581. map_guard = atomic_add_return(-1, &duart->map_guard);
  582. if (!map_guard)
  583. release_mem_region(duart->mapctrl,
  584. DUART_CHANREG_SPACING);
  585. }
  586. }
  587. if (ret) {
  588. release_mem_region(uport->mapbase, DUART_CHANREG_SPACING);
  589. return ret;
  590. }
  591. return 0;
  592. }
  593. static void sbd_config_port(struct uart_port *uport, int flags)
  594. {
  595. struct sbd_port *sport = to_sport(uport);
  596. if (flags & UART_CONFIG_TYPE) {
  597. if (sbd_request_port(uport))
  598. return;
  599. uport->type = PORT_SB1250_DUART;
  600. sbd_init_port(sport);
  601. }
  602. }
  603. static int sbd_verify_port(struct uart_port *uport, struct serial_struct *ser)
  604. {
  605. int ret = 0;
  606. if (ser->type != PORT_UNKNOWN && ser->type != PORT_SB1250_DUART)
  607. ret = -EINVAL;
  608. if (ser->irq != uport->irq)
  609. ret = -EINVAL;
  610. if (ser->baud_base != uport->uartclk / 16)
  611. ret = -EINVAL;
  612. return ret;
  613. }
  614. static const struct uart_ops sbd_ops = {
  615. .tx_empty = sbd_tx_empty,
  616. .set_mctrl = sbd_set_mctrl,
  617. .get_mctrl = sbd_get_mctrl,
  618. .stop_tx = sbd_stop_tx,
  619. .start_tx = sbd_start_tx,
  620. .stop_rx = sbd_stop_rx,
  621. .enable_ms = sbd_enable_ms,
  622. .break_ctl = sbd_break_ctl,
  623. .startup = sbd_startup,
  624. .shutdown = sbd_shutdown,
  625. .set_termios = sbd_set_termios,
  626. .type = sbd_type,
  627. .release_port = sbd_release_port,
  628. .request_port = sbd_request_port,
  629. .config_port = sbd_config_port,
  630. .verify_port = sbd_verify_port,
  631. };
  632. /* Initialize SB1250 DUART port structures. */
  633. static void __init sbd_probe_duarts(void)
  634. {
  635. static int probed;
  636. int chip, side;
  637. int max_lines, line;
  638. if (probed)
  639. return;
  640. /* Set the number of available units based on the SOC type. */
  641. switch (soc_type) {
  642. case K_SYS_SOC_TYPE_BCM1x55:
  643. case K_SYS_SOC_TYPE_BCM1x80:
  644. max_lines = 4;
  645. break;
  646. default:
  647. /* Assume at least two serial ports at the normal address. */
  648. max_lines = 2;
  649. break;
  650. }
  651. probed = 1;
  652. for (chip = 0, line = 0; chip < DUART_MAX_CHIP && line < max_lines;
  653. chip++) {
  654. sbd_duarts[chip].mapctrl = SBD_CTRLREGS(line);
  655. for (side = 0; side < DUART_MAX_SIDE && line < max_lines;
  656. side++, line++) {
  657. struct sbd_port *sport = &sbd_duarts[chip].sport[side];
  658. struct uart_port *uport = &sport->port;
  659. sport->duart = &sbd_duarts[chip];
  660. uport->irq = SBD_INT(line);
  661. uport->uartclk = 100000000 / 20 * 16;
  662. uport->fifosize = 16;
  663. uport->iotype = UPIO_MEM;
  664. uport->flags = UPF_BOOT_AUTOCONF;
  665. uport->ops = &sbd_ops;
  666. uport->line = line;
  667. uport->mapbase = SBD_CHANREGS(line);
  668. }
  669. }
  670. }
  671. #ifdef CONFIG_SERIAL_SB1250_DUART_CONSOLE
  672. /*
  673. * Serial console stuff. Very basic, polling driver for doing serial
  674. * console output. The console_lock is held by the caller, so we
  675. * shouldn't be interrupted for more console activity.
  676. */
  677. static void sbd_console_putchar(struct uart_port *uport, int ch)
  678. {
  679. struct sbd_port *sport = to_sport(uport);
  680. sbd_transmit_drain(sport);
  681. write_sbdchn(sport, R_DUART_TX_HOLD, ch);
  682. }
  683. static void sbd_console_write(struct console *co, const char *s,
  684. unsigned int count)
  685. {
  686. int chip = co->index / DUART_MAX_SIDE;
  687. int side = co->index % DUART_MAX_SIDE;
  688. struct sbd_port *sport = &sbd_duarts[chip].sport[side];
  689. struct uart_port *uport = &sport->port;
  690. unsigned long flags;
  691. unsigned int mask;
  692. /* Disable transmit interrupts and enable the transmitter. */
  693. spin_lock_irqsave(&uport->lock, flags);
  694. mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
  695. write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2),
  696. mask & ~M_DUART_IMR_TX);
  697. write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN);
  698. spin_unlock_irqrestore(&uport->lock, flags);
  699. uart_console_write(&sport->port, s, count, sbd_console_putchar);
  700. /* Restore transmit interrupts and the transmitter enable. */
  701. spin_lock_irqsave(&uport->lock, flags);
  702. sbd_line_drain(sport);
  703. if (sport->tx_stopped)
  704. write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS);
  705. write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
  706. spin_unlock_irqrestore(&uport->lock, flags);
  707. }
  708. static int __init sbd_console_setup(struct console *co, char *options)
  709. {
  710. int chip = co->index / DUART_MAX_SIDE;
  711. int side = co->index % DUART_MAX_SIDE;
  712. struct sbd_port *sport = &sbd_duarts[chip].sport[side];
  713. struct uart_port *uport = &sport->port;
  714. int baud = 115200;
  715. int bits = 8;
  716. int parity = 'n';
  717. int flow = 'n';
  718. int ret;
  719. if (!sport->duart)
  720. return -ENXIO;
  721. ret = sbd_map_port(uport);
  722. if (ret)
  723. return ret;
  724. sbd_init_port(sport);
  725. if (options)
  726. uart_parse_options(options, &baud, &parity, &bits, &flow);
  727. return uart_set_options(uport, co, baud, parity, bits, flow);
  728. }
  729. static struct uart_driver sbd_reg;
  730. static struct console sbd_console = {
  731. .name = "duart",
  732. .write = sbd_console_write,
  733. .device = uart_console_device,
  734. .setup = sbd_console_setup,
  735. .flags = CON_PRINTBUFFER,
  736. .index = -1,
  737. .data = &sbd_reg
  738. };
  739. static int __init sbd_serial_console_init(void)
  740. {
  741. sbd_probe_duarts();
  742. register_console(&sbd_console);
  743. return 0;
  744. }
  745. console_initcall(sbd_serial_console_init);
  746. #define SERIAL_SB1250_DUART_CONSOLE &sbd_console
  747. #else
  748. #define SERIAL_SB1250_DUART_CONSOLE NULL
  749. #endif /* CONFIG_SERIAL_SB1250_DUART_CONSOLE */
  750. static struct uart_driver sbd_reg = {
  751. .owner = THIS_MODULE,
  752. .driver_name = "sb1250_duart",
  753. .dev_name = "duart",
  754. .major = TTY_MAJOR,
  755. .minor = SB1250_DUART_MINOR_BASE,
  756. .nr = DUART_MAX_CHIP * DUART_MAX_SIDE,
  757. .cons = SERIAL_SB1250_DUART_CONSOLE,
  758. };
  759. /* Set up the driver and register it. */
  760. static int __init sbd_init(void)
  761. {
  762. int i, ret;
  763. sbd_probe_duarts();
  764. ret = uart_register_driver(&sbd_reg);
  765. if (ret)
  766. return ret;
  767. for (i = 0; i < DUART_MAX_CHIP * DUART_MAX_SIDE; i++) {
  768. struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE];
  769. struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE];
  770. struct uart_port *uport = &sport->port;
  771. if (sport->duart)
  772. uart_add_one_port(&sbd_reg, uport);
  773. }
  774. return 0;
  775. }
  776. /* Unload the driver. Unregister stuff, get ready to go away. */
  777. static void __exit sbd_exit(void)
  778. {
  779. int i;
  780. for (i = DUART_MAX_CHIP * DUART_MAX_SIDE - 1; i >= 0; i--) {
  781. struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE];
  782. struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE];
  783. struct uart_port *uport = &sport->port;
  784. if (sport->duart)
  785. uart_remove_one_port(&sbd_reg, uport);
  786. }
  787. uart_unregister_driver(&sbd_reg);
  788. }
  789. module_init(sbd_init);
  790. module_exit(sbd_exit);