dt3155v4l.c 33 KB

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  1. /***************************************************************************
  2. * Copyright (C) 2006-2010 by Marin Mitov *
  3. * mitov@issp.bas.bg *
  4. * *
  5. * This program is free software; you can redistribute it and/or modify *
  6. * it under the terms of the GNU General Public License as published by *
  7. * the Free Software Foundation; either version 2 of the License, or *
  8. * (at your option) any later version. *
  9. * *
  10. * This program is distributed in the hope that it will be useful, *
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  13. * GNU General Public License for more details. *
  14. * *
  15. * You should have received a copy of the GNU General Public License *
  16. * along with this program; if not, write to the *
  17. * Free Software Foundation, Inc., *
  18. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  19. ***************************************************************************/
  20. #include <linux/version.h>
  21. #include <linux/stringify.h>
  22. #include <linux/delay.h>
  23. #include <linux/kthread.h>
  24. #include <media/v4l2-dev.h>
  25. #include <media/v4l2-ioctl.h>
  26. #include <media/videobuf-dma-contig.h>
  27. #include "dt3155v4l.h"
  28. #define DT3155_VENDOR_ID 0x8086
  29. #define DT3155_DEVICE_ID 0x1223
  30. /* DT3155_CHUNK_SIZE is 4M (2^22) 8 full size buffers */
  31. #define DT3155_CHUNK_SIZE (1U << 22)
  32. #define DT3155_COH_FLAGS (GFP_KERNEL | GFP_DMA32 | __GFP_COLD | __GFP_NOWARN)
  33. #define DT3155_BUF_SIZE (768 * 576)
  34. /* global initializers (for all boards) */
  35. #ifdef CONFIG_DT3155_CCIR
  36. static const u8 csr2_init = VT_50HZ;
  37. #define DT3155_CURRENT_NORM V4L2_STD_625_50
  38. static const unsigned int img_width = 768;
  39. static const unsigned int img_height = 576;
  40. static const unsigned int frames_per_sec = 25;
  41. static const struct v4l2_fmtdesc frame_std[] = {
  42. {
  43. .index = 0,
  44. .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
  45. .flags = 0,
  46. .description = "CCIR/50Hz 8 bits gray",
  47. .pixelformat = V4L2_PIX_FMT_GREY,
  48. },
  49. };
  50. #else
  51. static const u8 csr2_init = VT_60HZ;
  52. #define DT3155_CURRENT_NORM V4L2_STD_525_60
  53. static const unsigned int img_width = 640;
  54. static const unsigned int img_height = 480;
  55. static const unsigned int frames_per_sec = 30;
  56. static const struct v4l2_fmtdesc frame_std[] = {
  57. {
  58. .index = 0,
  59. .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
  60. .flags = 0,
  61. .description = "RS-170/60Hz 8 bits gray",
  62. .pixelformat = V4L2_PIX_FMT_GREY,
  63. },
  64. };
  65. #endif
  66. #define NUM_OF_FORMATS ARRAY_SIZE(frame_std)
  67. static u8 config_init = ACQ_MODE_EVEN;
  68. /**
  69. * read_i2c_reg - reads an internal i2c register
  70. *
  71. * @addr: dt3155 mmio base address
  72. * @index: index (internal address) of register to read
  73. * @data: pointer to byte the read data will be placed in
  74. *
  75. * returns: zero on success or error code
  76. *
  77. * This function starts reading the specified (by index) register
  78. * and busy waits for the process to finish. The result is placed
  79. * in a byte pointed by data.
  80. */
  81. static int
  82. read_i2c_reg(void __iomem *addr, u8 index, u8 *data)
  83. {
  84. u32 tmp = index;
  85. iowrite32((tmp<<17) | IIC_READ, addr + IIC_CSR2);
  86. mmiowb();
  87. udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */
  88. if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) {
  89. /* error: NEW_CYCLE not cleared */
  90. printk(KERN_ERR "dt3155: NEW_CYCLE not cleared\n");
  91. return -EIO;
  92. }
  93. tmp = ioread32(addr + IIC_CSR1);
  94. if (tmp & DIRECT_ABORT) {
  95. /* error: DIRECT_ABORT set */
  96. printk(KERN_ERR "dt3155: DIRECT_ABORT set\n");
  97. /* reset DIRECT_ABORT bit */
  98. iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
  99. return -EIO;
  100. }
  101. *data = tmp>>24;
  102. return 0;
  103. }
  104. /**
  105. * write_i2c_reg - writes to an internal i2c register
  106. *
  107. * @addr: dt3155 mmio base address
  108. * @index: index (internal address) of register to read
  109. * @data: data to be written
  110. *
  111. * returns: zero on success or error code
  112. *
  113. * This function starts writting the specified (by index) register
  114. * and busy waits for the process to finish.
  115. */
  116. static int
  117. write_i2c_reg(void __iomem *addr, u8 index, u8 data)
  118. {
  119. u32 tmp = index;
  120. iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2);
  121. mmiowb();
  122. udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
  123. if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) {
  124. /* error: NEW_CYCLE not cleared */
  125. printk(KERN_ERR "dt3155: NEW_CYCLE not cleared\n");
  126. return -EIO;
  127. }
  128. if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
  129. /* error: DIRECT_ABORT set */
  130. printk(KERN_ERR "dt3155: DIRECT_ABORT set\n");
  131. /* reset DIRECT_ABORT bit */
  132. iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
  133. return -EIO;
  134. }
  135. return 0;
  136. }
  137. /**
  138. * write_i2c_reg_nowait - writes to an internal i2c register
  139. *
  140. * @addr: dt3155 mmio base address
  141. * @index: index (internal address) of register to read
  142. * @data: data to be written
  143. *
  144. * This function starts writting the specified (by index) register
  145. * and then returns.
  146. */
  147. static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data)
  148. {
  149. u32 tmp = index;
  150. iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2);
  151. mmiowb();
  152. }
  153. /**
  154. * wait_i2c_reg - waits the read/write to finish
  155. *
  156. * @addr: dt3155 mmio base address
  157. *
  158. * returns: zero on success or error code
  159. *
  160. * This function waits reading/writting to finish.
  161. */
  162. static int wait_i2c_reg(void __iomem *addr)
  163. {
  164. if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
  165. udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
  166. if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) {
  167. /* error: NEW_CYCLE not cleared */
  168. printk(KERN_ERR "dt3155: NEW_CYCLE not cleared\n");
  169. return -EIO;
  170. }
  171. if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
  172. /* error: DIRECT_ABORT set */
  173. printk(KERN_ERR "dt3155: DIRECT_ABORT set\n");
  174. /* reset DIRECT_ABORT bit */
  175. iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
  176. return -EIO;
  177. }
  178. return 0;
  179. }
  180. static int
  181. dt3155_start_acq(struct dt3155_priv *pd)
  182. {
  183. struct videobuf_buffer *vb = pd->curr_buf;
  184. dma_addr_t dma_addr;
  185. dma_addr = videobuf_to_dma_contig(vb);
  186. iowrite32(dma_addr, pd->regs + EVEN_DMA_START);
  187. iowrite32(dma_addr + vb->width, pd->regs + ODD_DMA_START);
  188. iowrite32(vb->width, pd->regs + EVEN_DMA_STRIDE);
  189. iowrite32(vb->width, pd->regs + ODD_DMA_STRIDE);
  190. /* enable interrupts, clear all irq flags */
  191. iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
  192. FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
  193. iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
  194. FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD,
  195. pd->regs + CSR1);
  196. wait_i2c_reg(pd->regs);
  197. write_i2c_reg(pd->regs, CONFIG, pd->config);
  198. write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);
  199. write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);
  200. /* start the board */
  201. write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);
  202. return 0; /* success */
  203. }
  204. static int
  205. dt3155_stop_acq(struct dt3155_priv *pd)
  206. {
  207. int tmp;
  208. /* stop the board */
  209. wait_i2c_reg(pd->regs);
  210. write_i2c_reg(pd->regs, CSR2, pd->csr2);
  211. /* disable all irqs, clear all irq flags */
  212. iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
  213. write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);
  214. write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);
  215. tmp = ioread32(pd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD);
  216. if (tmp)
  217. printk(KERN_ERR "dt3155: corrupted field %u\n", tmp);
  218. iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
  219. FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD,
  220. pd->regs + CSR1);
  221. return 0;
  222. }
  223. /* Locking: Caller holds q->vb_lock */
  224. static int
  225. dt3155_buf_setup(struct videobuf_queue *q, unsigned int *count,
  226. unsigned int *size)
  227. {
  228. *size = img_width * img_height;
  229. return 0;
  230. }
  231. /* Locking: Caller holds q->vb_lock */
  232. static int
  233. dt3155_buf_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb,
  234. enum v4l2_field field)
  235. {
  236. int ret = 0;
  237. vb->width = img_width;
  238. vb->height = img_height;
  239. vb->size = img_width * img_height;
  240. vb->field = field;
  241. if (vb->state == VIDEOBUF_NEEDS_INIT)
  242. ret = videobuf_iolock(q, vb, NULL);
  243. if (ret) {
  244. vb->state = VIDEOBUF_ERROR;
  245. printk(KERN_ERR "ERROR: videobuf_iolock() failed\n");
  246. videobuf_dma_contig_free(q, vb); /* FIXME: needed? */
  247. } else
  248. vb->state = VIDEOBUF_PREPARED;
  249. return ret;
  250. }
  251. /* Locking: Caller holds q->vb_lock & q->irqlock */
  252. static void
  253. dt3155_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  254. {
  255. struct dt3155_priv *pd = q->priv_data;
  256. if (vb->state != VIDEOBUF_NEEDS_INIT) {
  257. vb->state = VIDEOBUF_QUEUED;
  258. list_add_tail(&vb->queue, &pd->dmaq);
  259. wake_up_interruptible_sync(&pd->do_dma);
  260. } else
  261. vb->state = VIDEOBUF_ERROR;
  262. }
  263. /* Locking: Caller holds q->vb_lock */
  264. static void
  265. dt3155_buf_release(struct videobuf_queue *q, struct videobuf_buffer *vb)
  266. {
  267. if (vb->state == VIDEOBUF_ACTIVE)
  268. videobuf_waiton(q, vb, 0, 0); /* FIXME: cannot be interrupted */
  269. videobuf_dma_contig_free(q, vb);
  270. vb->state = VIDEOBUF_NEEDS_INIT;
  271. }
  272. static struct videobuf_queue_ops vbq_ops = {
  273. .buf_setup = dt3155_buf_setup,
  274. .buf_prepare = dt3155_buf_prepare,
  275. .buf_queue = dt3155_buf_queue,
  276. .buf_release = dt3155_buf_release,
  277. };
  278. static irqreturn_t
  279. dt3155_irq_handler_even(int irq, void *dev_id)
  280. {
  281. struct dt3155_priv *ipd = dev_id;
  282. struct videobuf_buffer *ivb;
  283. dma_addr_t dma_addr;
  284. u32 tmp;
  285. tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD);
  286. if (!tmp)
  287. return IRQ_NONE; /* not our irq */
  288. if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) {
  289. iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START,
  290. ipd->regs + INT_CSR);
  291. ipd->field_count++;
  292. return IRQ_HANDLED; /* start of field irq */
  293. }
  294. if ((tmp & FLD_START) && (tmp & FLD_END_ODD)) {
  295. if (!ipd->stats.start_before_end++)
  296. printk(KERN_ERR "dt3155: irq: START before END\n");
  297. }
  298. /* check for corrupted fields */
  299. /* write_i2c_reg(ipd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE); */
  300. /* write_i2c_reg(ipd->regs, ODD_CSR, CSR_ERROR | CSR_DONE); */
  301. tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD);
  302. if (tmp) {
  303. if (!ipd->stats.corrupted_fields++)
  304. printk(KERN_ERR "dt3155: corrupted field %u\n", tmp);
  305. iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
  306. FLD_DN_ODD | FLD_DN_EVEN |
  307. CAP_CONT_EVEN | CAP_CONT_ODD,
  308. ipd->regs + CSR1);
  309. mmiowb();
  310. }
  311. spin_lock(&ipd->lock);
  312. if (ipd->curr_buf && ipd->curr_buf->state == VIDEOBUF_ACTIVE) {
  313. if (waitqueue_active(&ipd->curr_buf->done)) {
  314. do_gettimeofday(&ipd->curr_buf->ts);
  315. ipd->curr_buf->field_count = ipd->field_count;
  316. ipd->curr_buf->state = VIDEOBUF_DONE;
  317. wake_up(&ipd->curr_buf->done);
  318. } else {
  319. ivb = ipd->curr_buf;
  320. goto load_dma;
  321. }
  322. } else
  323. goto stop_dma;
  324. if (list_empty(&ipd->dmaq))
  325. goto stop_dma;
  326. ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), queue);
  327. list_del(&ivb->queue);
  328. if (ivb->state == VIDEOBUF_QUEUED) {
  329. ivb->state = VIDEOBUF_ACTIVE;
  330. ipd->curr_buf = ivb;
  331. } else
  332. goto stop_dma;
  333. load_dma:
  334. dma_addr = videobuf_to_dma_contig(ivb);
  335. iowrite32(dma_addr, ipd->regs + EVEN_DMA_START);
  336. iowrite32(dma_addr + ivb->width, ipd->regs + ODD_DMA_START);
  337. iowrite32(ivb->width, ipd->regs + EVEN_DMA_STRIDE);
  338. iowrite32(ivb->width, ipd->regs + ODD_DMA_STRIDE);
  339. mmiowb();
  340. /* enable interrupts, clear all irq flags */
  341. iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
  342. FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
  343. spin_unlock(&ipd->lock);
  344. return IRQ_HANDLED;
  345. stop_dma:
  346. ipd->curr_buf = NULL;
  347. /* stop the board */
  348. write_i2c_reg_nowait(ipd->regs, CSR2, ipd->csr2);
  349. /* disable interrupts, clear all irq flags */
  350. iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
  351. spin_unlock(&ipd->lock);
  352. return IRQ_HANDLED;
  353. }
  354. static int
  355. dt3155_threadfn(void *arg)
  356. {
  357. struct dt3155_priv *pd = arg;
  358. struct videobuf_buffer *vb;
  359. unsigned long flags;
  360. while (1) {
  361. wait_event_interruptible(pd->do_dma,
  362. kthread_should_stop() || !list_empty(&pd->dmaq));
  363. if (kthread_should_stop())
  364. break;
  365. spin_lock_irqsave(&pd->lock, flags);
  366. if (pd->curr_buf) /* dma is active */
  367. goto done;
  368. if (list_empty(&pd->dmaq)) /* no empty biffers */
  369. goto done;
  370. vb = list_first_entry(&pd->dmaq, typeof(*vb), queue);
  371. list_del(&vb->queue);
  372. if (vb->state == VIDEOBUF_QUEUED) {
  373. vb->state = VIDEOBUF_ACTIVE;
  374. pd->curr_buf = vb;
  375. spin_unlock_irqrestore(&pd->lock, flags);
  376. /* start dma */
  377. dt3155_start_acq(pd);
  378. continue;
  379. } else
  380. printk(KERN_DEBUG "%s(): This is a BUG\n", __func__);
  381. done:
  382. spin_unlock_irqrestore(&pd->lock, flags);
  383. }
  384. return 0;
  385. }
  386. static int
  387. dt3155_open(struct file *filp)
  388. {
  389. int ret = 0;
  390. struct dt3155_priv *pd = video_drvdata(filp);
  391. printk(KERN_INFO "dt3155: open(): minor: %i\n", pd->vdev->minor);
  392. if (mutex_lock_interruptible(&pd->mux) == -EINTR)
  393. return -ERESTARTSYS;
  394. if (!pd->users) {
  395. pd->vidq = kzalloc(sizeof(*pd->vidq), GFP_KERNEL);
  396. if (!pd->vidq) {
  397. printk(KERN_ERR "dt3155: error: alloc queue\n");
  398. ret = -ENOMEM;
  399. goto err_alloc_queue;
  400. }
  401. videobuf_queue_dma_contig_init(pd->vidq, &vbq_ops,
  402. &pd->pdev->dev, &pd->lock,
  403. V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
  404. sizeof(struct videobuf_buffer), pd, NULL);
  405. /* disable all irqs, clear all irq flags */
  406. iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD,
  407. pd->regs + INT_CSR);
  408. pd->irq_handler = dt3155_irq_handler_even;
  409. ret = request_irq(pd->pdev->irq, pd->irq_handler,
  410. IRQF_SHARED, DT3155_NAME, pd);
  411. if (ret) {
  412. printk(KERN_ERR "dt3155: error: request_irq\n");
  413. goto err_request_irq;
  414. }
  415. pd->curr_buf = NULL;
  416. pd->thread = kthread_run(dt3155_threadfn, pd,
  417. "dt3155_thread_%i", pd->vdev->minor);
  418. if (IS_ERR(pd->thread)) {
  419. printk(KERN_ERR "dt3155: kthread_run() failed\n");
  420. ret = PTR_ERR(pd->thread);
  421. goto err_thread;
  422. }
  423. pd->field_count = 0;
  424. }
  425. pd->users++;
  426. goto done;
  427. err_thread:
  428. free_irq(pd->pdev->irq, pd);
  429. err_request_irq:
  430. kfree(pd->vidq);
  431. pd->vidq = NULL;
  432. err_alloc_queue:
  433. done:
  434. mutex_unlock(&pd->mux);
  435. return ret;
  436. }
  437. static int
  438. dt3155_release(struct file *filp)
  439. {
  440. struct dt3155_priv *pd = video_drvdata(filp);
  441. struct videobuf_buffer *tmp;
  442. unsigned long flags;
  443. int ret = 0;
  444. printk(KERN_INFO "dt3155: release(): minor: %i\n", pd->vdev->minor);
  445. if (mutex_lock_interruptible(&pd->mux) == -EINTR)
  446. return -ERESTARTSYS;
  447. pd->users--;
  448. BUG_ON(pd->users < 0);
  449. if (pd->acq_fp == filp) {
  450. spin_lock_irqsave(&pd->lock, flags);
  451. INIT_LIST_HEAD(&pd->dmaq); /* queue is emptied */
  452. tmp = pd->curr_buf;
  453. spin_unlock_irqrestore(&pd->lock, flags);
  454. if (tmp)
  455. videobuf_waiton(pd->vidq, tmp, 0, 1); /* block, interruptible */
  456. dt3155_stop_acq(pd);
  457. videobuf_stop(pd->vidq);
  458. pd->acq_fp = NULL;
  459. pd->streaming = 0;
  460. }
  461. if (!pd->users) {
  462. kthread_stop(pd->thread);
  463. free_irq(pd->pdev->irq, pd);
  464. kfree(pd->vidq);
  465. pd->vidq = NULL;
  466. }
  467. mutex_unlock(&pd->mux);
  468. return ret;
  469. }
  470. static ssize_t
  471. dt3155_read(struct file *filp, char __user *user, size_t size, loff_t *loff)
  472. {
  473. struct dt3155_priv *pd = video_drvdata(filp);
  474. int ret;
  475. if (mutex_lock_interruptible(&pd->mux) == -EINTR)
  476. return -ERESTARTSYS;
  477. if (!pd->acq_fp) {
  478. pd->acq_fp = filp;
  479. pd->streaming = 0;
  480. } else if (pd->acq_fp != filp) {
  481. ret = -EBUSY;
  482. goto done;
  483. } else if (pd->streaming == 1) {
  484. ret = -EINVAL;
  485. goto done;
  486. }
  487. ret = videobuf_read_stream(pd->vidq, user, size, loff, 0,
  488. filp->f_flags & O_NONBLOCK);
  489. done:
  490. mutex_unlock(&pd->mux);
  491. return ret;
  492. }
  493. static unsigned int
  494. dt3155_poll(struct file *filp, struct poll_table_struct *polltbl)
  495. {
  496. struct dt3155_priv *pd = video_drvdata(filp);
  497. return videobuf_poll_stream(filp, pd->vidq, polltbl);
  498. }
  499. static int
  500. dt3155_mmap(struct file *filp, struct vm_area_struct *vma)
  501. {
  502. struct dt3155_priv *pd = video_drvdata(filp);
  503. return videobuf_mmap_mapper(pd->vidq, vma);
  504. }
  505. static const struct v4l2_file_operations dt3155_fops = {
  506. .owner = THIS_MODULE,
  507. .open = dt3155_open,
  508. .release = dt3155_release,
  509. .read = dt3155_read,
  510. .poll = dt3155_poll,
  511. .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */
  512. .mmap = dt3155_mmap,
  513. };
  514. static int
  515. dt3155_ioc_streamon(struct file *filp, void *p, enum v4l2_buf_type type)
  516. {
  517. struct dt3155_priv *pd = video_drvdata(filp);
  518. int ret = -ERESTARTSYS;
  519. if (mutex_lock_interruptible(&pd->mux) == -EINTR)
  520. return ret;
  521. if (!pd->acq_fp) {
  522. ret = videobuf_streamon(pd->vidq);
  523. if (ret)
  524. goto unlock;
  525. pd->acq_fp = filp;
  526. pd->streaming = 1;
  527. wake_up_interruptible_sync(&pd->do_dma);
  528. } else if (pd->acq_fp == filp) {
  529. pd->streaming = 1;
  530. ret = videobuf_streamon(pd->vidq);
  531. if (!ret)
  532. wake_up_interruptible_sync(&pd->do_dma);
  533. } else
  534. ret = -EBUSY;
  535. unlock:
  536. mutex_unlock(&pd->mux);
  537. return ret;
  538. }
  539. static int
  540. dt3155_ioc_streamoff(struct file *filp, void *p, enum v4l2_buf_type type)
  541. {
  542. struct dt3155_priv *pd = video_drvdata(filp);
  543. struct videobuf_buffer *tmp;
  544. unsigned long flags;
  545. int ret;
  546. ret = videobuf_streamoff(pd->vidq);
  547. if (ret)
  548. return ret;
  549. spin_lock_irqsave(&pd->lock, flags);
  550. tmp = pd->curr_buf;
  551. spin_unlock_irqrestore(&pd->lock, flags);
  552. if (tmp)
  553. videobuf_waiton(pd->vidq, tmp, 0, 1); /* block, interruptible */
  554. return ret;
  555. }
  556. static int
  557. dt3155_ioc_querycap(struct file *filp, void *p, struct v4l2_capability *cap)
  558. {
  559. struct dt3155_priv *pd = video_drvdata(filp);
  560. strcpy(cap->driver, DT3155_NAME);
  561. strcpy(cap->card, DT3155_NAME " frame grabber");
  562. sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev));
  563. cap->version =
  564. KERNEL_VERSION(DT3155_VER_MAJ, DT3155_VER_MIN, DT3155_VER_EXT);
  565. cap->capabilities = V4L2_CAP_VIDEO_CAPTURE |
  566. V4L2_CAP_STREAMING |
  567. V4L2_CAP_READWRITE;
  568. return 0;
  569. }
  570. static int
  571. dt3155_ioc_enum_fmt_vid_cap(struct file *filp, void *p, struct v4l2_fmtdesc *f)
  572. {
  573. if (f->index >= NUM_OF_FORMATS)
  574. return -EINVAL;
  575. *f = frame_std[f->index];
  576. return 0;
  577. }
  578. static int
  579. dt3155_ioc_g_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
  580. {
  581. if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
  582. return -EINVAL;
  583. f->fmt.pix.width = img_width;
  584. f->fmt.pix.height = img_height;
  585. f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY;
  586. f->fmt.pix.field = V4L2_FIELD_NONE;
  587. f->fmt.pix.bytesperline = f->fmt.pix.width;
  588. f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height;
  589. f->fmt.pix.colorspace = 0;
  590. f->fmt.pix.priv = 0;
  591. return 0;
  592. }
  593. static int
  594. dt3155_ioc_try_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
  595. {
  596. if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
  597. return -EINVAL;
  598. if (f->fmt.pix.width == img_width &&
  599. f->fmt.pix.height == img_height &&
  600. f->fmt.pix.pixelformat == V4L2_PIX_FMT_GREY &&
  601. f->fmt.pix.field == V4L2_FIELD_NONE &&
  602. f->fmt.pix.bytesperline == f->fmt.pix.width &&
  603. f->fmt.pix.sizeimage == f->fmt.pix.width * f->fmt.pix.height)
  604. return 0;
  605. else
  606. return -EINVAL;
  607. }
  608. static int
  609. dt3155_ioc_s_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
  610. {
  611. struct dt3155_priv *pd = video_drvdata(filp);
  612. int ret = -ERESTARTSYS;
  613. if (mutex_lock_interruptible(&pd->mux) == -EINTR)
  614. return ret;
  615. if (!pd->acq_fp) {
  616. pd->acq_fp = filp;
  617. pd->streaming = 0;
  618. } else if (pd->acq_fp != filp) {
  619. ret = -EBUSY;
  620. goto done;
  621. }
  622. /* FIXME: we don't change the format for now
  623. if (pd->vidq->streaming || pd->vidq->reading || pd->curr_buff) {
  624. ret = -EBUSY;
  625. goto done;
  626. }
  627. */
  628. ret = dt3155_ioc_g_fmt_vid_cap(filp, p, f);
  629. done:
  630. mutex_unlock(&pd->mux);
  631. return ret;
  632. }
  633. static int
  634. dt3155_ioc_reqbufs(struct file *filp, void *p, struct v4l2_requestbuffers *b)
  635. {
  636. struct dt3155_priv *pd = video_drvdata(filp);
  637. struct videobuf_queue *q = pd->vidq;
  638. int ret = -ERESTARTSYS;
  639. if (b->memory != V4L2_MEMORY_MMAP)
  640. return -EINVAL;
  641. if (mutex_lock_interruptible(&pd->mux) == -EINTR)
  642. return ret;
  643. if (!pd->acq_fp)
  644. pd->acq_fp = filp;
  645. else if (pd->acq_fp != filp) {
  646. ret = -EBUSY;
  647. goto done;
  648. }
  649. pd->streaming = 1;
  650. ret = 0;
  651. done:
  652. mutex_unlock(&pd->mux);
  653. if (ret)
  654. return ret;
  655. if (b->count)
  656. ret = videobuf_reqbufs(q, b);
  657. else { /* FIXME: is it necessary? */
  658. printk(KERN_DEBUG "dt3155: request to free buffers\n");
  659. /* ret = videobuf_mmap_free(q); */
  660. ret = dt3155_ioc_streamoff(filp, p,
  661. V4L2_BUF_TYPE_VIDEO_CAPTURE);
  662. }
  663. return ret;
  664. }
  665. static int
  666. dt3155_ioc_querybuf(struct file *filp, void *p, struct v4l2_buffer *b)
  667. {
  668. struct dt3155_priv *pd = video_drvdata(filp);
  669. struct videobuf_queue *q = pd->vidq;
  670. return videobuf_querybuf(q, b);
  671. }
  672. static int
  673. dt3155_ioc_qbuf(struct file *filp, void *p, struct v4l2_buffer *b)
  674. {
  675. struct dt3155_priv *pd = video_drvdata(filp);
  676. struct videobuf_queue *q = pd->vidq;
  677. int ret;
  678. ret = videobuf_qbuf(q, b);
  679. if (ret)
  680. return ret;
  681. return videobuf_querybuf(q, b);
  682. }
  683. static int
  684. dt3155_ioc_dqbuf(struct file *filp, void *p, struct v4l2_buffer *b)
  685. {
  686. struct dt3155_priv *pd = video_drvdata(filp);
  687. struct videobuf_queue *q = pd->vidq;
  688. return videobuf_dqbuf(q, b, filp->f_flags & O_NONBLOCK);
  689. }
  690. static int
  691. dt3155_ioc_querystd(struct file *filp, void *p, v4l2_std_id *norm)
  692. {
  693. *norm = DT3155_CURRENT_NORM;
  694. return 0;
  695. }
  696. static int
  697. dt3155_ioc_g_std(struct file *filp, void *p, v4l2_std_id *norm)
  698. {
  699. *norm = DT3155_CURRENT_NORM;
  700. return 0;
  701. }
  702. static int
  703. dt3155_ioc_s_std(struct file *filp, void *p, v4l2_std_id *norm)
  704. {
  705. if (*norm & DT3155_CURRENT_NORM)
  706. return 0;
  707. return -EINVAL;
  708. }
  709. static int
  710. dt3155_ioc_enum_input(struct file *filp, void *p, struct v4l2_input *input)
  711. {
  712. if (input->index)
  713. return -EINVAL;
  714. strcpy(input->name, "Coax in");
  715. input->type = V4L2_INPUT_TYPE_CAMERA;
  716. /*
  717. * FIXME: input->std = 0 according to v4l2 API
  718. * VIDIOC_G_STD, VIDIOC_S_STD, VIDIOC_QUERYSTD and VIDIOC_ENUMSTD
  719. * should return -EINVAL
  720. */
  721. input->std = DT3155_CURRENT_NORM;
  722. input->status = 0;/* FIXME: add sync detection & V4L2_IN_ST_NO_H_LOCK */
  723. return 0;
  724. }
  725. static int
  726. dt3155_ioc_g_input(struct file *filp, void *p, unsigned int *i)
  727. {
  728. *i = 0;
  729. return 0;
  730. }
  731. static int
  732. dt3155_ioc_s_input(struct file *filp, void *p, unsigned int i)
  733. {
  734. if (i)
  735. return -EINVAL;
  736. return 0;
  737. }
  738. static int
  739. dt3155_ioc_g_parm(struct file *filp, void *p, struct v4l2_streamparm *parms)
  740. {
  741. if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
  742. return -EINVAL;
  743. parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
  744. parms->parm.capture.capturemode = 0;
  745. parms->parm.capture.timeperframe.numerator = 1001;
  746. parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000;
  747. parms->parm.capture.extendedmode = 0;
  748. parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */
  749. return 0;
  750. }
  751. static int
  752. dt3155_ioc_s_parm(struct file *filp, void *p, struct v4l2_streamparm *parms)
  753. {
  754. if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
  755. return -EINVAL;
  756. parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
  757. parms->parm.capture.capturemode = 0;
  758. parms->parm.capture.timeperframe.numerator = 1001;
  759. parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000;
  760. parms->parm.capture.extendedmode = 0;
  761. parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */
  762. return 0;
  763. }
  764. static const struct v4l2_ioctl_ops dt3155_ioctl_ops = {
  765. .vidioc_streamon = dt3155_ioc_streamon,
  766. .vidioc_streamoff = dt3155_ioc_streamoff,
  767. .vidioc_querycap = dt3155_ioc_querycap,
  768. /*
  769. .vidioc_g_priority = dt3155_ioc_g_priority,
  770. .vidioc_s_priority = dt3155_ioc_s_priority,
  771. */
  772. .vidioc_enum_fmt_vid_cap = dt3155_ioc_enum_fmt_vid_cap,
  773. .vidioc_try_fmt_vid_cap = dt3155_ioc_try_fmt_vid_cap,
  774. .vidioc_g_fmt_vid_cap = dt3155_ioc_g_fmt_vid_cap,
  775. .vidioc_s_fmt_vid_cap = dt3155_ioc_s_fmt_vid_cap,
  776. .vidioc_reqbufs = dt3155_ioc_reqbufs,
  777. .vidioc_querybuf = dt3155_ioc_querybuf,
  778. .vidioc_qbuf = dt3155_ioc_qbuf,
  779. .vidioc_dqbuf = dt3155_ioc_dqbuf,
  780. .vidioc_querystd = dt3155_ioc_querystd,
  781. .vidioc_g_std = dt3155_ioc_g_std,
  782. .vidioc_s_std = dt3155_ioc_s_std,
  783. .vidioc_enum_input = dt3155_ioc_enum_input,
  784. .vidioc_g_input = dt3155_ioc_g_input,
  785. .vidioc_s_input = dt3155_ioc_s_input,
  786. /*
  787. .vidioc_queryctrl = dt3155_ioc_queryctrl,
  788. .vidioc_g_ctrl = dt3155_ioc_g_ctrl,
  789. .vidioc_s_ctrl = dt3155_ioc_s_ctrl,
  790. .vidioc_querymenu = dt3155_ioc_querymenu,
  791. .vidioc_g_ext_ctrls = dt3155_ioc_g_ext_ctrls,
  792. .vidioc_s_ext_ctrls = dt3155_ioc_s_ext_ctrls,
  793. */
  794. .vidioc_g_parm = dt3155_ioc_g_parm,
  795. .vidioc_s_parm = dt3155_ioc_s_parm,
  796. /*
  797. .vidioc_cropcap = dt3155_ioc_cropcap,
  798. .vidioc_g_crop = dt3155_ioc_g_crop,
  799. .vidioc_s_crop = dt3155_ioc_s_crop,
  800. .vidioc_enum_framesizes = dt3155_ioc_enum_framesizes,
  801. .vidioc_enum_frameintervals = dt3155_ioc_enum_frameintervals,
  802. */
  803. };
  804. static int __devinit
  805. dt3155_init_board(struct pci_dev *dev)
  806. {
  807. struct dt3155_priv *pd = pci_get_drvdata(dev);
  808. void *buf_cpu;
  809. dma_addr_t buf_dma;
  810. int i;
  811. u8 tmp;
  812. pci_set_master(dev); /* dt3155 needs it */
  813. /* resetting the adapter */
  814. iowrite32(FLD_CRPT_ODD | FLD_CRPT_EVEN | FLD_DN_ODD | FLD_DN_EVEN,
  815. pd->regs + CSR1);
  816. mmiowb();
  817. msleep(10);
  818. /* initializing adaper registers */
  819. iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
  820. mmiowb();
  821. iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT);
  822. iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT);
  823. iowrite32(0x00000020, pd->regs + FIFO_TRIGER);
  824. iowrite32(0x00000103, pd->regs + XFER_MODE);
  825. iowrite32(0, pd->regs + RETRY_WAIT_CNT);
  826. iowrite32(0, pd->regs + INT_CSR);
  827. iowrite32(1, pd->regs + EVEN_FLD_MASK);
  828. iowrite32(1, pd->regs + ODD_FLD_MASK);
  829. iowrite32(0, pd->regs + MASK_LENGTH);
  830. iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT);
  831. iowrite32(0x01010101, pd->regs + IIC_CLK_DUR);
  832. mmiowb();
  833. /* verifying that we have a DT3155 board (not just a SAA7116 chip) */
  834. read_i2c_reg(pd->regs, DT_ID, &tmp);
  835. if (tmp != DT3155_ID)
  836. return -ENODEV;
  837. /* initialize AD LUT */
  838. write_i2c_reg(pd->regs, AD_ADDR, 0);
  839. for (i = 0; i < 256; i++)
  840. write_i2c_reg(pd->regs, AD_LUT, i);
  841. /* initialize ADC references */
  842. /* FIXME: pos_ref & neg_ref depend on VT_50HZ */
  843. write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
  844. write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
  845. write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF);
  846. write_i2c_reg(pd->regs, AD_CMD, 34);
  847. write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF);
  848. write_i2c_reg(pd->regs, AD_CMD, 0);
  849. /* initialize PM LUT */
  850. write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM);
  851. for (i = 0; i < 256; i++) {
  852. write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
  853. write_i2c_reg(pd->regs, PM_LUT_DATA, i);
  854. }
  855. write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL);
  856. for (i = 0; i < 256; i++) {
  857. write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
  858. write_i2c_reg(pd->regs, PM_LUT_DATA, i);
  859. }
  860. write_i2c_reg(pd->regs, CONFIG, pd->config); /* ACQ_MODE_EVEN */
  861. /* select chanel 1 for input and set sync level */
  862. write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
  863. write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
  864. /* allocate memory, and initialize the DMA machine */
  865. buf_cpu = dma_alloc_coherent(&dev->dev, DT3155_BUF_SIZE, &buf_dma,
  866. GFP_KERNEL);
  867. if (!buf_cpu) {
  868. printk(KERN_ERR "dt3155: dma_alloc_coherent "
  869. "(in dt3155_init_board) failed\n");
  870. return -ENOMEM;
  871. }
  872. iowrite32(buf_dma, pd->regs + EVEN_DMA_START);
  873. iowrite32(buf_dma, pd->regs + ODD_DMA_START);
  874. iowrite32(0, pd->regs + EVEN_DMA_STRIDE);
  875. iowrite32(0, pd->regs + ODD_DMA_STRIDE);
  876. /* Perform a pseudo even field acquire */
  877. iowrite32(FIFO_EN | SRST | CAP_CONT_ODD, pd->regs + CSR1);
  878. write_i2c_reg(pd->regs, CSR2, pd->csr2 | SYNC_SNTL);
  879. write_i2c_reg(pd->regs, CONFIG, pd->config);
  880. write_i2c_reg(pd->regs, EVEN_CSR, CSR_SNGL);
  881. write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | SYNC_SNTL);
  882. msleep(100);
  883. read_i2c_reg(pd->regs, CSR2, &tmp);
  884. write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE);
  885. write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE);
  886. write_i2c_reg(pd->regs, CSR2, pd->csr2);
  887. iowrite32(FIFO_EN | SRST | FLD_DN_EVEN | FLD_DN_ODD, pd->regs + CSR1);
  888. /* deallocate memory */
  889. dma_free_coherent(&dev->dev, DT3155_BUF_SIZE, buf_cpu, buf_dma);
  890. if (tmp & BUSY_EVEN) {
  891. printk(KERN_ERR "dt3155: BUSY_EVEN not cleared\n");
  892. return -EIO;
  893. }
  894. return 0;
  895. }
  896. static struct video_device dt3155_vdev = {
  897. .name = DT3155_NAME,
  898. .fops = &dt3155_fops,
  899. .ioctl_ops = &dt3155_ioctl_ops,
  900. .minor = -1,
  901. .release = video_device_release,
  902. .tvnorms = DT3155_CURRENT_NORM,
  903. .current_norm = DT3155_CURRENT_NORM,
  904. };
  905. /* same as in drivers/base/dma-coherent.c */
  906. struct dma_coherent_mem {
  907. void *virt_base;
  908. u32 device_base;
  909. int size;
  910. int flags;
  911. unsigned long *bitmap;
  912. };
  913. static int __devinit
  914. dt3155_alloc_coherent(struct device *dev, size_t size, int flags)
  915. {
  916. struct dma_coherent_mem *mem;
  917. dma_addr_t dev_base;
  918. int pages = size >> PAGE_SHIFT;
  919. int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
  920. if ((flags & DMA_MEMORY_MAP) == 0)
  921. goto out;
  922. if (!size)
  923. goto out;
  924. if (dev->dma_mem)
  925. goto out;
  926. mem = kzalloc(sizeof(*mem), GFP_KERNEL);
  927. if (!mem)
  928. goto out;
  929. mem->virt_base = dma_alloc_coherent(dev, size, &dev_base,
  930. DT3155_COH_FLAGS);
  931. if (!mem->virt_base)
  932. goto err_alloc_coherent;
  933. mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
  934. if (!mem->bitmap)
  935. goto err_bitmap;
  936. /* coherent_dma_mask is already set to 32 bits */
  937. mem->device_base = dev_base;
  938. mem->size = pages;
  939. mem->flags = flags;
  940. dev->dma_mem = mem;
  941. return DMA_MEMORY_MAP;
  942. err_bitmap:
  943. dma_free_coherent(dev, size, mem->virt_base, dev_base);
  944. err_alloc_coherent:
  945. kfree(mem);
  946. out:
  947. return 0;
  948. }
  949. static void __devexit
  950. dt3155_free_coherent(struct device *dev)
  951. {
  952. struct dma_coherent_mem *mem = dev->dma_mem;
  953. if (!mem)
  954. return;
  955. dev->dma_mem = NULL;
  956. dma_free_coherent(dev, mem->size << PAGE_SHIFT,
  957. mem->virt_base, mem->device_base);
  958. kfree(mem->bitmap);
  959. kfree(mem);
  960. }
  961. static int __devinit
  962. dt3155_probe(struct pci_dev *dev, const struct pci_device_id *id)
  963. {
  964. int err;
  965. struct dt3155_priv *pd;
  966. printk(KERN_INFO "dt3155: probe()\n");
  967. err = dma_set_mask(&dev->dev, DMA_BIT_MASK(32));
  968. if (err) {
  969. printk(KERN_ERR "dt3155: cannot set dma_mask\n");
  970. return -ENODEV;
  971. }
  972. err = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
  973. if (err) {
  974. printk(KERN_ERR "dt3155: cannot set dma_coherent_mask\n");
  975. return -ENODEV;
  976. }
  977. pd = kzalloc(sizeof(*pd), GFP_KERNEL);
  978. if (!pd) {
  979. printk(KERN_ERR "dt3155: cannot allocate dt3155_priv\n");
  980. return -ENOMEM;
  981. }
  982. pd->vdev = video_device_alloc();
  983. if (!pd->vdev) {
  984. printk(KERN_ERR "dt3155: cannot allocate vdev structure\n");
  985. goto err_video_device_alloc;
  986. }
  987. *pd->vdev = dt3155_vdev;
  988. pci_set_drvdata(dev, pd); /* for use in dt3155_remove() */
  989. video_set_drvdata(pd->vdev, pd); /* for use in video_fops */
  990. pd->users = 0;
  991. pd->acq_fp = NULL;
  992. pd->pdev = dev;
  993. INIT_LIST_HEAD(&pd->dmaq);
  994. init_waitqueue_head(&pd->do_dma);
  995. mutex_init(&pd->mux);
  996. pd->csr2 = csr2_init;
  997. pd->config = config_init;
  998. err = pci_enable_device(pd->pdev);
  999. if (err) {
  1000. printk(KERN_ERR "dt3155: pci_dev not enabled\n");
  1001. goto err_enable_dev;
  1002. }
  1003. err = pci_request_region(pd->pdev, 0, pci_name(pd->pdev));
  1004. if (err)
  1005. goto err_req_region;
  1006. pd->regs = pci_iomap(pd->pdev, 0, pci_resource_len(pd->pdev, 0));
  1007. if (!pd->regs) {
  1008. err = -ENOMEM;
  1009. printk(KERN_ERR "dt3155: pci_iomap failed\n");
  1010. goto err_pci_iomap;
  1011. }
  1012. err = dt3155_init_board(pd->pdev);
  1013. if (err) {
  1014. printk(KERN_ERR "dt3155: dt3155_init_board failed\n");
  1015. goto err_init_board;
  1016. }
  1017. err = video_register_device(pd->vdev, VFL_TYPE_GRABBER, -1);
  1018. if (err) {
  1019. printk(KERN_ERR "dt3155: Cannot register video device\n");
  1020. goto err_init_board;
  1021. }
  1022. err = dt3155_alloc_coherent(&dev->dev, DT3155_CHUNK_SIZE,
  1023. DMA_MEMORY_MAP);
  1024. if (err)
  1025. printk(KERN_INFO "dt3155: preallocated 8 buffers\n");
  1026. printk(KERN_INFO "dt3155: /dev/video%i is ready\n", pd->vdev->minor);
  1027. return 0; /* success */
  1028. err_init_board:
  1029. pci_iounmap(pd->pdev, pd->regs);
  1030. err_pci_iomap:
  1031. pci_release_region(pd->pdev, 0);
  1032. err_req_region:
  1033. pci_disable_device(pd->pdev);
  1034. err_enable_dev:
  1035. video_device_release(pd->vdev);
  1036. err_video_device_alloc:
  1037. kfree(pd);
  1038. return err;
  1039. }
  1040. static void __devexit
  1041. dt3155_remove(struct pci_dev *dev)
  1042. {
  1043. struct dt3155_priv *pd = pci_get_drvdata(dev);
  1044. printk(KERN_INFO "dt3155: remove()\n");
  1045. dt3155_free_coherent(&dev->dev);
  1046. video_unregister_device(pd->vdev);
  1047. pci_iounmap(dev, pd->regs);
  1048. pci_release_region(pd->pdev, 0);
  1049. pci_disable_device(pd->pdev);
  1050. /*
  1051. * video_device_release() is invoked automatically
  1052. * see: struct video_device dt3155_vdev
  1053. */
  1054. kfree(pd);
  1055. }
  1056. static DEFINE_PCI_DEVICE_TABLE(pci_ids) = {
  1057. { PCI_DEVICE(DT3155_VENDOR_ID, DT3155_DEVICE_ID) },
  1058. { 0, /* zero marks the end */ },
  1059. };
  1060. MODULE_DEVICE_TABLE(pci, pci_ids);
  1061. static struct pci_driver pci_driver = {
  1062. .name = DT3155_NAME,
  1063. .id_table = pci_ids,
  1064. .probe = dt3155_probe,
  1065. .remove = __devexit_p(dt3155_remove),
  1066. };
  1067. static int __init
  1068. dt3155_init_module(void)
  1069. {
  1070. int err;
  1071. printk(KERN_INFO "dt3155: ==================\n");
  1072. printk(KERN_INFO "dt3155: init()\n");
  1073. err = pci_register_driver(&pci_driver);
  1074. if (err) {
  1075. printk(KERN_ERR "dt3155: cannot register pci_driver\n");
  1076. return err;
  1077. }
  1078. return 0; /* succes */
  1079. }
  1080. static void __exit
  1081. dt3155_exit_module(void)
  1082. {
  1083. pci_unregister_driver(&pci_driver);
  1084. printk(KERN_INFO "dt3155: exit()\n");
  1085. printk(KERN_INFO "dt3155: ==================\n");
  1086. }
  1087. module_init(dt3155_init_module);
  1088. module_exit(dt3155_exit_module);
  1089. MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber");
  1090. MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>");
  1091. MODULE_VERSION(DT3155_VERSION);
  1092. MODULE_LICENSE("GPL");