spi_sh.c 12 KB

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  1. /*
  2. * SH SPI bus driver
  3. *
  4. * Copyright (C) 2011 Renesas Solutions Corp.
  5. *
  6. * Based on pxa2xx_spi.c:
  7. * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; version 2 of the License.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  21. *
  22. */
  23. #include <linux/module.h>
  24. #include <linux/kernel.h>
  25. #include <linux/sched.h>
  26. #include <linux/errno.h>
  27. #include <linux/timer.h>
  28. #include <linux/delay.h>
  29. #include <linux/list.h>
  30. #include <linux/workqueue.h>
  31. #include <linux/interrupt.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/io.h>
  34. #include <linux/spi/spi.h>
  35. #define SPI_SH_TBR 0x00
  36. #define SPI_SH_RBR 0x00
  37. #define SPI_SH_CR1 0x08
  38. #define SPI_SH_CR2 0x10
  39. #define SPI_SH_CR3 0x18
  40. #define SPI_SH_CR4 0x20
  41. #define SPI_SH_CR5 0x28
  42. /* CR1 */
  43. #define SPI_SH_TBE 0x80
  44. #define SPI_SH_TBF 0x40
  45. #define SPI_SH_RBE 0x20
  46. #define SPI_SH_RBF 0x10
  47. #define SPI_SH_PFONRD 0x08
  48. #define SPI_SH_SSDB 0x04
  49. #define SPI_SH_SSD 0x02
  50. #define SPI_SH_SSA 0x01
  51. /* CR2 */
  52. #define SPI_SH_RSTF 0x80
  53. #define SPI_SH_LOOPBK 0x40
  54. #define SPI_SH_CPOL 0x20
  55. #define SPI_SH_CPHA 0x10
  56. #define SPI_SH_L1M0 0x08
  57. /* CR3 */
  58. #define SPI_SH_MAX_BYTE 0xFF
  59. /* CR4 */
  60. #define SPI_SH_TBEI 0x80
  61. #define SPI_SH_TBFI 0x40
  62. #define SPI_SH_RBEI 0x20
  63. #define SPI_SH_RBFI 0x10
  64. #define SPI_SH_WPABRT 0x04
  65. #define SPI_SH_SSS 0x01
  66. /* CR8 */
  67. #define SPI_SH_P1L0 0x80
  68. #define SPI_SH_PP1L0 0x40
  69. #define SPI_SH_MUXI 0x20
  70. #define SPI_SH_MUXIRQ 0x10
  71. #define SPI_SH_FIFO_SIZE 32
  72. #define SPI_SH_SEND_TIMEOUT (3 * HZ)
  73. #define SPI_SH_RECEIVE_TIMEOUT (HZ >> 3)
  74. #undef DEBUG
  75. struct spi_sh_data {
  76. void __iomem *addr;
  77. int irq;
  78. struct spi_master *master;
  79. struct list_head queue;
  80. struct workqueue_struct *workqueue;
  81. struct work_struct ws;
  82. unsigned long cr1;
  83. wait_queue_head_t wait;
  84. spinlock_t lock;
  85. };
  86. static void spi_sh_write(struct spi_sh_data *ss, unsigned long data,
  87. unsigned long offset)
  88. {
  89. writel(data, ss->addr + offset);
  90. }
  91. static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset)
  92. {
  93. return readl(ss->addr + offset);
  94. }
  95. static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val,
  96. unsigned long offset)
  97. {
  98. unsigned long tmp;
  99. tmp = spi_sh_read(ss, offset);
  100. tmp |= val;
  101. spi_sh_write(ss, tmp, offset);
  102. }
  103. static void spi_sh_clear_bit(struct spi_sh_data *ss, unsigned long val,
  104. unsigned long offset)
  105. {
  106. unsigned long tmp;
  107. tmp = spi_sh_read(ss, offset);
  108. tmp &= ~val;
  109. spi_sh_write(ss, tmp, offset);
  110. }
  111. static void clear_fifo(struct spi_sh_data *ss)
  112. {
  113. spi_sh_set_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
  114. spi_sh_clear_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
  115. }
  116. static int spi_sh_wait_receive_buffer(struct spi_sh_data *ss)
  117. {
  118. int timeout = 100000;
  119. while (spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
  120. udelay(10);
  121. if (timeout-- < 0)
  122. return -ETIMEDOUT;
  123. }
  124. return 0;
  125. }
  126. static int spi_sh_wait_write_buffer_empty(struct spi_sh_data *ss)
  127. {
  128. int timeout = 100000;
  129. while (!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBE)) {
  130. udelay(10);
  131. if (timeout-- < 0)
  132. return -ETIMEDOUT;
  133. }
  134. return 0;
  135. }
  136. static int spi_sh_send(struct spi_sh_data *ss, struct spi_message *mesg,
  137. struct spi_transfer *t)
  138. {
  139. int i, retval = 0;
  140. int remain = t->len;
  141. int cur_len;
  142. unsigned char *data;
  143. unsigned long tmp;
  144. long ret;
  145. if (t->len)
  146. spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
  147. data = (unsigned char *)t->tx_buf;
  148. while (remain > 0) {
  149. cur_len = min(SPI_SH_FIFO_SIZE, remain);
  150. for (i = 0; i < cur_len &&
  151. !(spi_sh_read(ss, SPI_SH_CR4) &
  152. SPI_SH_WPABRT) &&
  153. !(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBF);
  154. i++)
  155. spi_sh_write(ss, (unsigned long)data[i], SPI_SH_TBR);
  156. if (spi_sh_read(ss, SPI_SH_CR4) & SPI_SH_WPABRT) {
  157. /* Abort SPI operation */
  158. spi_sh_set_bit(ss, SPI_SH_WPABRT, SPI_SH_CR4);
  159. retval = -EIO;
  160. break;
  161. }
  162. cur_len = i;
  163. remain -= cur_len;
  164. data += cur_len;
  165. if (remain > 0) {
  166. ss->cr1 &= ~SPI_SH_TBE;
  167. spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
  168. ret = wait_event_interruptible_timeout(ss->wait,
  169. ss->cr1 & SPI_SH_TBE,
  170. SPI_SH_SEND_TIMEOUT);
  171. if (ret == 0 && !(ss->cr1 & SPI_SH_TBE)) {
  172. printk(KERN_ERR "%s: timeout\n", __func__);
  173. return -ETIMEDOUT;
  174. }
  175. }
  176. }
  177. if (list_is_last(&t->transfer_list, &mesg->transfers)) {
  178. tmp = spi_sh_read(ss, SPI_SH_CR1);
  179. tmp = tmp & ~(SPI_SH_SSD | SPI_SH_SSDB);
  180. spi_sh_write(ss, tmp, SPI_SH_CR1);
  181. spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
  182. ss->cr1 &= ~SPI_SH_TBE;
  183. spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
  184. ret = wait_event_interruptible_timeout(ss->wait,
  185. ss->cr1 & SPI_SH_TBE,
  186. SPI_SH_SEND_TIMEOUT);
  187. if (ret == 0 && (ss->cr1 & SPI_SH_TBE)) {
  188. printk(KERN_ERR "%s: timeout\n", __func__);
  189. return -ETIMEDOUT;
  190. }
  191. }
  192. return retval;
  193. }
  194. static int spi_sh_receive(struct spi_sh_data *ss, struct spi_message *mesg,
  195. struct spi_transfer *t)
  196. {
  197. int i;
  198. int remain = t->len;
  199. int cur_len;
  200. unsigned char *data;
  201. unsigned long tmp;
  202. long ret;
  203. if (t->len > SPI_SH_MAX_BYTE)
  204. spi_sh_write(ss, SPI_SH_MAX_BYTE, SPI_SH_CR3);
  205. else
  206. spi_sh_write(ss, t->len, SPI_SH_CR3);
  207. tmp = spi_sh_read(ss, SPI_SH_CR1);
  208. tmp = tmp & ~(SPI_SH_SSD | SPI_SH_SSDB);
  209. spi_sh_write(ss, tmp, SPI_SH_CR1);
  210. spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
  211. spi_sh_wait_write_buffer_empty(ss);
  212. data = (unsigned char *)t->rx_buf;
  213. while (remain > 0) {
  214. if (remain >= SPI_SH_FIFO_SIZE) {
  215. ss->cr1 &= ~SPI_SH_RBF;
  216. spi_sh_set_bit(ss, SPI_SH_RBF, SPI_SH_CR4);
  217. ret = wait_event_interruptible_timeout(ss->wait,
  218. ss->cr1 & SPI_SH_RBF,
  219. SPI_SH_RECEIVE_TIMEOUT);
  220. if (ret == 0 &&
  221. spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
  222. printk(KERN_ERR "%s: timeout\n", __func__);
  223. return -ETIMEDOUT;
  224. }
  225. }
  226. cur_len = min(SPI_SH_FIFO_SIZE, remain);
  227. for (i = 0; i < cur_len; i++) {
  228. if (spi_sh_wait_receive_buffer(ss))
  229. break;
  230. data[i] = (unsigned char)spi_sh_read(ss, SPI_SH_RBR);
  231. }
  232. remain -= cur_len;
  233. data += cur_len;
  234. }
  235. /* deassert CS when SPI is receiving. */
  236. if (t->len > SPI_SH_MAX_BYTE) {
  237. clear_fifo(ss);
  238. spi_sh_write(ss, 1, SPI_SH_CR3);
  239. } else {
  240. spi_sh_write(ss, 0, SPI_SH_CR3);
  241. }
  242. return 0;
  243. }
  244. static void spi_sh_work(struct work_struct *work)
  245. {
  246. struct spi_sh_data *ss = container_of(work, struct spi_sh_data, ws);
  247. struct spi_message *mesg;
  248. struct spi_transfer *t;
  249. unsigned long flags;
  250. int ret;
  251. pr_debug("%s: enter\n", __func__);
  252. spin_lock_irqsave(&ss->lock, flags);
  253. while (!list_empty(&ss->queue)) {
  254. mesg = list_entry(ss->queue.next, struct spi_message, queue);
  255. list_del_init(&mesg->queue);
  256. spin_unlock_irqrestore(&ss->lock, flags);
  257. list_for_each_entry(t, &mesg->transfers, transfer_list) {
  258. pr_debug("tx_buf = %p, rx_buf = %p\n",
  259. t->tx_buf, t->rx_buf);
  260. pr_debug("len = %d, delay_usecs = %d\n",
  261. t->len, t->delay_usecs);
  262. if (t->tx_buf) {
  263. ret = spi_sh_send(ss, mesg, t);
  264. if (ret < 0)
  265. goto error;
  266. }
  267. if (t->rx_buf) {
  268. ret = spi_sh_receive(ss, mesg, t);
  269. if (ret < 0)
  270. goto error;
  271. }
  272. mesg->actual_length += t->len;
  273. }
  274. spin_lock_irqsave(&ss->lock, flags);
  275. mesg->status = 0;
  276. mesg->complete(mesg->context);
  277. }
  278. clear_fifo(ss);
  279. spi_sh_set_bit(ss, SPI_SH_SSD, SPI_SH_CR1);
  280. udelay(100);
  281. spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
  282. SPI_SH_CR1);
  283. clear_fifo(ss);
  284. spin_unlock_irqrestore(&ss->lock, flags);
  285. return;
  286. error:
  287. mesg->status = ret;
  288. mesg->complete(mesg->context);
  289. spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
  290. SPI_SH_CR1);
  291. clear_fifo(ss);
  292. }
  293. static int spi_sh_setup(struct spi_device *spi)
  294. {
  295. struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
  296. if (!spi->bits_per_word)
  297. spi->bits_per_word = 8;
  298. pr_debug("%s: enter\n", __func__);
  299. spi_sh_write(ss, 0xfe, SPI_SH_CR1); /* SPI sycle stop */
  300. spi_sh_write(ss, 0x00, SPI_SH_CR1); /* CR1 init */
  301. spi_sh_write(ss, 0x00, SPI_SH_CR3); /* CR3 init */
  302. clear_fifo(ss);
  303. /* 1/8 clock */
  304. spi_sh_write(ss, spi_sh_read(ss, SPI_SH_CR2) | 0x07, SPI_SH_CR2);
  305. udelay(10);
  306. return 0;
  307. }
  308. static int spi_sh_transfer(struct spi_device *spi, struct spi_message *mesg)
  309. {
  310. struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
  311. unsigned long flags;
  312. pr_debug("%s: enter\n", __func__);
  313. pr_debug("\tmode = %02x\n", spi->mode);
  314. spin_lock_irqsave(&ss->lock, flags);
  315. mesg->actual_length = 0;
  316. mesg->status = -EINPROGRESS;
  317. spi_sh_clear_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
  318. list_add_tail(&mesg->queue, &ss->queue);
  319. queue_work(ss->workqueue, &ss->ws);
  320. spin_unlock_irqrestore(&ss->lock, flags);
  321. return 0;
  322. }
  323. static void spi_sh_cleanup(struct spi_device *spi)
  324. {
  325. struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
  326. pr_debug("%s: enter\n", __func__);
  327. spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
  328. SPI_SH_CR1);
  329. }
  330. static irqreturn_t spi_sh_irq(int irq, void *_ss)
  331. {
  332. struct spi_sh_data *ss = (struct spi_sh_data *)_ss;
  333. unsigned long cr1;
  334. cr1 = spi_sh_read(ss, SPI_SH_CR1);
  335. if (cr1 & SPI_SH_TBE)
  336. ss->cr1 |= SPI_SH_TBE;
  337. if (cr1 & SPI_SH_TBF)
  338. ss->cr1 |= SPI_SH_TBF;
  339. if (cr1 & SPI_SH_RBE)
  340. ss->cr1 |= SPI_SH_RBE;
  341. if (cr1 & SPI_SH_RBF)
  342. ss->cr1 |= SPI_SH_RBF;
  343. if (ss->cr1) {
  344. spi_sh_clear_bit(ss, ss->cr1, SPI_SH_CR4);
  345. wake_up(&ss->wait);
  346. }
  347. return IRQ_HANDLED;
  348. }
  349. static int __devexit spi_sh_remove(struct platform_device *pdev)
  350. {
  351. struct spi_sh_data *ss = dev_get_drvdata(&pdev->dev);
  352. spi_unregister_master(ss->master);
  353. destroy_workqueue(ss->workqueue);
  354. free_irq(ss->irq, ss);
  355. iounmap(ss->addr);
  356. return 0;
  357. }
  358. static int __devinit spi_sh_probe(struct platform_device *pdev)
  359. {
  360. struct resource *res;
  361. struct spi_master *master;
  362. struct spi_sh_data *ss;
  363. int ret, irq;
  364. /* get base addr */
  365. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  366. if (unlikely(res == NULL)) {
  367. dev_err(&pdev->dev, "invalid resource\n");
  368. return -EINVAL;
  369. }
  370. irq = platform_get_irq(pdev, 0);
  371. if (irq < 0) {
  372. dev_err(&pdev->dev, "platform_get_irq error\n");
  373. return -ENODEV;
  374. }
  375. master = spi_alloc_master(&pdev->dev, sizeof(struct spi_sh_data));
  376. if (master == NULL) {
  377. dev_err(&pdev->dev, "spi_alloc_master error.\n");
  378. return -ENOMEM;
  379. }
  380. ss = spi_master_get_devdata(master);
  381. dev_set_drvdata(&pdev->dev, ss);
  382. ss->irq = irq;
  383. ss->master = master;
  384. ss->addr = ioremap(res->start, resource_size(res));
  385. if (ss->addr == NULL) {
  386. dev_err(&pdev->dev, "ioremap error.\n");
  387. ret = -ENOMEM;
  388. goto error1;
  389. }
  390. INIT_LIST_HEAD(&ss->queue);
  391. spin_lock_init(&ss->lock);
  392. INIT_WORK(&ss->ws, spi_sh_work);
  393. init_waitqueue_head(&ss->wait);
  394. ss->workqueue = create_singlethread_workqueue(
  395. dev_name(master->dev.parent));
  396. if (ss->workqueue == NULL) {
  397. dev_err(&pdev->dev, "create workqueue error\n");
  398. ret = -EBUSY;
  399. goto error2;
  400. }
  401. ret = request_irq(irq, spi_sh_irq, IRQF_DISABLED, "spi_sh", ss);
  402. if (ret < 0) {
  403. dev_err(&pdev->dev, "request_irq error\n");
  404. goto error3;
  405. }
  406. master->num_chipselect = 2;
  407. master->bus_num = pdev->id;
  408. master->setup = spi_sh_setup;
  409. master->transfer = spi_sh_transfer;
  410. master->cleanup = spi_sh_cleanup;
  411. ret = spi_register_master(master);
  412. if (ret < 0) {
  413. printk(KERN_ERR "spi_register_master error.\n");
  414. goto error4;
  415. }
  416. return 0;
  417. error4:
  418. free_irq(irq, ss);
  419. error3:
  420. destroy_workqueue(ss->workqueue);
  421. error2:
  422. iounmap(ss->addr);
  423. error1:
  424. spi_master_put(master);
  425. return ret;
  426. }
  427. static struct platform_driver spi_sh_driver = {
  428. .probe = spi_sh_probe,
  429. .remove = __devexit_p(spi_sh_remove),
  430. .driver = {
  431. .name = "sh_spi",
  432. .owner = THIS_MODULE,
  433. },
  434. };
  435. static int __init spi_sh_init(void)
  436. {
  437. return platform_driver_register(&spi_sh_driver);
  438. }
  439. module_init(spi_sh_init);
  440. static void __exit spi_sh_exit(void)
  441. {
  442. platform_driver_unregister(&spi_sh_driver);
  443. }
  444. module_exit(spi_sh_exit);
  445. MODULE_DESCRIPTION("SH SPI bus driver");
  446. MODULE_LICENSE("GPL");
  447. MODULE_AUTHOR("Yoshihiro Shimoda");
  448. MODULE_ALIAS("platform:sh_spi");