orion_spi.c 13 KB

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  1. /*
  2. * orion_spi.c -- Marvell Orion SPI controller driver
  3. *
  4. * Author: Shadi Ammouri <shadi@marvell.com>
  5. * Copyright (C) 2007-2008 Marvell Ltd.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/init.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/delay.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/err.h>
  16. #include <linux/io.h>
  17. #include <linux/spi/spi.h>
  18. #include <linux/spi/orion_spi.h>
  19. #include <asm/unaligned.h>
  20. #define DRIVER_NAME "orion_spi"
  21. #define ORION_NUM_CHIPSELECTS 1 /* only one slave is supported*/
  22. #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
  23. #define ORION_SPI_IF_CTRL_REG 0x00
  24. #define ORION_SPI_IF_CONFIG_REG 0x04
  25. #define ORION_SPI_DATA_OUT_REG 0x08
  26. #define ORION_SPI_DATA_IN_REG 0x0c
  27. #define ORION_SPI_INT_CAUSE_REG 0x10
  28. #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
  29. #define ORION_SPI_CLK_PRESCALE_MASK 0x1F
  30. struct orion_spi {
  31. struct work_struct work;
  32. /* Lock access to transfer list. */
  33. spinlock_t lock;
  34. struct list_head msg_queue;
  35. struct spi_master *master;
  36. void __iomem *base;
  37. unsigned int max_speed;
  38. unsigned int min_speed;
  39. struct orion_spi_info *spi_info;
  40. };
  41. static struct workqueue_struct *orion_spi_wq;
  42. static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
  43. {
  44. return orion_spi->base + reg;
  45. }
  46. static inline void
  47. orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
  48. {
  49. void __iomem *reg_addr = spi_reg(orion_spi, reg);
  50. u32 val;
  51. val = readl(reg_addr);
  52. val |= mask;
  53. writel(val, reg_addr);
  54. }
  55. static inline void
  56. orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
  57. {
  58. void __iomem *reg_addr = spi_reg(orion_spi, reg);
  59. u32 val;
  60. val = readl(reg_addr);
  61. val &= ~mask;
  62. writel(val, reg_addr);
  63. }
  64. static int orion_spi_set_transfer_size(struct orion_spi *orion_spi, int size)
  65. {
  66. if (size == 16) {
  67. orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
  68. ORION_SPI_IF_8_16_BIT_MODE);
  69. } else if (size == 8) {
  70. orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
  71. ORION_SPI_IF_8_16_BIT_MODE);
  72. } else {
  73. pr_debug("Bad bits per word value %d (only 8 or 16 are "
  74. "allowed).\n", size);
  75. return -EINVAL;
  76. }
  77. return 0;
  78. }
  79. static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
  80. {
  81. u32 tclk_hz;
  82. u32 rate;
  83. u32 prescale;
  84. u32 reg;
  85. struct orion_spi *orion_spi;
  86. orion_spi = spi_master_get_devdata(spi->master);
  87. tclk_hz = orion_spi->spi_info->tclk;
  88. /*
  89. * the supported rates are: 4,6,8...30
  90. * round up as we look for equal or less speed
  91. */
  92. rate = DIV_ROUND_UP(tclk_hz, speed);
  93. rate = roundup(rate, 2);
  94. /* check if requested speed is too small */
  95. if (rate > 30)
  96. return -EINVAL;
  97. if (rate < 4)
  98. rate = 4;
  99. /* Convert the rate to SPI clock divisor value. */
  100. prescale = 0x10 + rate/2;
  101. reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
  102. reg = ((reg & ~ORION_SPI_CLK_PRESCALE_MASK) | prescale);
  103. writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
  104. return 0;
  105. }
  106. /*
  107. * called only when no transfer is active on the bus
  108. */
  109. static int
  110. orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
  111. {
  112. struct orion_spi *orion_spi;
  113. unsigned int speed = spi->max_speed_hz;
  114. unsigned int bits_per_word = spi->bits_per_word;
  115. int rc;
  116. orion_spi = spi_master_get_devdata(spi->master);
  117. if ((t != NULL) && t->speed_hz)
  118. speed = t->speed_hz;
  119. if ((t != NULL) && t->bits_per_word)
  120. bits_per_word = t->bits_per_word;
  121. rc = orion_spi_baudrate_set(spi, speed);
  122. if (rc)
  123. return rc;
  124. return orion_spi_set_transfer_size(orion_spi, bits_per_word);
  125. }
  126. static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable)
  127. {
  128. if (enable)
  129. orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
  130. else
  131. orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
  132. }
  133. static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
  134. {
  135. int i;
  136. for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
  137. if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
  138. return 1;
  139. else
  140. udelay(1);
  141. }
  142. return -1;
  143. }
  144. static inline int
  145. orion_spi_write_read_8bit(struct spi_device *spi,
  146. const u8 **tx_buf, u8 **rx_buf)
  147. {
  148. void __iomem *tx_reg, *rx_reg, *int_reg;
  149. struct orion_spi *orion_spi;
  150. orion_spi = spi_master_get_devdata(spi->master);
  151. tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
  152. rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
  153. int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
  154. /* clear the interrupt cause register */
  155. writel(0x0, int_reg);
  156. if (tx_buf && *tx_buf)
  157. writel(*(*tx_buf)++, tx_reg);
  158. else
  159. writel(0, tx_reg);
  160. if (orion_spi_wait_till_ready(orion_spi) < 0) {
  161. dev_err(&spi->dev, "TXS timed out\n");
  162. return -1;
  163. }
  164. if (rx_buf && *rx_buf)
  165. *(*rx_buf)++ = readl(rx_reg);
  166. return 1;
  167. }
  168. static inline int
  169. orion_spi_write_read_16bit(struct spi_device *spi,
  170. const u16 **tx_buf, u16 **rx_buf)
  171. {
  172. void __iomem *tx_reg, *rx_reg, *int_reg;
  173. struct orion_spi *orion_spi;
  174. orion_spi = spi_master_get_devdata(spi->master);
  175. tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
  176. rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
  177. int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
  178. /* clear the interrupt cause register */
  179. writel(0x0, int_reg);
  180. if (tx_buf && *tx_buf)
  181. writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
  182. else
  183. writel(0, tx_reg);
  184. if (orion_spi_wait_till_ready(orion_spi) < 0) {
  185. dev_err(&spi->dev, "TXS timed out\n");
  186. return -1;
  187. }
  188. if (rx_buf && *rx_buf)
  189. put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
  190. return 1;
  191. }
  192. static unsigned int
  193. orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
  194. {
  195. struct orion_spi *orion_spi;
  196. unsigned int count;
  197. int word_len;
  198. orion_spi = spi_master_get_devdata(spi->master);
  199. word_len = spi->bits_per_word;
  200. count = xfer->len;
  201. if (word_len == 8) {
  202. const u8 *tx = xfer->tx_buf;
  203. u8 *rx = xfer->rx_buf;
  204. do {
  205. if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
  206. goto out;
  207. count--;
  208. } while (count);
  209. } else if (word_len == 16) {
  210. const u16 *tx = xfer->tx_buf;
  211. u16 *rx = xfer->rx_buf;
  212. do {
  213. if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
  214. goto out;
  215. count -= 2;
  216. } while (count);
  217. }
  218. out:
  219. return xfer->len - count;
  220. }
  221. static void orion_spi_work(struct work_struct *work)
  222. {
  223. struct orion_spi *orion_spi =
  224. container_of(work, struct orion_spi, work);
  225. spin_lock_irq(&orion_spi->lock);
  226. while (!list_empty(&orion_spi->msg_queue)) {
  227. struct spi_message *m;
  228. struct spi_device *spi;
  229. struct spi_transfer *t = NULL;
  230. int par_override = 0;
  231. int status = 0;
  232. int cs_active = 0;
  233. m = container_of(orion_spi->msg_queue.next, struct spi_message,
  234. queue);
  235. list_del_init(&m->queue);
  236. spin_unlock_irq(&orion_spi->lock);
  237. spi = m->spi;
  238. /* Load defaults */
  239. status = orion_spi_setup_transfer(spi, NULL);
  240. if (status < 0)
  241. goto msg_done;
  242. list_for_each_entry(t, &m->transfers, transfer_list) {
  243. if (par_override || t->speed_hz || t->bits_per_word) {
  244. par_override = 1;
  245. status = orion_spi_setup_transfer(spi, t);
  246. if (status < 0)
  247. break;
  248. if (!t->speed_hz && !t->bits_per_word)
  249. par_override = 0;
  250. }
  251. if (!cs_active) {
  252. orion_spi_set_cs(orion_spi, 1);
  253. cs_active = 1;
  254. }
  255. if (t->len)
  256. m->actual_length +=
  257. orion_spi_write_read(spi, t);
  258. if (t->delay_usecs)
  259. udelay(t->delay_usecs);
  260. if (t->cs_change) {
  261. orion_spi_set_cs(orion_spi, 0);
  262. cs_active = 0;
  263. }
  264. }
  265. msg_done:
  266. if (cs_active)
  267. orion_spi_set_cs(orion_spi, 0);
  268. m->status = status;
  269. m->complete(m->context);
  270. spin_lock_irq(&orion_spi->lock);
  271. }
  272. spin_unlock_irq(&orion_spi->lock);
  273. }
  274. static int __init orion_spi_reset(struct orion_spi *orion_spi)
  275. {
  276. /* Verify that the CS is deasserted */
  277. orion_spi_set_cs(orion_spi, 0);
  278. return 0;
  279. }
  280. static int orion_spi_setup(struct spi_device *spi)
  281. {
  282. struct orion_spi *orion_spi;
  283. orion_spi = spi_master_get_devdata(spi->master);
  284. /* Fix ac timing if required. */
  285. if (orion_spi->spi_info->enable_clock_fix)
  286. orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
  287. (1 << 14));
  288. if ((spi->max_speed_hz == 0)
  289. || (spi->max_speed_hz > orion_spi->max_speed))
  290. spi->max_speed_hz = orion_spi->max_speed;
  291. if (spi->max_speed_hz < orion_spi->min_speed) {
  292. dev_err(&spi->dev, "setup: requested speed too low %d Hz\n",
  293. spi->max_speed_hz);
  294. return -EINVAL;
  295. }
  296. /*
  297. * baudrate & width will be set orion_spi_setup_transfer
  298. */
  299. return 0;
  300. }
  301. static int orion_spi_transfer(struct spi_device *spi, struct spi_message *m)
  302. {
  303. struct orion_spi *orion_spi;
  304. struct spi_transfer *t = NULL;
  305. unsigned long flags;
  306. m->actual_length = 0;
  307. m->status = 0;
  308. /* reject invalid messages and transfers */
  309. if (list_empty(&m->transfers) || !m->complete)
  310. return -EINVAL;
  311. orion_spi = spi_master_get_devdata(spi->master);
  312. list_for_each_entry(t, &m->transfers, transfer_list) {
  313. unsigned int bits_per_word = spi->bits_per_word;
  314. if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
  315. dev_err(&spi->dev,
  316. "message rejected : "
  317. "invalid transfer data buffers\n");
  318. goto msg_rejected;
  319. }
  320. if (t->bits_per_word)
  321. bits_per_word = t->bits_per_word;
  322. if ((bits_per_word != 8) && (bits_per_word != 16)) {
  323. dev_err(&spi->dev,
  324. "message rejected : "
  325. "invalid transfer bits_per_word (%d bits)\n",
  326. bits_per_word);
  327. goto msg_rejected;
  328. }
  329. /*make sure buffer length is even when working in 16 bit mode*/
  330. if ((t->bits_per_word == 16) && (t->len & 1)) {
  331. dev_err(&spi->dev,
  332. "message rejected : "
  333. "odd data length (%d) while in 16 bit mode\n",
  334. t->len);
  335. goto msg_rejected;
  336. }
  337. if (t->speed_hz && t->speed_hz < orion_spi->min_speed) {
  338. dev_err(&spi->dev,
  339. "message rejected : "
  340. "device min speed (%d Hz) exceeds "
  341. "required transfer speed (%d Hz)\n",
  342. orion_spi->min_speed, t->speed_hz);
  343. goto msg_rejected;
  344. }
  345. }
  346. spin_lock_irqsave(&orion_spi->lock, flags);
  347. list_add_tail(&m->queue, &orion_spi->msg_queue);
  348. queue_work(orion_spi_wq, &orion_spi->work);
  349. spin_unlock_irqrestore(&orion_spi->lock, flags);
  350. return 0;
  351. msg_rejected:
  352. /* Message rejected and not queued */
  353. m->status = -EINVAL;
  354. if (m->complete)
  355. m->complete(m->context);
  356. return -EINVAL;
  357. }
  358. static int __init orion_spi_probe(struct platform_device *pdev)
  359. {
  360. struct spi_master *master;
  361. struct orion_spi *spi;
  362. struct resource *r;
  363. struct orion_spi_info *spi_info;
  364. int status = 0;
  365. spi_info = pdev->dev.platform_data;
  366. master = spi_alloc_master(&pdev->dev, sizeof *spi);
  367. if (master == NULL) {
  368. dev_dbg(&pdev->dev, "master allocation failed\n");
  369. return -ENOMEM;
  370. }
  371. if (pdev->id != -1)
  372. master->bus_num = pdev->id;
  373. /* we support only mode 0, and no options */
  374. master->mode_bits = 0;
  375. master->setup = orion_spi_setup;
  376. master->transfer = orion_spi_transfer;
  377. master->num_chipselect = ORION_NUM_CHIPSELECTS;
  378. dev_set_drvdata(&pdev->dev, master);
  379. spi = spi_master_get_devdata(master);
  380. spi->master = master;
  381. spi->spi_info = spi_info;
  382. spi->max_speed = DIV_ROUND_UP(spi_info->tclk, 4);
  383. spi->min_speed = DIV_ROUND_UP(spi_info->tclk, 30);
  384. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  385. if (r == NULL) {
  386. status = -ENODEV;
  387. goto out;
  388. }
  389. if (!request_mem_region(r->start, (r->end - r->start) + 1,
  390. dev_name(&pdev->dev))) {
  391. status = -EBUSY;
  392. goto out;
  393. }
  394. spi->base = ioremap(r->start, SZ_1K);
  395. INIT_WORK(&spi->work, orion_spi_work);
  396. spin_lock_init(&spi->lock);
  397. INIT_LIST_HEAD(&spi->msg_queue);
  398. if (orion_spi_reset(spi) < 0)
  399. goto out_rel_mem;
  400. status = spi_register_master(master);
  401. if (status < 0)
  402. goto out_rel_mem;
  403. return status;
  404. out_rel_mem:
  405. release_mem_region(r->start, (r->end - r->start) + 1);
  406. out:
  407. spi_master_put(master);
  408. return status;
  409. }
  410. static int __exit orion_spi_remove(struct platform_device *pdev)
  411. {
  412. struct spi_master *master;
  413. struct orion_spi *spi;
  414. struct resource *r;
  415. master = dev_get_drvdata(&pdev->dev);
  416. spi = spi_master_get_devdata(master);
  417. cancel_work_sync(&spi->work);
  418. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  419. release_mem_region(r->start, (r->end - r->start) + 1);
  420. spi_unregister_master(master);
  421. return 0;
  422. }
  423. MODULE_ALIAS("platform:" DRIVER_NAME);
  424. static struct platform_driver orion_spi_driver = {
  425. .driver = {
  426. .name = DRIVER_NAME,
  427. .owner = THIS_MODULE,
  428. },
  429. .remove = __exit_p(orion_spi_remove),
  430. };
  431. static int __init orion_spi_init(void)
  432. {
  433. orion_spi_wq = create_singlethread_workqueue(
  434. orion_spi_driver.driver.name);
  435. if (orion_spi_wq == NULL)
  436. return -ENOMEM;
  437. return platform_driver_probe(&orion_spi_driver, orion_spi_probe);
  438. }
  439. module_init(orion_spi_init);
  440. static void __exit orion_spi_exit(void)
  441. {
  442. flush_workqueue(orion_spi_wq);
  443. platform_driver_unregister(&orion_spi_driver);
  444. destroy_workqueue(orion_spi_wq);
  445. }
  446. module_exit(orion_spi_exit);
  447. MODULE_DESCRIPTION("Orion SPI driver");
  448. MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
  449. MODULE_LICENSE("GPL");