qlogicpti.c 40 KB

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  1. /* qlogicpti.c: Performance Technologies QlogicISP sbus card driver.
  2. *
  3. * Copyright (C) 1996, 2006, 2008 David S. Miller (davem@davemloft.net)
  4. *
  5. * A lot of this driver was directly stolen from Erik H. Moe's PCI
  6. * Qlogic ISP driver. Mucho kudos to him for this code.
  7. *
  8. * An even bigger kudos to John Grana at Performance Technologies
  9. * for providing me with the hardware to write this driver, you rule
  10. * John you really do.
  11. *
  12. * May, 2, 1997: Added support for QLGC,isp --jj
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/delay.h>
  16. #include <linux/types.h>
  17. #include <linux/string.h>
  18. #include <linux/gfp.h>
  19. #include <linux/blkdev.h>
  20. #include <linux/proc_fs.h>
  21. #include <linux/stat.h>
  22. #include <linux/init.h>
  23. #include <linux/spinlock.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/module.h>
  26. #include <linux/jiffies.h>
  27. #include <linux/dma-mapping.h>
  28. #include <linux/of.h>
  29. #include <linux/of_device.h>
  30. #include <linux/firmware.h>
  31. #include <asm/byteorder.h>
  32. #include "qlogicpti.h"
  33. #include <asm/dma.h>
  34. #include <asm/system.h>
  35. #include <asm/ptrace.h>
  36. #include <asm/pgtable.h>
  37. #include <asm/oplib.h>
  38. #include <asm/io.h>
  39. #include <asm/irq.h>
  40. #include <scsi/scsi.h>
  41. #include <scsi/scsi_cmnd.h>
  42. #include <scsi/scsi_device.h>
  43. #include <scsi/scsi_eh.h>
  44. #include <scsi/scsi_tcq.h>
  45. #include <scsi/scsi_host.h>
  46. #define MAX_TARGETS 16
  47. #define MAX_LUNS 8 /* 32 for 1.31 F/W */
  48. #define DEFAULT_LOOP_COUNT 10000
  49. static struct qlogicpti *qptichain = NULL;
  50. static DEFINE_SPINLOCK(qptichain_lock);
  51. #define PACKB(a, b) (((a)<<4)|(b))
  52. static const u_char mbox_param[] = {
  53. PACKB(1, 1), /* MBOX_NO_OP */
  54. PACKB(5, 5), /* MBOX_LOAD_RAM */
  55. PACKB(2, 0), /* MBOX_EXEC_FIRMWARE */
  56. PACKB(5, 5), /* MBOX_DUMP_RAM */
  57. PACKB(3, 3), /* MBOX_WRITE_RAM_WORD */
  58. PACKB(2, 3), /* MBOX_READ_RAM_WORD */
  59. PACKB(6, 6), /* MBOX_MAILBOX_REG_TEST */
  60. PACKB(2, 3), /* MBOX_VERIFY_CHECKSUM */
  61. PACKB(1, 3), /* MBOX_ABOUT_FIRMWARE */
  62. PACKB(0, 0), /* 0x0009 */
  63. PACKB(0, 0), /* 0x000a */
  64. PACKB(0, 0), /* 0x000b */
  65. PACKB(0, 0), /* 0x000c */
  66. PACKB(0, 0), /* 0x000d */
  67. PACKB(1, 2), /* MBOX_CHECK_FIRMWARE */
  68. PACKB(0, 0), /* 0x000f */
  69. PACKB(5, 5), /* MBOX_INIT_REQ_QUEUE */
  70. PACKB(6, 6), /* MBOX_INIT_RES_QUEUE */
  71. PACKB(4, 4), /* MBOX_EXECUTE_IOCB */
  72. PACKB(2, 2), /* MBOX_WAKE_UP */
  73. PACKB(1, 6), /* MBOX_STOP_FIRMWARE */
  74. PACKB(4, 4), /* MBOX_ABORT */
  75. PACKB(2, 2), /* MBOX_ABORT_DEVICE */
  76. PACKB(3, 3), /* MBOX_ABORT_TARGET */
  77. PACKB(2, 2), /* MBOX_BUS_RESET */
  78. PACKB(2, 3), /* MBOX_STOP_QUEUE */
  79. PACKB(2, 3), /* MBOX_START_QUEUE */
  80. PACKB(2, 3), /* MBOX_SINGLE_STEP_QUEUE */
  81. PACKB(2, 3), /* MBOX_ABORT_QUEUE */
  82. PACKB(2, 4), /* MBOX_GET_DEV_QUEUE_STATUS */
  83. PACKB(0, 0), /* 0x001e */
  84. PACKB(1, 3), /* MBOX_GET_FIRMWARE_STATUS */
  85. PACKB(1, 2), /* MBOX_GET_INIT_SCSI_ID */
  86. PACKB(1, 2), /* MBOX_GET_SELECT_TIMEOUT */
  87. PACKB(1, 3), /* MBOX_GET_RETRY_COUNT */
  88. PACKB(1, 2), /* MBOX_GET_TAG_AGE_LIMIT */
  89. PACKB(1, 2), /* MBOX_GET_CLOCK_RATE */
  90. PACKB(1, 2), /* MBOX_GET_ACT_NEG_STATE */
  91. PACKB(1, 2), /* MBOX_GET_ASYNC_DATA_SETUP_TIME */
  92. PACKB(1, 3), /* MBOX_GET_SBUS_PARAMS */
  93. PACKB(2, 4), /* MBOX_GET_TARGET_PARAMS */
  94. PACKB(2, 4), /* MBOX_GET_DEV_QUEUE_PARAMS */
  95. PACKB(0, 0), /* 0x002a */
  96. PACKB(0, 0), /* 0x002b */
  97. PACKB(0, 0), /* 0x002c */
  98. PACKB(0, 0), /* 0x002d */
  99. PACKB(0, 0), /* 0x002e */
  100. PACKB(0, 0), /* 0x002f */
  101. PACKB(2, 2), /* MBOX_SET_INIT_SCSI_ID */
  102. PACKB(2, 2), /* MBOX_SET_SELECT_TIMEOUT */
  103. PACKB(3, 3), /* MBOX_SET_RETRY_COUNT */
  104. PACKB(2, 2), /* MBOX_SET_TAG_AGE_LIMIT */
  105. PACKB(2, 2), /* MBOX_SET_CLOCK_RATE */
  106. PACKB(2, 2), /* MBOX_SET_ACTIVE_NEG_STATE */
  107. PACKB(2, 2), /* MBOX_SET_ASYNC_DATA_SETUP_TIME */
  108. PACKB(3, 3), /* MBOX_SET_SBUS_CONTROL_PARAMS */
  109. PACKB(4, 4), /* MBOX_SET_TARGET_PARAMS */
  110. PACKB(4, 4), /* MBOX_SET_DEV_QUEUE_PARAMS */
  111. PACKB(0, 0), /* 0x003a */
  112. PACKB(0, 0), /* 0x003b */
  113. PACKB(0, 0), /* 0x003c */
  114. PACKB(0, 0), /* 0x003d */
  115. PACKB(0, 0), /* 0x003e */
  116. PACKB(0, 0), /* 0x003f */
  117. PACKB(0, 0), /* 0x0040 */
  118. PACKB(0, 0), /* 0x0041 */
  119. PACKB(0, 0) /* 0x0042 */
  120. };
  121. #define MAX_MBOX_COMMAND ARRAY_SIZE(mbox_param)
  122. /* queue length's _must_ be power of two: */
  123. #define QUEUE_DEPTH(in, out, ql) ((in - out) & (ql))
  124. #define REQ_QUEUE_DEPTH(in, out) QUEUE_DEPTH(in, out, \
  125. QLOGICPTI_REQ_QUEUE_LEN)
  126. #define RES_QUEUE_DEPTH(in, out) QUEUE_DEPTH(in, out, RES_QUEUE_LEN)
  127. static inline void qlogicpti_enable_irqs(struct qlogicpti *qpti)
  128. {
  129. sbus_writew(SBUS_CTRL_ERIRQ | SBUS_CTRL_GENAB,
  130. qpti->qregs + SBUS_CTRL);
  131. }
  132. static inline void qlogicpti_disable_irqs(struct qlogicpti *qpti)
  133. {
  134. sbus_writew(0, qpti->qregs + SBUS_CTRL);
  135. }
  136. static inline void set_sbus_cfg1(struct qlogicpti *qpti)
  137. {
  138. u16 val;
  139. u8 bursts = qpti->bursts;
  140. #if 0 /* It appears that at least PTI cards do not support
  141. * 64-byte bursts and that setting the B64 bit actually
  142. * is a nop and the chip ends up using the smallest burst
  143. * size. -DaveM
  144. */
  145. if (sbus_can_burst64() && (bursts & DMA_BURST64)) {
  146. val = (SBUS_CFG1_BENAB | SBUS_CFG1_B64);
  147. } else
  148. #endif
  149. if (bursts & DMA_BURST32) {
  150. val = (SBUS_CFG1_BENAB | SBUS_CFG1_B32);
  151. } else if (bursts & DMA_BURST16) {
  152. val = (SBUS_CFG1_BENAB | SBUS_CFG1_B16);
  153. } else if (bursts & DMA_BURST8) {
  154. val = (SBUS_CFG1_BENAB | SBUS_CFG1_B8);
  155. } else {
  156. val = 0; /* No sbus bursts for you... */
  157. }
  158. sbus_writew(val, qpti->qregs + SBUS_CFG1);
  159. }
  160. static int qlogicpti_mbox_command(struct qlogicpti *qpti, u_short param[], int force)
  161. {
  162. int loop_count;
  163. u16 tmp;
  164. if (mbox_param[param[0]] == 0)
  165. return 1;
  166. /* Set SBUS semaphore. */
  167. tmp = sbus_readw(qpti->qregs + SBUS_SEMAPHORE);
  168. tmp |= SBUS_SEMAPHORE_LCK;
  169. sbus_writew(tmp, qpti->qregs + SBUS_SEMAPHORE);
  170. /* Wait for host IRQ bit to clear. */
  171. loop_count = DEFAULT_LOOP_COUNT;
  172. while (--loop_count && (sbus_readw(qpti->qregs + HCCTRL) & HCCTRL_HIRQ)) {
  173. barrier();
  174. cpu_relax();
  175. }
  176. if (!loop_count)
  177. printk(KERN_EMERG "qlogicpti%d: mbox_command loop timeout #1\n",
  178. qpti->qpti_id);
  179. /* Write mailbox command registers. */
  180. switch (mbox_param[param[0]] >> 4) {
  181. case 6: sbus_writew(param[5], qpti->qregs + MBOX5);
  182. case 5: sbus_writew(param[4], qpti->qregs + MBOX4);
  183. case 4: sbus_writew(param[3], qpti->qregs + MBOX3);
  184. case 3: sbus_writew(param[2], qpti->qregs + MBOX2);
  185. case 2: sbus_writew(param[1], qpti->qregs + MBOX1);
  186. case 1: sbus_writew(param[0], qpti->qregs + MBOX0);
  187. }
  188. /* Clear RISC interrupt. */
  189. tmp = sbus_readw(qpti->qregs + HCCTRL);
  190. tmp |= HCCTRL_CRIRQ;
  191. sbus_writew(tmp, qpti->qregs + HCCTRL);
  192. /* Clear SBUS semaphore. */
  193. sbus_writew(0, qpti->qregs + SBUS_SEMAPHORE);
  194. /* Set HOST interrupt. */
  195. tmp = sbus_readw(qpti->qregs + HCCTRL);
  196. tmp |= HCCTRL_SHIRQ;
  197. sbus_writew(tmp, qpti->qregs + HCCTRL);
  198. /* Wait for HOST interrupt clears. */
  199. loop_count = DEFAULT_LOOP_COUNT;
  200. while (--loop_count &&
  201. (sbus_readw(qpti->qregs + HCCTRL) & HCCTRL_CRIRQ))
  202. udelay(20);
  203. if (!loop_count)
  204. printk(KERN_EMERG "qlogicpti%d: mbox_command[%04x] loop timeout #2\n",
  205. qpti->qpti_id, param[0]);
  206. /* Wait for SBUS semaphore to get set. */
  207. loop_count = DEFAULT_LOOP_COUNT;
  208. while (--loop_count &&
  209. !(sbus_readw(qpti->qregs + SBUS_SEMAPHORE) & SBUS_SEMAPHORE_LCK)) {
  210. udelay(20);
  211. /* Workaround for some buggy chips. */
  212. if (sbus_readw(qpti->qregs + MBOX0) & 0x4000)
  213. break;
  214. }
  215. if (!loop_count)
  216. printk(KERN_EMERG "qlogicpti%d: mbox_command[%04x] loop timeout #3\n",
  217. qpti->qpti_id, param[0]);
  218. /* Wait for MBOX busy condition to go away. */
  219. loop_count = DEFAULT_LOOP_COUNT;
  220. while (--loop_count && (sbus_readw(qpti->qregs + MBOX0) == 0x04))
  221. udelay(20);
  222. if (!loop_count)
  223. printk(KERN_EMERG "qlogicpti%d: mbox_command[%04x] loop timeout #4\n",
  224. qpti->qpti_id, param[0]);
  225. /* Read back output parameters. */
  226. switch (mbox_param[param[0]] & 0xf) {
  227. case 6: param[5] = sbus_readw(qpti->qregs + MBOX5);
  228. case 5: param[4] = sbus_readw(qpti->qregs + MBOX4);
  229. case 4: param[3] = sbus_readw(qpti->qregs + MBOX3);
  230. case 3: param[2] = sbus_readw(qpti->qregs + MBOX2);
  231. case 2: param[1] = sbus_readw(qpti->qregs + MBOX1);
  232. case 1: param[0] = sbus_readw(qpti->qregs + MBOX0);
  233. }
  234. /* Clear RISC interrupt. */
  235. tmp = sbus_readw(qpti->qregs + HCCTRL);
  236. tmp |= HCCTRL_CRIRQ;
  237. sbus_writew(tmp, qpti->qregs + HCCTRL);
  238. /* Release SBUS semaphore. */
  239. tmp = sbus_readw(qpti->qregs + SBUS_SEMAPHORE);
  240. tmp &= ~(SBUS_SEMAPHORE_LCK);
  241. sbus_writew(tmp, qpti->qregs + SBUS_SEMAPHORE);
  242. /* We're done. */
  243. return 0;
  244. }
  245. static inline void qlogicpti_set_hostdev_defaults(struct qlogicpti *qpti)
  246. {
  247. int i;
  248. qpti->host_param.initiator_scsi_id = qpti->scsi_id;
  249. qpti->host_param.bus_reset_delay = 3;
  250. qpti->host_param.retry_count = 0;
  251. qpti->host_param.retry_delay = 5;
  252. qpti->host_param.async_data_setup_time = 3;
  253. qpti->host_param.req_ack_active_negation = 1;
  254. qpti->host_param.data_line_active_negation = 1;
  255. qpti->host_param.data_dma_burst_enable = 1;
  256. qpti->host_param.command_dma_burst_enable = 1;
  257. qpti->host_param.tag_aging = 8;
  258. qpti->host_param.selection_timeout = 250;
  259. qpti->host_param.max_queue_depth = 256;
  260. for(i = 0; i < MAX_TARGETS; i++) {
  261. /*
  262. * disconnect, parity, arq, reneg on reset, and, oddly enough
  263. * tags...the midlayer's notion of tagged support has to match
  264. * our device settings, and since we base whether we enable a
  265. * tag on a per-cmnd basis upon what the midlayer sez, we
  266. * actually enable the capability here.
  267. */
  268. qpti->dev_param[i].device_flags = 0xcd;
  269. qpti->dev_param[i].execution_throttle = 16;
  270. if (qpti->ultra) {
  271. qpti->dev_param[i].synchronous_period = 12;
  272. qpti->dev_param[i].synchronous_offset = 8;
  273. } else {
  274. qpti->dev_param[i].synchronous_period = 25;
  275. qpti->dev_param[i].synchronous_offset = 12;
  276. }
  277. qpti->dev_param[i].device_enable = 1;
  278. }
  279. }
  280. static int qlogicpti_reset_hardware(struct Scsi_Host *host)
  281. {
  282. struct qlogicpti *qpti = (struct qlogicpti *) host->hostdata;
  283. u_short param[6];
  284. unsigned short risc_code_addr;
  285. int loop_count, i;
  286. unsigned long flags;
  287. risc_code_addr = 0x1000; /* all load addresses are at 0x1000 */
  288. spin_lock_irqsave(host->host_lock, flags);
  289. sbus_writew(HCCTRL_PAUSE, qpti->qregs + HCCTRL);
  290. /* Only reset the scsi bus if it is not free. */
  291. if (sbus_readw(qpti->qregs + CPU_PCTRL) & CPU_PCTRL_BSY) {
  292. sbus_writew(CPU_ORIDE_RMOD, qpti->qregs + CPU_ORIDE);
  293. sbus_writew(CPU_CMD_BRESET, qpti->qregs + CPU_CMD);
  294. udelay(400);
  295. }
  296. sbus_writew(SBUS_CTRL_RESET, qpti->qregs + SBUS_CTRL);
  297. sbus_writew((DMA_CTRL_CCLEAR | DMA_CTRL_CIRQ), qpti->qregs + CMD_DMA_CTRL);
  298. sbus_writew((DMA_CTRL_CCLEAR | DMA_CTRL_CIRQ), qpti->qregs + DATA_DMA_CTRL);
  299. loop_count = DEFAULT_LOOP_COUNT;
  300. while (--loop_count && ((sbus_readw(qpti->qregs + MBOX0) & 0xff) == 0x04))
  301. udelay(20);
  302. if (!loop_count)
  303. printk(KERN_EMERG "qlogicpti%d: reset_hardware loop timeout\n",
  304. qpti->qpti_id);
  305. sbus_writew(HCCTRL_PAUSE, qpti->qregs + HCCTRL);
  306. set_sbus_cfg1(qpti);
  307. qlogicpti_enable_irqs(qpti);
  308. if (sbus_readw(qpti->qregs + RISC_PSR) & RISC_PSR_ULTRA) {
  309. qpti->ultra = 1;
  310. sbus_writew((RISC_MTREG_P0ULTRA | RISC_MTREG_P1ULTRA),
  311. qpti->qregs + RISC_MTREG);
  312. } else {
  313. qpti->ultra = 0;
  314. sbus_writew((RISC_MTREG_P0DFLT | RISC_MTREG_P1DFLT),
  315. qpti->qregs + RISC_MTREG);
  316. }
  317. /* reset adapter and per-device default values. */
  318. /* do it after finding out whether we're ultra mode capable */
  319. qlogicpti_set_hostdev_defaults(qpti);
  320. /* Release the RISC processor. */
  321. sbus_writew(HCCTRL_REL, qpti->qregs + HCCTRL);
  322. /* Get RISC to start executing the firmware code. */
  323. param[0] = MBOX_EXEC_FIRMWARE;
  324. param[1] = risc_code_addr;
  325. if (qlogicpti_mbox_command(qpti, param, 1)) {
  326. printk(KERN_EMERG "qlogicpti%d: Cannot execute ISP firmware.\n",
  327. qpti->qpti_id);
  328. spin_unlock_irqrestore(host->host_lock, flags);
  329. return 1;
  330. }
  331. /* Set initiator scsi ID. */
  332. param[0] = MBOX_SET_INIT_SCSI_ID;
  333. param[1] = qpti->host_param.initiator_scsi_id;
  334. if (qlogicpti_mbox_command(qpti, param, 1) ||
  335. (param[0] != MBOX_COMMAND_COMPLETE)) {
  336. printk(KERN_EMERG "qlogicpti%d: Cannot set initiator SCSI ID.\n",
  337. qpti->qpti_id);
  338. spin_unlock_irqrestore(host->host_lock, flags);
  339. return 1;
  340. }
  341. /* Initialize state of the queues, both hw and sw. */
  342. qpti->req_in_ptr = qpti->res_out_ptr = 0;
  343. param[0] = MBOX_INIT_RES_QUEUE;
  344. param[1] = RES_QUEUE_LEN + 1;
  345. param[2] = (u_short) (qpti->res_dvma >> 16);
  346. param[3] = (u_short) (qpti->res_dvma & 0xffff);
  347. param[4] = param[5] = 0;
  348. if (qlogicpti_mbox_command(qpti, param, 1)) {
  349. printk(KERN_EMERG "qlogicpti%d: Cannot init response queue.\n",
  350. qpti->qpti_id);
  351. spin_unlock_irqrestore(host->host_lock, flags);
  352. return 1;
  353. }
  354. param[0] = MBOX_INIT_REQ_QUEUE;
  355. param[1] = QLOGICPTI_REQ_QUEUE_LEN + 1;
  356. param[2] = (u_short) (qpti->req_dvma >> 16);
  357. param[3] = (u_short) (qpti->req_dvma & 0xffff);
  358. param[4] = param[5] = 0;
  359. if (qlogicpti_mbox_command(qpti, param, 1)) {
  360. printk(KERN_EMERG "qlogicpti%d: Cannot init request queue.\n",
  361. qpti->qpti_id);
  362. spin_unlock_irqrestore(host->host_lock, flags);
  363. return 1;
  364. }
  365. param[0] = MBOX_SET_RETRY_COUNT;
  366. param[1] = qpti->host_param.retry_count;
  367. param[2] = qpti->host_param.retry_delay;
  368. qlogicpti_mbox_command(qpti, param, 0);
  369. param[0] = MBOX_SET_TAG_AGE_LIMIT;
  370. param[1] = qpti->host_param.tag_aging;
  371. qlogicpti_mbox_command(qpti, param, 0);
  372. for (i = 0; i < MAX_TARGETS; i++) {
  373. param[0] = MBOX_GET_DEV_QUEUE_PARAMS;
  374. param[1] = (i << 8);
  375. qlogicpti_mbox_command(qpti, param, 0);
  376. }
  377. param[0] = MBOX_GET_FIRMWARE_STATUS;
  378. qlogicpti_mbox_command(qpti, param, 0);
  379. param[0] = MBOX_SET_SELECT_TIMEOUT;
  380. param[1] = qpti->host_param.selection_timeout;
  381. qlogicpti_mbox_command(qpti, param, 0);
  382. for (i = 0; i < MAX_TARGETS; i++) {
  383. param[0] = MBOX_SET_TARGET_PARAMS;
  384. param[1] = (i << 8);
  385. param[2] = (qpti->dev_param[i].device_flags << 8);
  386. /*
  387. * Since we're now loading 1.31 f/w, force narrow/async.
  388. */
  389. param[2] |= 0xc0;
  390. param[3] = 0; /* no offset, we do not have sync mode yet */
  391. qlogicpti_mbox_command(qpti, param, 0);
  392. }
  393. /*
  394. * Always (sigh) do an initial bus reset (kicks f/w).
  395. */
  396. param[0] = MBOX_BUS_RESET;
  397. param[1] = qpti->host_param.bus_reset_delay;
  398. qlogicpti_mbox_command(qpti, param, 0);
  399. qpti->send_marker = 1;
  400. spin_unlock_irqrestore(host->host_lock, flags);
  401. return 0;
  402. }
  403. #define PTI_RESET_LIMIT 400
  404. static int __devinit qlogicpti_load_firmware(struct qlogicpti *qpti)
  405. {
  406. const struct firmware *fw;
  407. const char fwname[] = "qlogic/isp1000.bin";
  408. const __le16 *fw_data;
  409. struct Scsi_Host *host = qpti->qhost;
  410. unsigned short csum = 0;
  411. unsigned short param[6];
  412. unsigned short risc_code_addr, risc_code_length;
  413. int err;
  414. unsigned long flags;
  415. int i, timeout;
  416. err = request_firmware(&fw, fwname, &qpti->op->dev);
  417. if (err) {
  418. printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
  419. fwname, err);
  420. return err;
  421. }
  422. if (fw->size % 2) {
  423. printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
  424. fw->size, fwname);
  425. err = -EINVAL;
  426. goto outfirm;
  427. }
  428. fw_data = (const __le16 *)&fw->data[0];
  429. risc_code_addr = 0x1000; /* all f/w modules load at 0x1000 */
  430. risc_code_length = fw->size / 2;
  431. spin_lock_irqsave(host->host_lock, flags);
  432. /* Verify the checksum twice, one before loading it, and once
  433. * afterwards via the mailbox commands.
  434. */
  435. for (i = 0; i < risc_code_length; i++)
  436. csum += __le16_to_cpu(fw_data[i]);
  437. if (csum) {
  438. printk(KERN_EMERG "qlogicpti%d: Aieee, firmware checksum failed!",
  439. qpti->qpti_id);
  440. err = 1;
  441. goto out;
  442. }
  443. sbus_writew(SBUS_CTRL_RESET, qpti->qregs + SBUS_CTRL);
  444. sbus_writew((DMA_CTRL_CCLEAR | DMA_CTRL_CIRQ), qpti->qregs + CMD_DMA_CTRL);
  445. sbus_writew((DMA_CTRL_CCLEAR | DMA_CTRL_CIRQ), qpti->qregs + DATA_DMA_CTRL);
  446. timeout = PTI_RESET_LIMIT;
  447. while (--timeout && (sbus_readw(qpti->qregs + SBUS_CTRL) & SBUS_CTRL_RESET))
  448. udelay(20);
  449. if (!timeout) {
  450. printk(KERN_EMERG "qlogicpti%d: Cannot reset the ISP.", qpti->qpti_id);
  451. err = 1;
  452. goto out;
  453. }
  454. sbus_writew(HCCTRL_RESET, qpti->qregs + HCCTRL);
  455. mdelay(1);
  456. sbus_writew((SBUS_CTRL_GENAB | SBUS_CTRL_ERIRQ), qpti->qregs + SBUS_CTRL);
  457. set_sbus_cfg1(qpti);
  458. sbus_writew(0, qpti->qregs + SBUS_SEMAPHORE);
  459. if (sbus_readw(qpti->qregs + RISC_PSR) & RISC_PSR_ULTRA) {
  460. qpti->ultra = 1;
  461. sbus_writew((RISC_MTREG_P0ULTRA | RISC_MTREG_P1ULTRA),
  462. qpti->qregs + RISC_MTREG);
  463. } else {
  464. qpti->ultra = 0;
  465. sbus_writew((RISC_MTREG_P0DFLT | RISC_MTREG_P1DFLT),
  466. qpti->qregs + RISC_MTREG);
  467. }
  468. sbus_writew(HCCTRL_REL, qpti->qregs + HCCTRL);
  469. /* Pin lines are only stable while RISC is paused. */
  470. sbus_writew(HCCTRL_PAUSE, qpti->qregs + HCCTRL);
  471. if (sbus_readw(qpti->qregs + CPU_PDIFF) & CPU_PDIFF_MODE)
  472. qpti->differential = 1;
  473. else
  474. qpti->differential = 0;
  475. sbus_writew(HCCTRL_REL, qpti->qregs + HCCTRL);
  476. /* This shouldn't be necessary- we've reset things so we should be
  477. running from the ROM now.. */
  478. param[0] = MBOX_STOP_FIRMWARE;
  479. param[1] = param[2] = param[3] = param[4] = param[5] = 0;
  480. if (qlogicpti_mbox_command(qpti, param, 1)) {
  481. printk(KERN_EMERG "qlogicpti%d: Cannot stop firmware for reload.\n",
  482. qpti->qpti_id);
  483. err = 1;
  484. goto out;
  485. }
  486. /* Load it up.. */
  487. for (i = 0; i < risc_code_length; i++) {
  488. param[0] = MBOX_WRITE_RAM_WORD;
  489. param[1] = risc_code_addr + i;
  490. param[2] = __le16_to_cpu(fw_data[i]);
  491. if (qlogicpti_mbox_command(qpti, param, 1) ||
  492. param[0] != MBOX_COMMAND_COMPLETE) {
  493. printk("qlogicpti%d: Firmware dload failed, I'm bolixed!\n",
  494. qpti->qpti_id);
  495. err = 1;
  496. goto out;
  497. }
  498. }
  499. /* Reset the ISP again. */
  500. sbus_writew(HCCTRL_RESET, qpti->qregs + HCCTRL);
  501. mdelay(1);
  502. qlogicpti_enable_irqs(qpti);
  503. sbus_writew(0, qpti->qregs + SBUS_SEMAPHORE);
  504. sbus_writew(HCCTRL_REL, qpti->qregs + HCCTRL);
  505. /* Ask ISP to verify the checksum of the new code. */
  506. param[0] = MBOX_VERIFY_CHECKSUM;
  507. param[1] = risc_code_addr;
  508. if (qlogicpti_mbox_command(qpti, param, 1) ||
  509. (param[0] != MBOX_COMMAND_COMPLETE)) {
  510. printk(KERN_EMERG "qlogicpti%d: New firmware csum failure!\n",
  511. qpti->qpti_id);
  512. err = 1;
  513. goto out;
  514. }
  515. /* Start using newly downloaded firmware. */
  516. param[0] = MBOX_EXEC_FIRMWARE;
  517. param[1] = risc_code_addr;
  518. qlogicpti_mbox_command(qpti, param, 1);
  519. param[0] = MBOX_ABOUT_FIRMWARE;
  520. if (qlogicpti_mbox_command(qpti, param, 1) ||
  521. (param[0] != MBOX_COMMAND_COMPLETE)) {
  522. printk(KERN_EMERG "qlogicpti%d: AboutFirmware cmd fails.\n",
  523. qpti->qpti_id);
  524. err = 1;
  525. goto out;
  526. }
  527. /* Snag the major and minor revisions from the result. */
  528. qpti->fware_majrev = param[1];
  529. qpti->fware_minrev = param[2];
  530. qpti->fware_micrev = param[3];
  531. /* Set the clock rate */
  532. param[0] = MBOX_SET_CLOCK_RATE;
  533. param[1] = qpti->clock;
  534. if (qlogicpti_mbox_command(qpti, param, 1) ||
  535. (param[0] != MBOX_COMMAND_COMPLETE)) {
  536. printk(KERN_EMERG "qlogicpti%d: could not set clock rate.\n",
  537. qpti->qpti_id);
  538. err = 1;
  539. goto out;
  540. }
  541. if (qpti->is_pti != 0) {
  542. /* Load scsi initiator ID and interrupt level into sbus static ram. */
  543. param[0] = MBOX_WRITE_RAM_WORD;
  544. param[1] = 0xff80;
  545. param[2] = (unsigned short) qpti->scsi_id;
  546. qlogicpti_mbox_command(qpti, param, 1);
  547. param[0] = MBOX_WRITE_RAM_WORD;
  548. param[1] = 0xff00;
  549. param[2] = (unsigned short) 3;
  550. qlogicpti_mbox_command(qpti, param, 1);
  551. }
  552. out:
  553. spin_unlock_irqrestore(host->host_lock, flags);
  554. outfirm:
  555. release_firmware(fw);
  556. return err;
  557. }
  558. static int qlogicpti_verify_tmon(struct qlogicpti *qpti)
  559. {
  560. int curstat = sbus_readb(qpti->sreg);
  561. curstat &= 0xf0;
  562. if (!(curstat & SREG_FUSE) && (qpti->swsreg & SREG_FUSE))
  563. printk("qlogicpti%d: Fuse returned to normal state.\n", qpti->qpti_id);
  564. if (!(curstat & SREG_TPOWER) && (qpti->swsreg & SREG_TPOWER))
  565. printk("qlogicpti%d: termpwr back to normal state.\n", qpti->qpti_id);
  566. if (curstat != qpti->swsreg) {
  567. int error = 0;
  568. if (curstat & SREG_FUSE) {
  569. error++;
  570. printk("qlogicpti%d: Fuse is open!\n", qpti->qpti_id);
  571. }
  572. if (curstat & SREG_TPOWER) {
  573. error++;
  574. printk("qlogicpti%d: termpwr failure\n", qpti->qpti_id);
  575. }
  576. if (qpti->differential &&
  577. (curstat & SREG_DSENSE) != SREG_DSENSE) {
  578. error++;
  579. printk("qlogicpti%d: You have a single ended device on a "
  580. "differential bus! Please fix!\n", qpti->qpti_id);
  581. }
  582. qpti->swsreg = curstat;
  583. return error;
  584. }
  585. return 0;
  586. }
  587. static irqreturn_t qpti_intr(int irq, void *dev_id);
  588. static void __devinit qpti_chain_add(struct qlogicpti *qpti)
  589. {
  590. spin_lock_irq(&qptichain_lock);
  591. if (qptichain != NULL) {
  592. struct qlogicpti *qlink = qptichain;
  593. while(qlink->next)
  594. qlink = qlink->next;
  595. qlink->next = qpti;
  596. } else {
  597. qptichain = qpti;
  598. }
  599. qpti->next = NULL;
  600. spin_unlock_irq(&qptichain_lock);
  601. }
  602. static void __devexit qpti_chain_del(struct qlogicpti *qpti)
  603. {
  604. spin_lock_irq(&qptichain_lock);
  605. if (qptichain == qpti) {
  606. qptichain = qpti->next;
  607. } else {
  608. struct qlogicpti *qlink = qptichain;
  609. while(qlink->next != qpti)
  610. qlink = qlink->next;
  611. qlink->next = qpti->next;
  612. }
  613. qpti->next = NULL;
  614. spin_unlock_irq(&qptichain_lock);
  615. }
  616. static int __devinit qpti_map_regs(struct qlogicpti *qpti)
  617. {
  618. struct platform_device *op = qpti->op;
  619. qpti->qregs = of_ioremap(&op->resource[0], 0,
  620. resource_size(&op->resource[0]),
  621. "PTI Qlogic/ISP");
  622. if (!qpti->qregs) {
  623. printk("PTI: Qlogic/ISP registers are unmappable\n");
  624. return -1;
  625. }
  626. if (qpti->is_pti) {
  627. qpti->sreg = of_ioremap(&op->resource[0], (16 * 4096),
  628. sizeof(unsigned char),
  629. "PTI Qlogic/ISP statreg");
  630. if (!qpti->sreg) {
  631. printk("PTI: Qlogic/ISP status register is unmappable\n");
  632. return -1;
  633. }
  634. }
  635. return 0;
  636. }
  637. static int __devinit qpti_register_irq(struct qlogicpti *qpti)
  638. {
  639. struct platform_device *op = qpti->op;
  640. qpti->qhost->irq = qpti->irq = op->archdata.irqs[0];
  641. /* We used to try various overly-clever things to
  642. * reduce the interrupt processing overhead on
  643. * sun4c/sun4m when multiple PTI's shared the
  644. * same IRQ. It was too complex and messy to
  645. * sanely maintain.
  646. */
  647. if (request_irq(qpti->irq, qpti_intr,
  648. IRQF_SHARED, "QlogicPTI", qpti))
  649. goto fail;
  650. printk("qlogicpti%d: IRQ %d ", qpti->qpti_id, qpti->irq);
  651. return 0;
  652. fail:
  653. printk("qlogicpti%d: Cannot acquire irq line\n", qpti->qpti_id);
  654. return -1;
  655. }
  656. static void __devinit qpti_get_scsi_id(struct qlogicpti *qpti)
  657. {
  658. struct platform_device *op = qpti->op;
  659. struct device_node *dp;
  660. dp = op->dev.of_node;
  661. qpti->scsi_id = of_getintprop_default(dp, "initiator-id", -1);
  662. if (qpti->scsi_id == -1)
  663. qpti->scsi_id = of_getintprop_default(dp, "scsi-initiator-id",
  664. -1);
  665. if (qpti->scsi_id == -1)
  666. qpti->scsi_id =
  667. of_getintprop_default(dp->parent,
  668. "scsi-initiator-id", 7);
  669. qpti->qhost->this_id = qpti->scsi_id;
  670. qpti->qhost->max_sectors = 64;
  671. printk("SCSI ID %d ", qpti->scsi_id);
  672. }
  673. static void qpti_get_bursts(struct qlogicpti *qpti)
  674. {
  675. struct platform_device *op = qpti->op;
  676. u8 bursts, bmask;
  677. bursts = of_getintprop_default(op->dev.of_node, "burst-sizes", 0xff);
  678. bmask = of_getintprop_default(op->dev.of_node->parent, "burst-sizes", 0xff);
  679. if (bmask != 0xff)
  680. bursts &= bmask;
  681. if (bursts == 0xff ||
  682. (bursts & DMA_BURST16) == 0 ||
  683. (bursts & DMA_BURST32) == 0)
  684. bursts = (DMA_BURST32 - 1);
  685. qpti->bursts = bursts;
  686. }
  687. static void qpti_get_clock(struct qlogicpti *qpti)
  688. {
  689. unsigned int cfreq;
  690. /* Check for what the clock input to this card is.
  691. * Default to 40Mhz.
  692. */
  693. cfreq = prom_getintdefault(qpti->prom_node,"clock-frequency",40000000);
  694. qpti->clock = (cfreq + 500000)/1000000;
  695. if (qpti->clock == 0) /* bullshit */
  696. qpti->clock = 40;
  697. }
  698. /* The request and response queues must each be aligned
  699. * on a page boundary.
  700. */
  701. static int __devinit qpti_map_queues(struct qlogicpti *qpti)
  702. {
  703. struct platform_device *op = qpti->op;
  704. #define QSIZE(entries) (((entries) + 1) * QUEUE_ENTRY_LEN)
  705. qpti->res_cpu = dma_alloc_coherent(&op->dev,
  706. QSIZE(RES_QUEUE_LEN),
  707. &qpti->res_dvma, GFP_ATOMIC);
  708. if (qpti->res_cpu == NULL ||
  709. qpti->res_dvma == 0) {
  710. printk("QPTI: Cannot map response queue.\n");
  711. return -1;
  712. }
  713. qpti->req_cpu = dma_alloc_coherent(&op->dev,
  714. QSIZE(QLOGICPTI_REQ_QUEUE_LEN),
  715. &qpti->req_dvma, GFP_ATOMIC);
  716. if (qpti->req_cpu == NULL ||
  717. qpti->req_dvma == 0) {
  718. dma_free_coherent(&op->dev, QSIZE(RES_QUEUE_LEN),
  719. qpti->res_cpu, qpti->res_dvma);
  720. printk("QPTI: Cannot map request queue.\n");
  721. return -1;
  722. }
  723. memset(qpti->res_cpu, 0, QSIZE(RES_QUEUE_LEN));
  724. memset(qpti->req_cpu, 0, QSIZE(QLOGICPTI_REQ_QUEUE_LEN));
  725. return 0;
  726. }
  727. const char *qlogicpti_info(struct Scsi_Host *host)
  728. {
  729. static char buf[80];
  730. struct qlogicpti *qpti = (struct qlogicpti *) host->hostdata;
  731. sprintf(buf, "PTI Qlogic,ISP SBUS SCSI irq %d regs at %p",
  732. qpti->qhost->irq, qpti->qregs);
  733. return buf;
  734. }
  735. /* I am a certified frobtronicist. */
  736. static inline void marker_frob(struct Command_Entry *cmd)
  737. {
  738. struct Marker_Entry *marker = (struct Marker_Entry *) cmd;
  739. memset(marker, 0, sizeof(struct Marker_Entry));
  740. marker->hdr.entry_cnt = 1;
  741. marker->hdr.entry_type = ENTRY_MARKER;
  742. marker->modifier = SYNC_ALL;
  743. marker->rsvd = 0;
  744. }
  745. static inline void cmd_frob(struct Command_Entry *cmd, struct scsi_cmnd *Cmnd,
  746. struct qlogicpti *qpti)
  747. {
  748. memset(cmd, 0, sizeof(struct Command_Entry));
  749. cmd->hdr.entry_cnt = 1;
  750. cmd->hdr.entry_type = ENTRY_COMMAND;
  751. cmd->target_id = Cmnd->device->id;
  752. cmd->target_lun = Cmnd->device->lun;
  753. cmd->cdb_length = Cmnd->cmd_len;
  754. cmd->control_flags = 0;
  755. if (Cmnd->device->tagged_supported) {
  756. if (qpti->cmd_count[Cmnd->device->id] == 0)
  757. qpti->tag_ages[Cmnd->device->id] = jiffies;
  758. if (time_after(jiffies, qpti->tag_ages[Cmnd->device->id] + (5*HZ))) {
  759. cmd->control_flags = CFLAG_ORDERED_TAG;
  760. qpti->tag_ages[Cmnd->device->id] = jiffies;
  761. } else
  762. cmd->control_flags = CFLAG_SIMPLE_TAG;
  763. }
  764. if ((Cmnd->cmnd[0] == WRITE_6) ||
  765. (Cmnd->cmnd[0] == WRITE_10) ||
  766. (Cmnd->cmnd[0] == WRITE_12))
  767. cmd->control_flags |= CFLAG_WRITE;
  768. else
  769. cmd->control_flags |= CFLAG_READ;
  770. cmd->time_out = 30;
  771. memcpy(cmd->cdb, Cmnd->cmnd, Cmnd->cmd_len);
  772. }
  773. /* Do it to it baby. */
  774. static inline int load_cmd(struct scsi_cmnd *Cmnd, struct Command_Entry *cmd,
  775. struct qlogicpti *qpti, u_int in_ptr, u_int out_ptr)
  776. {
  777. struct dataseg *ds;
  778. struct scatterlist *sg, *s;
  779. int i, n;
  780. if (scsi_bufflen(Cmnd)) {
  781. int sg_count;
  782. sg = scsi_sglist(Cmnd);
  783. sg_count = dma_map_sg(&qpti->op->dev, sg,
  784. scsi_sg_count(Cmnd),
  785. Cmnd->sc_data_direction);
  786. ds = cmd->dataseg;
  787. cmd->segment_cnt = sg_count;
  788. /* Fill in first four sg entries: */
  789. n = sg_count;
  790. if (n > 4)
  791. n = 4;
  792. for_each_sg(sg, s, n, i) {
  793. ds[i].d_base = sg_dma_address(s);
  794. ds[i].d_count = sg_dma_len(s);
  795. }
  796. sg_count -= 4;
  797. sg = s;
  798. while (sg_count > 0) {
  799. struct Continuation_Entry *cont;
  800. ++cmd->hdr.entry_cnt;
  801. cont = (struct Continuation_Entry *) &qpti->req_cpu[in_ptr];
  802. in_ptr = NEXT_REQ_PTR(in_ptr);
  803. if (in_ptr == out_ptr)
  804. return -1;
  805. cont->hdr.entry_type = ENTRY_CONTINUATION;
  806. cont->hdr.entry_cnt = 0;
  807. cont->hdr.sys_def_1 = 0;
  808. cont->hdr.flags = 0;
  809. cont->reserved = 0;
  810. ds = cont->dataseg;
  811. n = sg_count;
  812. if (n > 7)
  813. n = 7;
  814. for_each_sg(sg, s, n, i) {
  815. ds[i].d_base = sg_dma_address(s);
  816. ds[i].d_count = sg_dma_len(s);
  817. }
  818. sg_count -= n;
  819. sg = s;
  820. }
  821. } else {
  822. cmd->dataseg[0].d_base = 0;
  823. cmd->dataseg[0].d_count = 0;
  824. cmd->segment_cnt = 1; /* Shouldn't this be 0? */
  825. }
  826. /* Committed, record Scsi_Cmd so we can find it later. */
  827. cmd->handle = in_ptr;
  828. qpti->cmd_slots[in_ptr] = Cmnd;
  829. qpti->cmd_count[Cmnd->device->id]++;
  830. sbus_writew(in_ptr, qpti->qregs + MBOX4);
  831. qpti->req_in_ptr = in_ptr;
  832. return in_ptr;
  833. }
  834. static inline void update_can_queue(struct Scsi_Host *host, u_int in_ptr, u_int out_ptr)
  835. {
  836. /* Temporary workaround until bug is found and fixed (one bug has been found
  837. already, but fixing it makes things even worse) -jj */
  838. int num_free = QLOGICPTI_REQ_QUEUE_LEN - REQ_QUEUE_DEPTH(in_ptr, out_ptr) - 64;
  839. host->can_queue = host->host_busy + num_free;
  840. host->sg_tablesize = QLOGICPTI_MAX_SG(num_free);
  841. }
  842. static int qlogicpti_slave_configure(struct scsi_device *sdev)
  843. {
  844. struct qlogicpti *qpti = shost_priv(sdev->host);
  845. int tgt = sdev->id;
  846. u_short param[6];
  847. /* tags handled in midlayer */
  848. /* enable sync mode? */
  849. if (sdev->sdtr) {
  850. qpti->dev_param[tgt].device_flags |= 0x10;
  851. } else {
  852. qpti->dev_param[tgt].synchronous_offset = 0;
  853. qpti->dev_param[tgt].synchronous_period = 0;
  854. }
  855. /* are we wide capable? */
  856. if (sdev->wdtr)
  857. qpti->dev_param[tgt].device_flags |= 0x20;
  858. param[0] = MBOX_SET_TARGET_PARAMS;
  859. param[1] = (tgt << 8);
  860. param[2] = (qpti->dev_param[tgt].device_flags << 8);
  861. if (qpti->dev_param[tgt].device_flags & 0x10) {
  862. param[3] = (qpti->dev_param[tgt].synchronous_offset << 8) |
  863. qpti->dev_param[tgt].synchronous_period;
  864. } else {
  865. param[3] = 0;
  866. }
  867. qlogicpti_mbox_command(qpti, param, 0);
  868. return 0;
  869. }
  870. /*
  871. * The middle SCSI layer ensures that queuecommand never gets invoked
  872. * concurrently with itself or the interrupt handler (though the
  873. * interrupt handler may call this routine as part of
  874. * request-completion handling).
  875. *
  876. * "This code must fly." -davem
  877. */
  878. static int qlogicpti_queuecommand_lck(struct scsi_cmnd *Cmnd, void (*done)(struct scsi_cmnd *))
  879. {
  880. struct Scsi_Host *host = Cmnd->device->host;
  881. struct qlogicpti *qpti = (struct qlogicpti *) host->hostdata;
  882. struct Command_Entry *cmd;
  883. u_int out_ptr;
  884. int in_ptr;
  885. Cmnd->scsi_done = done;
  886. in_ptr = qpti->req_in_ptr;
  887. cmd = (struct Command_Entry *) &qpti->req_cpu[in_ptr];
  888. out_ptr = sbus_readw(qpti->qregs + MBOX4);
  889. in_ptr = NEXT_REQ_PTR(in_ptr);
  890. if (in_ptr == out_ptr)
  891. goto toss_command;
  892. if (qpti->send_marker) {
  893. marker_frob(cmd);
  894. qpti->send_marker = 0;
  895. if (NEXT_REQ_PTR(in_ptr) == out_ptr) {
  896. sbus_writew(in_ptr, qpti->qregs + MBOX4);
  897. qpti->req_in_ptr = in_ptr;
  898. goto toss_command;
  899. }
  900. cmd = (struct Command_Entry *) &qpti->req_cpu[in_ptr];
  901. in_ptr = NEXT_REQ_PTR(in_ptr);
  902. }
  903. cmd_frob(cmd, Cmnd, qpti);
  904. if ((in_ptr = load_cmd(Cmnd, cmd, qpti, in_ptr, out_ptr)) == -1)
  905. goto toss_command;
  906. update_can_queue(host, in_ptr, out_ptr);
  907. return 0;
  908. toss_command:
  909. printk(KERN_EMERG "qlogicpti%d: request queue overflow\n",
  910. qpti->qpti_id);
  911. /* Unfortunately, unless you use the new EH code, which
  912. * we don't, the midlayer will ignore the return value,
  913. * which is insane. We pick up the pieces like this.
  914. */
  915. Cmnd->result = DID_BUS_BUSY;
  916. done(Cmnd);
  917. return 1;
  918. }
  919. static DEF_SCSI_QCMD(qlogicpti_queuecommand)
  920. static int qlogicpti_return_status(struct Status_Entry *sts, int id)
  921. {
  922. int host_status = DID_ERROR;
  923. switch (sts->completion_status) {
  924. case CS_COMPLETE:
  925. host_status = DID_OK;
  926. break;
  927. case CS_INCOMPLETE:
  928. if (!(sts->state_flags & SF_GOT_BUS))
  929. host_status = DID_NO_CONNECT;
  930. else if (!(sts->state_flags & SF_GOT_TARGET))
  931. host_status = DID_BAD_TARGET;
  932. else if (!(sts->state_flags & SF_SENT_CDB))
  933. host_status = DID_ERROR;
  934. else if (!(sts->state_flags & SF_TRANSFERRED_DATA))
  935. host_status = DID_ERROR;
  936. else if (!(sts->state_flags & SF_GOT_STATUS))
  937. host_status = DID_ERROR;
  938. else if (!(sts->state_flags & SF_GOT_SENSE))
  939. host_status = DID_ERROR;
  940. break;
  941. case CS_DMA_ERROR:
  942. case CS_TRANSPORT_ERROR:
  943. host_status = DID_ERROR;
  944. break;
  945. case CS_RESET_OCCURRED:
  946. case CS_BUS_RESET:
  947. host_status = DID_RESET;
  948. break;
  949. case CS_ABORTED:
  950. host_status = DID_ABORT;
  951. break;
  952. case CS_TIMEOUT:
  953. host_status = DID_TIME_OUT;
  954. break;
  955. case CS_DATA_OVERRUN:
  956. case CS_COMMAND_OVERRUN:
  957. case CS_STATUS_OVERRUN:
  958. case CS_BAD_MESSAGE:
  959. case CS_NO_MESSAGE_OUT:
  960. case CS_EXT_ID_FAILED:
  961. case CS_IDE_MSG_FAILED:
  962. case CS_ABORT_MSG_FAILED:
  963. case CS_NOP_MSG_FAILED:
  964. case CS_PARITY_ERROR_MSG_FAILED:
  965. case CS_DEVICE_RESET_MSG_FAILED:
  966. case CS_ID_MSG_FAILED:
  967. case CS_UNEXP_BUS_FREE:
  968. host_status = DID_ERROR;
  969. break;
  970. case CS_DATA_UNDERRUN:
  971. host_status = DID_OK;
  972. break;
  973. default:
  974. printk(KERN_EMERG "qlogicpti%d: unknown completion status 0x%04x\n",
  975. id, sts->completion_status);
  976. host_status = DID_ERROR;
  977. break;
  978. }
  979. return (sts->scsi_status & STATUS_MASK) | (host_status << 16);
  980. }
  981. static struct scsi_cmnd *qlogicpti_intr_handler(struct qlogicpti *qpti)
  982. {
  983. struct scsi_cmnd *Cmnd, *done_queue = NULL;
  984. struct Status_Entry *sts;
  985. u_int in_ptr, out_ptr;
  986. if (!(sbus_readw(qpti->qregs + SBUS_STAT) & SBUS_STAT_RINT))
  987. return NULL;
  988. in_ptr = sbus_readw(qpti->qregs + MBOX5);
  989. sbus_writew(HCCTRL_CRIRQ, qpti->qregs + HCCTRL);
  990. if (sbus_readw(qpti->qregs + SBUS_SEMAPHORE) & SBUS_SEMAPHORE_LCK) {
  991. switch (sbus_readw(qpti->qregs + MBOX0)) {
  992. case ASYNC_SCSI_BUS_RESET:
  993. case EXECUTION_TIMEOUT_RESET:
  994. qpti->send_marker = 1;
  995. break;
  996. case INVALID_COMMAND:
  997. case HOST_INTERFACE_ERROR:
  998. case COMMAND_ERROR:
  999. case COMMAND_PARAM_ERROR:
  1000. break;
  1001. };
  1002. sbus_writew(0, qpti->qregs + SBUS_SEMAPHORE);
  1003. }
  1004. /* This looks like a network driver! */
  1005. out_ptr = qpti->res_out_ptr;
  1006. while (out_ptr != in_ptr) {
  1007. u_int cmd_slot;
  1008. sts = (struct Status_Entry *) &qpti->res_cpu[out_ptr];
  1009. out_ptr = NEXT_RES_PTR(out_ptr);
  1010. /* We store an index in the handle, not the pointer in
  1011. * some form. This avoids problems due to the fact
  1012. * that the handle provided is only 32-bits. -DaveM
  1013. */
  1014. cmd_slot = sts->handle;
  1015. Cmnd = qpti->cmd_slots[cmd_slot];
  1016. qpti->cmd_slots[cmd_slot] = NULL;
  1017. if (sts->completion_status == CS_RESET_OCCURRED ||
  1018. sts->completion_status == CS_ABORTED ||
  1019. (sts->status_flags & STF_BUS_RESET))
  1020. qpti->send_marker = 1;
  1021. if (sts->state_flags & SF_GOT_SENSE)
  1022. memcpy(Cmnd->sense_buffer, sts->req_sense_data,
  1023. SCSI_SENSE_BUFFERSIZE);
  1024. if (sts->hdr.entry_type == ENTRY_STATUS)
  1025. Cmnd->result =
  1026. qlogicpti_return_status(sts, qpti->qpti_id);
  1027. else
  1028. Cmnd->result = DID_ERROR << 16;
  1029. if (scsi_bufflen(Cmnd))
  1030. dma_unmap_sg(&qpti->op->dev,
  1031. scsi_sglist(Cmnd), scsi_sg_count(Cmnd),
  1032. Cmnd->sc_data_direction);
  1033. qpti->cmd_count[Cmnd->device->id]--;
  1034. sbus_writew(out_ptr, qpti->qregs + MBOX5);
  1035. Cmnd->host_scribble = (unsigned char *) done_queue;
  1036. done_queue = Cmnd;
  1037. }
  1038. qpti->res_out_ptr = out_ptr;
  1039. return done_queue;
  1040. }
  1041. static irqreturn_t qpti_intr(int irq, void *dev_id)
  1042. {
  1043. struct qlogicpti *qpti = dev_id;
  1044. unsigned long flags;
  1045. struct scsi_cmnd *dq;
  1046. spin_lock_irqsave(qpti->qhost->host_lock, flags);
  1047. dq = qlogicpti_intr_handler(qpti);
  1048. if (dq != NULL) {
  1049. do {
  1050. struct scsi_cmnd *next;
  1051. next = (struct scsi_cmnd *) dq->host_scribble;
  1052. dq->scsi_done(dq);
  1053. dq = next;
  1054. } while (dq != NULL);
  1055. }
  1056. spin_unlock_irqrestore(qpti->qhost->host_lock, flags);
  1057. return IRQ_HANDLED;
  1058. }
  1059. static int qlogicpti_abort(struct scsi_cmnd *Cmnd)
  1060. {
  1061. u_short param[6];
  1062. struct Scsi_Host *host = Cmnd->device->host;
  1063. struct qlogicpti *qpti = (struct qlogicpti *) host->hostdata;
  1064. int return_status = SUCCESS;
  1065. u32 cmd_cookie;
  1066. int i;
  1067. printk(KERN_WARNING "qlogicpti%d: Aborting cmd for tgt[%d] lun[%d]\n",
  1068. qpti->qpti_id, (int)Cmnd->device->id, (int)Cmnd->device->lun);
  1069. qlogicpti_disable_irqs(qpti);
  1070. /* Find the 32-bit cookie we gave to the firmware for
  1071. * this command.
  1072. */
  1073. for (i = 0; i < QLOGICPTI_REQ_QUEUE_LEN + 1; i++)
  1074. if (qpti->cmd_slots[i] == Cmnd)
  1075. break;
  1076. cmd_cookie = i;
  1077. param[0] = MBOX_ABORT;
  1078. param[1] = (((u_short) Cmnd->device->id) << 8) | Cmnd->device->lun;
  1079. param[2] = cmd_cookie >> 16;
  1080. param[3] = cmd_cookie & 0xffff;
  1081. if (qlogicpti_mbox_command(qpti, param, 0) ||
  1082. (param[0] != MBOX_COMMAND_COMPLETE)) {
  1083. printk(KERN_EMERG "qlogicpti%d: scsi abort failure: %x\n",
  1084. qpti->qpti_id, param[0]);
  1085. return_status = FAILED;
  1086. }
  1087. qlogicpti_enable_irqs(qpti);
  1088. return return_status;
  1089. }
  1090. static int qlogicpti_reset(struct scsi_cmnd *Cmnd)
  1091. {
  1092. u_short param[6];
  1093. struct Scsi_Host *host = Cmnd->device->host;
  1094. struct qlogicpti *qpti = (struct qlogicpti *) host->hostdata;
  1095. int return_status = SUCCESS;
  1096. printk(KERN_WARNING "qlogicpti%d: Resetting SCSI bus!\n",
  1097. qpti->qpti_id);
  1098. qlogicpti_disable_irqs(qpti);
  1099. param[0] = MBOX_BUS_RESET;
  1100. param[1] = qpti->host_param.bus_reset_delay;
  1101. if (qlogicpti_mbox_command(qpti, param, 0) ||
  1102. (param[0] != MBOX_COMMAND_COMPLETE)) {
  1103. printk(KERN_EMERG "qlogicisp%d: scsi bus reset failure: %x\n",
  1104. qpti->qpti_id, param[0]);
  1105. return_status = FAILED;
  1106. }
  1107. qlogicpti_enable_irqs(qpti);
  1108. return return_status;
  1109. }
  1110. static struct scsi_host_template qpti_template = {
  1111. .module = THIS_MODULE,
  1112. .name = "qlogicpti",
  1113. .info = qlogicpti_info,
  1114. .queuecommand = qlogicpti_queuecommand,
  1115. .slave_configure = qlogicpti_slave_configure,
  1116. .eh_abort_handler = qlogicpti_abort,
  1117. .eh_bus_reset_handler = qlogicpti_reset,
  1118. .can_queue = QLOGICPTI_REQ_QUEUE_LEN,
  1119. .this_id = 7,
  1120. .sg_tablesize = QLOGICPTI_MAX_SG(QLOGICPTI_REQ_QUEUE_LEN),
  1121. .cmd_per_lun = 1,
  1122. .use_clustering = ENABLE_CLUSTERING,
  1123. };
  1124. static const struct of_device_id qpti_match[];
  1125. static int __devinit qpti_sbus_probe(struct platform_device *op)
  1126. {
  1127. const struct of_device_id *match;
  1128. struct scsi_host_template *tpnt;
  1129. struct device_node *dp = op->dev.of_node;
  1130. struct Scsi_Host *host;
  1131. struct qlogicpti *qpti;
  1132. static int nqptis;
  1133. const char *fcode;
  1134. match = of_match_device(qpti_match, &op->dev);
  1135. if (!match)
  1136. return -EINVAL;
  1137. tpnt = match->data;
  1138. /* Sometimes Antares cards come up not completely
  1139. * setup, and we get a report of a zero IRQ.
  1140. */
  1141. if (op->archdata.irqs[0] == 0)
  1142. return -ENODEV;
  1143. host = scsi_host_alloc(tpnt, sizeof(struct qlogicpti));
  1144. if (!host)
  1145. return -ENOMEM;
  1146. qpti = shost_priv(host);
  1147. host->max_id = MAX_TARGETS;
  1148. qpti->qhost = host;
  1149. qpti->op = op;
  1150. qpti->qpti_id = nqptis;
  1151. strcpy(qpti->prom_name, op->dev.of_node->name);
  1152. qpti->is_pti = strcmp(qpti->prom_name, "QLGC,isp");
  1153. if (qpti_map_regs(qpti) < 0)
  1154. goto fail_unlink;
  1155. if (qpti_register_irq(qpti) < 0)
  1156. goto fail_unmap_regs;
  1157. qpti_get_scsi_id(qpti);
  1158. qpti_get_bursts(qpti);
  1159. qpti_get_clock(qpti);
  1160. /* Clear out scsi_cmnd array. */
  1161. memset(qpti->cmd_slots, 0, sizeof(qpti->cmd_slots));
  1162. if (qpti_map_queues(qpti) < 0)
  1163. goto fail_free_irq;
  1164. /* Load the firmware. */
  1165. if (qlogicpti_load_firmware(qpti))
  1166. goto fail_unmap_queues;
  1167. if (qpti->is_pti) {
  1168. /* Check the PTI status reg. */
  1169. if (qlogicpti_verify_tmon(qpti))
  1170. goto fail_unmap_queues;
  1171. }
  1172. /* Reset the ISP and init res/req queues. */
  1173. if (qlogicpti_reset_hardware(host))
  1174. goto fail_unmap_queues;
  1175. printk("(Firmware v%d.%d.%d)", qpti->fware_majrev,
  1176. qpti->fware_minrev, qpti->fware_micrev);
  1177. fcode = of_get_property(dp, "isp-fcode", NULL);
  1178. if (fcode && fcode[0])
  1179. printk("(FCode %s)", fcode);
  1180. if (of_find_property(dp, "differential", NULL) != NULL)
  1181. qpti->differential = 1;
  1182. printk("\nqlogicpti%d: [%s Wide, using %s interface]\n",
  1183. qpti->qpti_id,
  1184. (qpti->ultra ? "Ultra" : "Fast"),
  1185. (qpti->differential ? "differential" : "single ended"));
  1186. if (scsi_add_host(host, &op->dev)) {
  1187. printk("qlogicpti%d: Failed scsi_add_host\n", qpti->qpti_id);
  1188. goto fail_unmap_queues;
  1189. }
  1190. dev_set_drvdata(&op->dev, qpti);
  1191. qpti_chain_add(qpti);
  1192. scsi_scan_host(host);
  1193. nqptis++;
  1194. return 0;
  1195. fail_unmap_queues:
  1196. #define QSIZE(entries) (((entries) + 1) * QUEUE_ENTRY_LEN)
  1197. dma_free_coherent(&op->dev,
  1198. QSIZE(RES_QUEUE_LEN),
  1199. qpti->res_cpu, qpti->res_dvma);
  1200. dma_free_coherent(&op->dev,
  1201. QSIZE(QLOGICPTI_REQ_QUEUE_LEN),
  1202. qpti->req_cpu, qpti->req_dvma);
  1203. #undef QSIZE
  1204. fail_unmap_regs:
  1205. of_iounmap(&op->resource[0], qpti->qregs,
  1206. resource_size(&op->resource[0]));
  1207. if (qpti->is_pti)
  1208. of_iounmap(&op->resource[0], qpti->sreg,
  1209. sizeof(unsigned char));
  1210. fail_free_irq:
  1211. free_irq(qpti->irq, qpti);
  1212. fail_unlink:
  1213. scsi_host_put(host);
  1214. return -ENODEV;
  1215. }
  1216. static int __devexit qpti_sbus_remove(struct platform_device *op)
  1217. {
  1218. struct qlogicpti *qpti = dev_get_drvdata(&op->dev);
  1219. qpti_chain_del(qpti);
  1220. scsi_remove_host(qpti->qhost);
  1221. /* Shut up the card. */
  1222. sbus_writew(0, qpti->qregs + SBUS_CTRL);
  1223. /* Free IRQ handler and unmap Qlogic,ISP and PTI status regs. */
  1224. free_irq(qpti->irq, qpti);
  1225. #define QSIZE(entries) (((entries) + 1) * QUEUE_ENTRY_LEN)
  1226. dma_free_coherent(&op->dev,
  1227. QSIZE(RES_QUEUE_LEN),
  1228. qpti->res_cpu, qpti->res_dvma);
  1229. dma_free_coherent(&op->dev,
  1230. QSIZE(QLOGICPTI_REQ_QUEUE_LEN),
  1231. qpti->req_cpu, qpti->req_dvma);
  1232. #undef QSIZE
  1233. of_iounmap(&op->resource[0], qpti->qregs,
  1234. resource_size(&op->resource[0]));
  1235. if (qpti->is_pti)
  1236. of_iounmap(&op->resource[0], qpti->sreg, sizeof(unsigned char));
  1237. scsi_host_put(qpti->qhost);
  1238. return 0;
  1239. }
  1240. static const struct of_device_id qpti_match[] = {
  1241. {
  1242. .name = "ptisp",
  1243. .data = &qpti_template,
  1244. },
  1245. {
  1246. .name = "PTI,ptisp",
  1247. .data = &qpti_template,
  1248. },
  1249. {
  1250. .name = "QLGC,isp",
  1251. .data = &qpti_template,
  1252. },
  1253. {
  1254. .name = "SUNW,isp",
  1255. .data = &qpti_template,
  1256. },
  1257. {},
  1258. };
  1259. MODULE_DEVICE_TABLE(of, qpti_match);
  1260. static struct platform_driver qpti_sbus_driver = {
  1261. .driver = {
  1262. .name = "qpti",
  1263. .owner = THIS_MODULE,
  1264. .of_match_table = qpti_match,
  1265. },
  1266. .probe = qpti_sbus_probe,
  1267. .remove = __devexit_p(qpti_sbus_remove),
  1268. };
  1269. static int __init qpti_init(void)
  1270. {
  1271. return platform_driver_register(&qpti_sbus_driver);
  1272. }
  1273. static void __exit qpti_exit(void)
  1274. {
  1275. platform_driver_unregister(&qpti_sbus_driver);
  1276. }
  1277. MODULE_DESCRIPTION("QlogicISP SBUS driver");
  1278. MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  1279. MODULE_LICENSE("GPL");
  1280. MODULE_VERSION("2.1");
  1281. MODULE_FIRMWARE("qlogic/isp1000.bin");
  1282. module_init(qpti_init);
  1283. module_exit(qpti_exit);