setup-res.c 7.8 KB

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  1. /*
  2. * drivers/pci/setup-res.c
  3. *
  4. * Extruded from code written by
  5. * Dave Rusling (david.rusling@reo.mts.dec.com)
  6. * David Mosberger (davidm@cs.arizona.edu)
  7. * David Miller (davem@redhat.com)
  8. *
  9. * Support routines for initializing a PCI subsystem.
  10. */
  11. /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
  12. /*
  13. * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  14. * Resource sorting
  15. */
  16. #include <linux/init.h>
  17. #include <linux/kernel.h>
  18. #include <linux/pci.h>
  19. #include <linux/errno.h>
  20. #include <linux/ioport.h>
  21. #include <linux/cache.h>
  22. #include <linux/slab.h>
  23. #include "pci.h"
  24. void pci_update_resource(struct pci_dev *dev, int resno)
  25. {
  26. struct pci_bus_region region;
  27. u32 new, check, mask;
  28. int reg;
  29. enum pci_bar_type type;
  30. struct resource *res = dev->resource + resno;
  31. /*
  32. * Ignore resources for unimplemented BARs and unused resource slots
  33. * for 64 bit BARs.
  34. */
  35. if (!res->flags)
  36. return;
  37. /*
  38. * Ignore non-moveable resources. This might be legacy resources for
  39. * which no functional BAR register exists or another important
  40. * system resource we shouldn't move around.
  41. */
  42. if (res->flags & IORESOURCE_PCI_FIXED)
  43. return;
  44. pcibios_resource_to_bus(dev, &region, res);
  45. new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
  46. if (res->flags & IORESOURCE_IO)
  47. mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
  48. else
  49. mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
  50. reg = pci_resource_bar(dev, resno, &type);
  51. if (!reg)
  52. return;
  53. if (type != pci_bar_unknown) {
  54. if (!(res->flags & IORESOURCE_ROM_ENABLE))
  55. return;
  56. new |= PCI_ROM_ADDRESS_ENABLE;
  57. }
  58. pci_write_config_dword(dev, reg, new);
  59. pci_read_config_dword(dev, reg, &check);
  60. if ((new ^ check) & mask) {
  61. dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
  62. resno, new, check);
  63. }
  64. if ((new & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
  65. (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) {
  66. new = region.start >> 16 >> 16;
  67. pci_write_config_dword(dev, reg + 4, new);
  68. pci_read_config_dword(dev, reg + 4, &check);
  69. if (check != new) {
  70. dev_err(&dev->dev, "BAR %d: error updating "
  71. "(high %#08x != %#08x)\n", resno, new, check);
  72. }
  73. }
  74. res->flags &= ~IORESOURCE_UNSET;
  75. dev_info(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx])\n",
  76. resno, res, (unsigned long long)region.start,
  77. (unsigned long long)region.end);
  78. }
  79. int pci_claim_resource(struct pci_dev *dev, int resource)
  80. {
  81. struct resource *res = &dev->resource[resource];
  82. struct resource *root, *conflict;
  83. root = pci_find_parent_resource(dev, res);
  84. if (!root) {
  85. dev_info(&dev->dev, "no compatible bridge window for %pR\n",
  86. res);
  87. return -EINVAL;
  88. }
  89. conflict = request_resource_conflict(root, res);
  90. if (conflict) {
  91. dev_info(&dev->dev,
  92. "address space collision: %pR conflicts with %s %pR\n",
  93. res, conflict->name, conflict);
  94. return -EBUSY;
  95. }
  96. return 0;
  97. }
  98. EXPORT_SYMBOL(pci_claim_resource);
  99. #ifdef CONFIG_PCI_QUIRKS
  100. void pci_disable_bridge_window(struct pci_dev *dev)
  101. {
  102. dev_info(&dev->dev, "disabling bridge mem windows\n");
  103. /* MMIO Base/Limit */
  104. pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
  105. /* Prefetchable MMIO Base/Limit */
  106. pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
  107. pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
  108. pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
  109. }
  110. #endif /* CONFIG_PCI_QUIRKS */
  111. static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
  112. int resno)
  113. {
  114. struct resource *res = dev->resource + resno;
  115. resource_size_t size, min, align;
  116. int ret;
  117. size = resource_size(res);
  118. min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
  119. align = pci_resource_alignment(dev, res);
  120. /* First, try exact prefetching match.. */
  121. ret = pci_bus_alloc_resource(bus, res, size, align, min,
  122. IORESOURCE_PREFETCH,
  123. pcibios_align_resource, dev);
  124. if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
  125. /*
  126. * That failed.
  127. *
  128. * But a prefetching area can handle a non-prefetching
  129. * window (it will just not perform as well).
  130. */
  131. ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
  132. pcibios_align_resource, dev);
  133. }
  134. if (ret < 0 && dev->fw_addr[resno]) {
  135. struct resource *root, *conflict;
  136. resource_size_t start, end;
  137. /*
  138. * If we failed to assign anything, let's try the address
  139. * where firmware left it. That at least has a chance of
  140. * working, which is better than just leaving it disabled.
  141. */
  142. if (res->flags & IORESOURCE_IO)
  143. root = &ioport_resource;
  144. else
  145. root = &iomem_resource;
  146. start = res->start;
  147. end = res->end;
  148. res->start = dev->fw_addr[resno];
  149. res->end = res->start + size - 1;
  150. dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
  151. resno, res);
  152. conflict = request_resource_conflict(root, res);
  153. if (conflict) {
  154. dev_info(&dev->dev,
  155. "BAR %d: %pR conflicts with %s %pR\n", resno,
  156. res, conflict->name, conflict);
  157. res->start = start;
  158. res->end = end;
  159. } else
  160. ret = 0;
  161. }
  162. if (!ret) {
  163. res->flags &= ~IORESOURCE_STARTALIGN;
  164. dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
  165. if (resno < PCI_BRIDGE_RESOURCES)
  166. pci_update_resource(dev, resno);
  167. }
  168. return ret;
  169. }
  170. int pci_assign_resource(struct pci_dev *dev, int resno)
  171. {
  172. struct resource *res = dev->resource + resno;
  173. resource_size_t align;
  174. struct pci_bus *bus;
  175. int ret;
  176. char *type;
  177. align = pci_resource_alignment(dev, res);
  178. if (!align) {
  179. dev_info(&dev->dev, "BAR %d: can't assign %pR "
  180. "(bogus alignment)\n", resno, res);
  181. return -EINVAL;
  182. }
  183. bus = dev->bus;
  184. while ((ret = __pci_assign_resource(bus, dev, resno))) {
  185. if (bus->parent && bus->self->transparent)
  186. bus = bus->parent;
  187. else
  188. bus = NULL;
  189. if (bus)
  190. continue;
  191. break;
  192. }
  193. if (ret) {
  194. if (res->flags & IORESOURCE_MEM)
  195. if (res->flags & IORESOURCE_PREFETCH)
  196. type = "mem pref";
  197. else
  198. type = "mem";
  199. else if (res->flags & IORESOURCE_IO)
  200. type = "io";
  201. else
  202. type = "unknown";
  203. dev_info(&dev->dev,
  204. "BAR %d: can't assign %s (size %#llx)\n",
  205. resno, type, (unsigned long long) resource_size(res));
  206. }
  207. return ret;
  208. }
  209. /* Sort resources by alignment */
  210. void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
  211. {
  212. int i;
  213. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  214. struct resource *r;
  215. struct resource_list *list, *tmp;
  216. resource_size_t r_align;
  217. r = &dev->resource[i];
  218. if (r->flags & IORESOURCE_PCI_FIXED)
  219. continue;
  220. if (!(r->flags) || r->parent)
  221. continue;
  222. r_align = pci_resource_alignment(dev, r);
  223. if (!r_align) {
  224. dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
  225. i, r);
  226. continue;
  227. }
  228. for (list = head; ; list = list->next) {
  229. resource_size_t align = 0;
  230. struct resource_list *ln = list->next;
  231. if (ln)
  232. align = pci_resource_alignment(ln->dev, ln->res);
  233. if (r_align > align) {
  234. tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
  235. if (!tmp)
  236. panic("pdev_sort_resources(): "
  237. "kmalloc() failed!\n");
  238. tmp->next = ln;
  239. tmp->res = r;
  240. tmp->dev = dev;
  241. list->next = tmp;
  242. break;
  243. }
  244. }
  245. }
  246. }
  247. int pci_enable_resources(struct pci_dev *dev, int mask)
  248. {
  249. u16 cmd, old_cmd;
  250. int i;
  251. struct resource *r;
  252. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  253. old_cmd = cmd;
  254. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  255. if (!(mask & (1 << i)))
  256. continue;
  257. r = &dev->resource[i];
  258. if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
  259. continue;
  260. if ((i == PCI_ROM_RESOURCE) &&
  261. (!(r->flags & IORESOURCE_ROM_ENABLE)))
  262. continue;
  263. if (!r->parent) {
  264. dev_err(&dev->dev, "device not available "
  265. "(can't reserve %pR)\n", r);
  266. return -EINVAL;
  267. }
  268. if (r->flags & IORESOURCE_IO)
  269. cmd |= PCI_COMMAND_IO;
  270. if (r->flags & IORESOURCE_MEM)
  271. cmd |= PCI_COMMAND_MEMORY;
  272. }
  273. if (cmd != old_cmd) {
  274. dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
  275. old_cmd, cmd);
  276. pci_write_config_word(dev, PCI_COMMAND, cmd);
  277. }
  278. return 0;
  279. }