falcon_xmac.c 12 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2006-2010 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/delay.h>
  11. #include "net_driver.h"
  12. #include "efx.h"
  13. #include "nic.h"
  14. #include "regs.h"
  15. #include "io.h"
  16. #include "mac.h"
  17. #include "mdio_10g.h"
  18. #include "workarounds.h"
  19. /**************************************************************************
  20. *
  21. * MAC operations
  22. *
  23. *************************************************************************/
  24. /* Configure the XAUI driver that is an output from Falcon */
  25. void falcon_setup_xaui(struct efx_nic *efx)
  26. {
  27. efx_oword_t sdctl, txdrv;
  28. /* Move the XAUI into low power, unless there is no PHY, in
  29. * which case the XAUI will have to drive a cable. */
  30. if (efx->phy_type == PHY_TYPE_NONE)
  31. return;
  32. efx_reado(efx, &sdctl, FR_AB_XX_SD_CTL);
  33. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
  34. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
  35. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
  36. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
  37. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
  38. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
  39. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
  40. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
  41. efx_writeo(efx, &sdctl, FR_AB_XX_SD_CTL);
  42. EFX_POPULATE_OWORD_8(txdrv,
  43. FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF,
  44. FRF_AB_XX_DEQC, FFE_AB_XX_TXDRV_DEQ_DEF,
  45. FRF_AB_XX_DEQB, FFE_AB_XX_TXDRV_DEQ_DEF,
  46. FRF_AB_XX_DEQA, FFE_AB_XX_TXDRV_DEQ_DEF,
  47. FRF_AB_XX_DTXD, FFE_AB_XX_TXDRV_DTX_DEF,
  48. FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF,
  49. FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF,
  50. FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF);
  51. efx_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL);
  52. }
  53. int falcon_reset_xaui(struct efx_nic *efx)
  54. {
  55. struct falcon_nic_data *nic_data = efx->nic_data;
  56. efx_oword_t reg;
  57. int count;
  58. /* Don't fetch MAC statistics over an XMAC reset */
  59. WARN_ON(nic_data->stats_disable_count == 0);
  60. /* Start reset sequence */
  61. EFX_POPULATE_OWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);
  62. efx_writeo(efx, &reg, FR_AB_XX_PWR_RST);
  63. /* Wait up to 10 ms for completion, then reinitialise */
  64. for (count = 0; count < 1000; count++) {
  65. efx_reado(efx, &reg, FR_AB_XX_PWR_RST);
  66. if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 &&
  67. EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) {
  68. falcon_setup_xaui(efx);
  69. return 0;
  70. }
  71. udelay(10);
  72. }
  73. netif_err(efx, hw, efx->net_dev,
  74. "timed out waiting for XAUI/XGXS reset\n");
  75. return -ETIMEDOUT;
  76. }
  77. static void falcon_ack_status_intr(struct efx_nic *efx)
  78. {
  79. struct falcon_nic_data *nic_data = efx->nic_data;
  80. efx_oword_t reg;
  81. if ((efx_nic_rev(efx) != EFX_REV_FALCON_B0) || LOOPBACK_INTERNAL(efx))
  82. return;
  83. /* We expect xgmii faults if the wireside link is down */
  84. if (!EFX_WORKAROUND_5147(efx) || !efx->link_state.up)
  85. return;
  86. /* We can only use this interrupt to signal the negative edge of
  87. * xaui_align [we have to poll the positive edge]. */
  88. if (nic_data->xmac_poll_required)
  89. return;
  90. efx_reado(efx, &reg, FR_AB_XM_MGT_INT_MSK);
  91. }
  92. static bool falcon_xgxs_link_ok(struct efx_nic *efx)
  93. {
  94. efx_oword_t reg;
  95. bool align_done, link_ok = false;
  96. int sync_status;
  97. /* Read link status */
  98. efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
  99. align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE);
  100. sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT);
  101. if (align_done && (sync_status == FFE_AB_XX_STAT_ALL_LANES))
  102. link_ok = true;
  103. /* Clear link status ready for next read */
  104. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);
  105. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES);
  106. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES);
  107. efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
  108. return link_ok;
  109. }
  110. static bool falcon_xmac_link_ok(struct efx_nic *efx)
  111. {
  112. /*
  113. * Check MAC's XGXS link status except when using XGMII loopback
  114. * which bypasses the XGXS block.
  115. * If possible, check PHY's XGXS link status except when using
  116. * MAC loopback.
  117. */
  118. return (efx->loopback_mode == LOOPBACK_XGMII ||
  119. falcon_xgxs_link_ok(efx)) &&
  120. (!(efx->mdio.mmds & (1 << MDIO_MMD_PHYXS)) ||
  121. LOOPBACK_INTERNAL(efx) ||
  122. efx_mdio_phyxgxs_lane_sync(efx));
  123. }
  124. static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
  125. {
  126. unsigned int max_frame_len;
  127. efx_oword_t reg;
  128. bool rx_fc = !!(efx->link_state.fc & EFX_FC_RX);
  129. bool tx_fc = !!(efx->link_state.fc & EFX_FC_TX);
  130. /* Configure MAC - cut-thru mode is hard wired on */
  131. EFX_POPULATE_OWORD_3(reg,
  132. FRF_AB_XM_RX_JUMBO_MODE, 1,
  133. FRF_AB_XM_TX_STAT_EN, 1,
  134. FRF_AB_XM_RX_STAT_EN, 1);
  135. efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
  136. /* Configure TX */
  137. EFX_POPULATE_OWORD_6(reg,
  138. FRF_AB_XM_TXEN, 1,
  139. FRF_AB_XM_TX_PRMBL, 1,
  140. FRF_AB_XM_AUTO_PAD, 1,
  141. FRF_AB_XM_TXCRC, 1,
  142. FRF_AB_XM_FCNTL, tx_fc,
  143. FRF_AB_XM_IPG, 0x3);
  144. efx_writeo(efx, &reg, FR_AB_XM_TX_CFG);
  145. /* Configure RX */
  146. EFX_POPULATE_OWORD_5(reg,
  147. FRF_AB_XM_RXEN, 1,
  148. FRF_AB_XM_AUTO_DEPAD, 0,
  149. FRF_AB_XM_ACPT_ALL_MCAST, 1,
  150. FRF_AB_XM_ACPT_ALL_UCAST, efx->promiscuous,
  151. FRF_AB_XM_PASS_CRC_ERR, 1);
  152. efx_writeo(efx, &reg, FR_AB_XM_RX_CFG);
  153. /* Set frame length */
  154. max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
  155. EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);
  156. efx_writeo(efx, &reg, FR_AB_XM_RX_PARAM);
  157. EFX_POPULATE_OWORD_2(reg,
  158. FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,
  159. FRF_AB_XM_TX_JUMBO_MODE, 1);
  160. efx_writeo(efx, &reg, FR_AB_XM_TX_PARAM);
  161. EFX_POPULATE_OWORD_2(reg,
  162. FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
  163. FRF_AB_XM_DIS_FCNTL, !rx_fc);
  164. efx_writeo(efx, &reg, FR_AB_XM_FC);
  165. /* Set MAC address */
  166. memcpy(&reg, &efx->net_dev->dev_addr[0], 4);
  167. efx_writeo(efx, &reg, FR_AB_XM_ADR_LO);
  168. memcpy(&reg, &efx->net_dev->dev_addr[4], 2);
  169. efx_writeo(efx, &reg, FR_AB_XM_ADR_HI);
  170. }
  171. static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
  172. {
  173. efx_oword_t reg;
  174. bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
  175. bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
  176. bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
  177. /* XGXS block is flaky and will need to be reset if moving
  178. * into our out of XGMII, XGXS or XAUI loopbacks. */
  179. if (EFX_WORKAROUND_5147(efx)) {
  180. bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
  181. bool reset_xgxs;
  182. efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
  183. old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN);
  184. old_xgmii_loopback =
  185. EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN);
  186. efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
  187. old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA);
  188. /* The PHY driver may have turned XAUI off */
  189. reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) ||
  190. (xaui_loopback != old_xaui_loopback) ||
  191. (xgmii_loopback != old_xgmii_loopback));
  192. if (reset_xgxs)
  193. falcon_reset_xaui(efx);
  194. }
  195. efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
  196. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG,
  197. (xgxs_loopback || xaui_loopback) ?
  198. FFE_AB_XX_FORCE_SIG_ALL_LANES : 0);
  199. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback);
  200. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback);
  201. efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
  202. efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
  203. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback);
  204. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback);
  205. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback);
  206. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback);
  207. efx_writeo(efx, &reg, FR_AB_XX_SD_CTL);
  208. }
  209. /* Try to bring up the Falcon side of the Falcon-Phy XAUI link */
  210. static bool falcon_xmac_link_ok_retry(struct efx_nic *efx, int tries)
  211. {
  212. bool mac_up = falcon_xmac_link_ok(efx);
  213. if (LOOPBACK_MASK(efx) & LOOPBACKS_EXTERNAL(efx) & LOOPBACKS_WS ||
  214. efx_phy_mode_disabled(efx->phy_mode))
  215. /* XAUI link is expected to be down */
  216. return mac_up;
  217. falcon_stop_nic_stats(efx);
  218. while (!mac_up && tries) {
  219. netif_dbg(efx, hw, efx->net_dev, "bashing xaui\n");
  220. falcon_reset_xaui(efx);
  221. udelay(200);
  222. mac_up = falcon_xmac_link_ok(efx);
  223. --tries;
  224. }
  225. falcon_start_nic_stats(efx);
  226. return mac_up;
  227. }
  228. static bool falcon_xmac_check_fault(struct efx_nic *efx)
  229. {
  230. return !falcon_xmac_link_ok_retry(efx, 5);
  231. }
  232. static int falcon_reconfigure_xmac(struct efx_nic *efx)
  233. {
  234. struct falcon_nic_data *nic_data = efx->nic_data;
  235. falcon_reconfigure_xgxs_core(efx);
  236. falcon_reconfigure_xmac_core(efx);
  237. falcon_reconfigure_mac_wrapper(efx);
  238. nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 5);
  239. falcon_ack_status_intr(efx);
  240. return 0;
  241. }
  242. static void falcon_update_stats_xmac(struct efx_nic *efx)
  243. {
  244. struct efx_mac_stats *mac_stats = &efx->mac_stats;
  245. /* Update MAC stats from DMAed values */
  246. FALCON_STAT(efx, XgRxOctets, rx_bytes);
  247. FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
  248. FALCON_STAT(efx, XgRxPkts, rx_packets);
  249. FALCON_STAT(efx, XgRxPktsOK, rx_good);
  250. FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
  251. FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
  252. FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
  253. FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
  254. FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
  255. FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
  256. FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
  257. FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
  258. FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
  259. FALCON_STAT(efx, XgRxAlignError, rx_align_error);
  260. FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
  261. FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
  262. FALCON_STAT(efx, XgRxControlPkts, rx_control);
  263. FALCON_STAT(efx, XgRxPausePkts, rx_pause);
  264. FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
  265. FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
  266. FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
  267. FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
  268. FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
  269. FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
  270. FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
  271. FALCON_STAT(efx, XgRxLengthError, rx_length_error);
  272. FALCON_STAT(efx, XgTxPkts, tx_packets);
  273. FALCON_STAT(efx, XgTxOctets, tx_bytes);
  274. FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
  275. FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
  276. FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
  277. FALCON_STAT(efx, XgTxControlPkts, tx_control);
  278. FALCON_STAT(efx, XgTxPausePkts, tx_pause);
  279. FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
  280. FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
  281. FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
  282. FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
  283. FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
  284. FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
  285. FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
  286. FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
  287. FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
  288. FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
  289. FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
  290. FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);
  291. /* Update derived statistics */
  292. mac_stats->tx_good_bytes =
  293. (mac_stats->tx_bytes - mac_stats->tx_bad_bytes -
  294. mac_stats->tx_control * 64);
  295. mac_stats->rx_bad_bytes =
  296. (mac_stats->rx_bytes - mac_stats->rx_good_bytes -
  297. mac_stats->rx_control * 64);
  298. }
  299. void falcon_poll_xmac(struct efx_nic *efx)
  300. {
  301. struct falcon_nic_data *nic_data = efx->nic_data;
  302. if (!EFX_WORKAROUND_5147(efx) || !efx->link_state.up ||
  303. !nic_data->xmac_poll_required)
  304. return;
  305. nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 1);
  306. falcon_ack_status_intr(efx);
  307. }
  308. const struct efx_mac_operations falcon_xmac_operations = {
  309. .reconfigure = falcon_reconfigure_xmac,
  310. .update_stats = falcon_update_stats_xmac,
  311. .check_fault = falcon_xmac_check_fault,
  312. };