qlge_mpi.c 30 KB

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  1. #include "qlge.h"
  2. int ql_unpause_mpi_risc(struct ql_adapter *qdev)
  3. {
  4. u32 tmp;
  5. /* Un-pause the RISC */
  6. tmp = ql_read32(qdev, CSR);
  7. if (!(tmp & CSR_RP))
  8. return -EIO;
  9. ql_write32(qdev, CSR, CSR_CMD_CLR_PAUSE);
  10. return 0;
  11. }
  12. int ql_pause_mpi_risc(struct ql_adapter *qdev)
  13. {
  14. u32 tmp;
  15. int count = UDELAY_COUNT;
  16. /* Pause the RISC */
  17. ql_write32(qdev, CSR, CSR_CMD_SET_PAUSE);
  18. do {
  19. tmp = ql_read32(qdev, CSR);
  20. if (tmp & CSR_RP)
  21. break;
  22. mdelay(UDELAY_DELAY);
  23. count--;
  24. } while (count);
  25. return (count == 0) ? -ETIMEDOUT : 0;
  26. }
  27. int ql_hard_reset_mpi_risc(struct ql_adapter *qdev)
  28. {
  29. u32 tmp;
  30. int count = UDELAY_COUNT;
  31. /* Reset the RISC */
  32. ql_write32(qdev, CSR, CSR_CMD_SET_RST);
  33. do {
  34. tmp = ql_read32(qdev, CSR);
  35. if (tmp & CSR_RR) {
  36. ql_write32(qdev, CSR, CSR_CMD_CLR_RST);
  37. break;
  38. }
  39. mdelay(UDELAY_DELAY);
  40. count--;
  41. } while (count);
  42. return (count == 0) ? -ETIMEDOUT : 0;
  43. }
  44. int ql_read_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
  45. {
  46. int status;
  47. /* wait for reg to come ready */
  48. status = ql_wait_reg_rdy(qdev, PROC_ADDR, PROC_ADDR_RDY, PROC_ADDR_ERR);
  49. if (status)
  50. goto exit;
  51. /* set up for reg read */
  52. ql_write32(qdev, PROC_ADDR, reg | PROC_ADDR_R);
  53. /* wait for reg to come ready */
  54. status = ql_wait_reg_rdy(qdev, PROC_ADDR, PROC_ADDR_RDY, PROC_ADDR_ERR);
  55. if (status)
  56. goto exit;
  57. /* get the data */
  58. *data = ql_read32(qdev, PROC_DATA);
  59. exit:
  60. return status;
  61. }
  62. int ql_write_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 data)
  63. {
  64. int status = 0;
  65. /* wait for reg to come ready */
  66. status = ql_wait_reg_rdy(qdev, PROC_ADDR, PROC_ADDR_RDY, PROC_ADDR_ERR);
  67. if (status)
  68. goto exit;
  69. /* write the data to the data reg */
  70. ql_write32(qdev, PROC_DATA, data);
  71. /* trigger the write */
  72. ql_write32(qdev, PROC_ADDR, reg);
  73. /* wait for reg to come ready */
  74. status = ql_wait_reg_rdy(qdev, PROC_ADDR, PROC_ADDR_RDY, PROC_ADDR_ERR);
  75. if (status)
  76. goto exit;
  77. exit:
  78. return status;
  79. }
  80. int ql_soft_reset_mpi_risc(struct ql_adapter *qdev)
  81. {
  82. int status;
  83. status = ql_write_mpi_reg(qdev, 0x00001010, 1);
  84. return status;
  85. }
  86. /* Determine if we are in charge of the firwmare. If
  87. * we are the lower of the 2 NIC pcie functions, or if
  88. * we are the higher function and the lower function
  89. * is not enabled.
  90. */
  91. int ql_own_firmware(struct ql_adapter *qdev)
  92. {
  93. u32 temp;
  94. /* If we are the lower of the 2 NIC functions
  95. * on the chip the we are responsible for
  96. * core dump and firmware reset after an error.
  97. */
  98. if (qdev->func < qdev->alt_func)
  99. return 1;
  100. /* If we are the higher of the 2 NIC functions
  101. * on the chip and the lower function is not
  102. * enabled, then we are responsible for
  103. * core dump and firmware reset after an error.
  104. */
  105. temp = ql_read32(qdev, STS);
  106. if (!(temp & (1 << (8 + qdev->alt_func))))
  107. return 1;
  108. return 0;
  109. }
  110. static int ql_get_mb_sts(struct ql_adapter *qdev, struct mbox_params *mbcp)
  111. {
  112. int i, status;
  113. status = ql_sem_spinlock(qdev, SEM_PROC_REG_MASK);
  114. if (status)
  115. return -EBUSY;
  116. for (i = 0; i < mbcp->out_count; i++) {
  117. status =
  118. ql_read_mpi_reg(qdev, qdev->mailbox_out + i,
  119. &mbcp->mbox_out[i]);
  120. if (status) {
  121. netif_err(qdev, drv, qdev->ndev, "Failed mailbox read.\n");
  122. break;
  123. }
  124. }
  125. ql_sem_unlock(qdev, SEM_PROC_REG_MASK); /* does flush too */
  126. return status;
  127. }
  128. /* Wait for a single mailbox command to complete.
  129. * Returns zero on success.
  130. */
  131. static int ql_wait_mbx_cmd_cmplt(struct ql_adapter *qdev)
  132. {
  133. int count = 100;
  134. u32 value;
  135. do {
  136. value = ql_read32(qdev, STS);
  137. if (value & STS_PI)
  138. return 0;
  139. mdelay(UDELAY_DELAY); /* 100ms */
  140. } while (--count);
  141. return -ETIMEDOUT;
  142. }
  143. /* Execute a single mailbox command.
  144. * Caller must hold PROC_ADDR semaphore.
  145. */
  146. static int ql_exec_mb_cmd(struct ql_adapter *qdev, struct mbox_params *mbcp)
  147. {
  148. int i, status;
  149. /*
  150. * Make sure there's nothing pending.
  151. * This shouldn't happen.
  152. */
  153. if (ql_read32(qdev, CSR) & CSR_HRI)
  154. return -EIO;
  155. status = ql_sem_spinlock(qdev, SEM_PROC_REG_MASK);
  156. if (status)
  157. return status;
  158. /*
  159. * Fill the outbound mailboxes.
  160. */
  161. for (i = 0; i < mbcp->in_count; i++) {
  162. status = ql_write_mpi_reg(qdev, qdev->mailbox_in + i,
  163. mbcp->mbox_in[i]);
  164. if (status)
  165. goto end;
  166. }
  167. /*
  168. * Wake up the MPI firmware.
  169. */
  170. ql_write32(qdev, CSR, CSR_CMD_SET_H2R_INT);
  171. end:
  172. ql_sem_unlock(qdev, SEM_PROC_REG_MASK);
  173. return status;
  174. }
  175. /* We are being asked by firmware to accept
  176. * a change to the port. This is only
  177. * a change to max frame sizes (Tx/Rx), pause
  178. * parameters, or loopback mode. We wake up a worker
  179. * to handler processing this since a mailbox command
  180. * will need to be sent to ACK the request.
  181. */
  182. static int ql_idc_req_aen(struct ql_adapter *qdev)
  183. {
  184. int status;
  185. struct mbox_params *mbcp = &qdev->idc_mbc;
  186. netif_err(qdev, drv, qdev->ndev, "Enter!\n");
  187. /* Get the status data and start up a thread to
  188. * handle the request.
  189. */
  190. mbcp = &qdev->idc_mbc;
  191. mbcp->out_count = 4;
  192. status = ql_get_mb_sts(qdev, mbcp);
  193. if (status) {
  194. netif_err(qdev, drv, qdev->ndev,
  195. "Could not read MPI, resetting ASIC!\n");
  196. ql_queue_asic_error(qdev);
  197. } else {
  198. /* Begin polled mode early so
  199. * we don't get another interrupt
  200. * when we leave mpi_worker.
  201. */
  202. ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));
  203. queue_delayed_work(qdev->workqueue, &qdev->mpi_idc_work, 0);
  204. }
  205. return status;
  206. }
  207. /* Process an inter-device event completion.
  208. * If good, signal the caller's completion.
  209. */
  210. static int ql_idc_cmplt_aen(struct ql_adapter *qdev)
  211. {
  212. int status;
  213. struct mbox_params *mbcp = &qdev->idc_mbc;
  214. mbcp->out_count = 4;
  215. status = ql_get_mb_sts(qdev, mbcp);
  216. if (status) {
  217. netif_err(qdev, drv, qdev->ndev,
  218. "Could not read MPI, resetting RISC!\n");
  219. ql_queue_fw_error(qdev);
  220. } else
  221. /* Wake up the sleeping mpi_idc_work thread that is
  222. * waiting for this event.
  223. */
  224. complete(&qdev->ide_completion);
  225. return status;
  226. }
  227. static void ql_link_up(struct ql_adapter *qdev, struct mbox_params *mbcp)
  228. {
  229. int status;
  230. mbcp->out_count = 2;
  231. status = ql_get_mb_sts(qdev, mbcp);
  232. if (status) {
  233. netif_err(qdev, drv, qdev->ndev,
  234. "%s: Could not get mailbox status.\n", __func__);
  235. return;
  236. }
  237. qdev->link_status = mbcp->mbox_out[1];
  238. netif_err(qdev, drv, qdev->ndev, "Link Up.\n");
  239. /* If we're coming back from an IDC event
  240. * then set up the CAM and frame routing.
  241. */
  242. if (test_bit(QL_CAM_RT_SET, &qdev->flags)) {
  243. status = ql_cam_route_initialize(qdev);
  244. if (status) {
  245. netif_err(qdev, ifup, qdev->ndev,
  246. "Failed to init CAM/Routing tables.\n");
  247. return;
  248. } else
  249. clear_bit(QL_CAM_RT_SET, &qdev->flags);
  250. }
  251. /* Queue up a worker to check the frame
  252. * size information, and fix it if it's not
  253. * to our liking.
  254. */
  255. if (!test_bit(QL_PORT_CFG, &qdev->flags)) {
  256. netif_err(qdev, drv, qdev->ndev, "Queue Port Config Worker!\n");
  257. set_bit(QL_PORT_CFG, &qdev->flags);
  258. /* Begin polled mode early so
  259. * we don't get another interrupt
  260. * when we leave mpi_worker dpc.
  261. */
  262. ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));
  263. queue_delayed_work(qdev->workqueue,
  264. &qdev->mpi_port_cfg_work, 0);
  265. }
  266. ql_link_on(qdev);
  267. }
  268. static void ql_link_down(struct ql_adapter *qdev, struct mbox_params *mbcp)
  269. {
  270. int status;
  271. mbcp->out_count = 3;
  272. status = ql_get_mb_sts(qdev, mbcp);
  273. if (status)
  274. netif_err(qdev, drv, qdev->ndev, "Link down AEN broken!\n");
  275. ql_link_off(qdev);
  276. }
  277. static int ql_sfp_in(struct ql_adapter *qdev, struct mbox_params *mbcp)
  278. {
  279. int status;
  280. mbcp->out_count = 5;
  281. status = ql_get_mb_sts(qdev, mbcp);
  282. if (status)
  283. netif_err(qdev, drv, qdev->ndev, "SFP in AEN broken!\n");
  284. else
  285. netif_err(qdev, drv, qdev->ndev, "SFP insertion detected.\n");
  286. return status;
  287. }
  288. static int ql_sfp_out(struct ql_adapter *qdev, struct mbox_params *mbcp)
  289. {
  290. int status;
  291. mbcp->out_count = 1;
  292. status = ql_get_mb_sts(qdev, mbcp);
  293. if (status)
  294. netif_err(qdev, drv, qdev->ndev, "SFP out AEN broken!\n");
  295. else
  296. netif_err(qdev, drv, qdev->ndev, "SFP removal detected.\n");
  297. return status;
  298. }
  299. static int ql_aen_lost(struct ql_adapter *qdev, struct mbox_params *mbcp)
  300. {
  301. int status;
  302. mbcp->out_count = 6;
  303. status = ql_get_mb_sts(qdev, mbcp);
  304. if (status)
  305. netif_err(qdev, drv, qdev->ndev, "Lost AEN broken!\n");
  306. else {
  307. int i;
  308. netif_err(qdev, drv, qdev->ndev, "Lost AEN detected.\n");
  309. for (i = 0; i < mbcp->out_count; i++)
  310. netif_err(qdev, drv, qdev->ndev, "mbox_out[%d] = 0x%.08x.\n",
  311. i, mbcp->mbox_out[i]);
  312. }
  313. return status;
  314. }
  315. static void ql_init_fw_done(struct ql_adapter *qdev, struct mbox_params *mbcp)
  316. {
  317. int status;
  318. mbcp->out_count = 2;
  319. status = ql_get_mb_sts(qdev, mbcp);
  320. if (status) {
  321. netif_err(qdev, drv, qdev->ndev, "Firmware did not initialize!\n");
  322. } else {
  323. netif_err(qdev, drv, qdev->ndev, "Firmware Revision = 0x%.08x.\n",
  324. mbcp->mbox_out[1]);
  325. qdev->fw_rev_id = mbcp->mbox_out[1];
  326. status = ql_cam_route_initialize(qdev);
  327. if (status)
  328. netif_err(qdev, ifup, qdev->ndev,
  329. "Failed to init CAM/Routing tables.\n");
  330. }
  331. }
  332. /* Process an async event and clear it unless it's an
  333. * error condition.
  334. * This can get called iteratively from the mpi_work thread
  335. * when events arrive via an interrupt.
  336. * It also gets called when a mailbox command is polling for
  337. * it's completion. */
  338. static int ql_mpi_handler(struct ql_adapter *qdev, struct mbox_params *mbcp)
  339. {
  340. int status;
  341. int orig_count = mbcp->out_count;
  342. /* Just get mailbox zero for now. */
  343. mbcp->out_count = 1;
  344. status = ql_get_mb_sts(qdev, mbcp);
  345. if (status) {
  346. netif_err(qdev, drv, qdev->ndev,
  347. "Could not read MPI, resetting ASIC!\n");
  348. ql_queue_asic_error(qdev);
  349. goto end;
  350. }
  351. switch (mbcp->mbox_out[0]) {
  352. /* This case is only active when we arrive here
  353. * as a result of issuing a mailbox command to
  354. * the firmware.
  355. */
  356. case MB_CMD_STS_INTRMDT:
  357. case MB_CMD_STS_GOOD:
  358. case MB_CMD_STS_INVLD_CMD:
  359. case MB_CMD_STS_XFC_ERR:
  360. case MB_CMD_STS_CSUM_ERR:
  361. case MB_CMD_STS_ERR:
  362. case MB_CMD_STS_PARAM_ERR:
  363. /* We can only get mailbox status if we're polling from an
  364. * unfinished command. Get the rest of the status data and
  365. * return back to the caller.
  366. * We only end up here when we're polling for a mailbox
  367. * command completion.
  368. */
  369. mbcp->out_count = orig_count;
  370. status = ql_get_mb_sts(qdev, mbcp);
  371. return status;
  372. /* We are being asked by firmware to accept
  373. * a change to the port. This is only
  374. * a change to max frame sizes (Tx/Rx), pause
  375. * parameters, or loopback mode.
  376. */
  377. case AEN_IDC_REQ:
  378. status = ql_idc_req_aen(qdev);
  379. break;
  380. /* Process and inbound IDC event.
  381. * This will happen when we're trying to
  382. * change tx/rx max frame size, change pause
  383. * parameters or loopback mode.
  384. */
  385. case AEN_IDC_CMPLT:
  386. case AEN_IDC_EXT:
  387. status = ql_idc_cmplt_aen(qdev);
  388. break;
  389. case AEN_LINK_UP:
  390. ql_link_up(qdev, mbcp);
  391. break;
  392. case AEN_LINK_DOWN:
  393. ql_link_down(qdev, mbcp);
  394. break;
  395. case AEN_FW_INIT_DONE:
  396. /* If we're in process on executing the firmware,
  397. * then convert the status to normal mailbox status.
  398. */
  399. if (mbcp->mbox_in[0] == MB_CMD_EX_FW) {
  400. mbcp->out_count = orig_count;
  401. status = ql_get_mb_sts(qdev, mbcp);
  402. mbcp->mbox_out[0] = MB_CMD_STS_GOOD;
  403. return status;
  404. }
  405. ql_init_fw_done(qdev, mbcp);
  406. break;
  407. case AEN_AEN_SFP_IN:
  408. ql_sfp_in(qdev, mbcp);
  409. break;
  410. case AEN_AEN_SFP_OUT:
  411. ql_sfp_out(qdev, mbcp);
  412. break;
  413. /* This event can arrive at boot time or after an
  414. * MPI reset if the firmware failed to initialize.
  415. */
  416. case AEN_FW_INIT_FAIL:
  417. /* If we're in process on executing the firmware,
  418. * then convert the status to normal mailbox status.
  419. */
  420. if (mbcp->mbox_in[0] == MB_CMD_EX_FW) {
  421. mbcp->out_count = orig_count;
  422. status = ql_get_mb_sts(qdev, mbcp);
  423. mbcp->mbox_out[0] = MB_CMD_STS_ERR;
  424. return status;
  425. }
  426. netif_err(qdev, drv, qdev->ndev,
  427. "Firmware initialization failed.\n");
  428. status = -EIO;
  429. ql_queue_fw_error(qdev);
  430. break;
  431. case AEN_SYS_ERR:
  432. netif_err(qdev, drv, qdev->ndev, "System Error.\n");
  433. ql_queue_fw_error(qdev);
  434. status = -EIO;
  435. break;
  436. case AEN_AEN_LOST:
  437. ql_aen_lost(qdev, mbcp);
  438. break;
  439. case AEN_DCBX_CHG:
  440. /* Need to support AEN 8110 */
  441. break;
  442. default:
  443. netif_err(qdev, drv, qdev->ndev,
  444. "Unsupported AE %.08x.\n", mbcp->mbox_out[0]);
  445. /* Clear the MPI firmware status. */
  446. }
  447. end:
  448. ql_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT);
  449. /* Restore the original mailbox count to
  450. * what the caller asked for. This can get
  451. * changed when a mailbox command is waiting
  452. * for a response and an AEN arrives and
  453. * is handled.
  454. * */
  455. mbcp->out_count = orig_count;
  456. return status;
  457. }
  458. /* Execute a single mailbox command.
  459. * mbcp is a pointer to an array of u32. Each
  460. * element in the array contains the value for it's
  461. * respective mailbox register.
  462. */
  463. static int ql_mailbox_command(struct ql_adapter *qdev, struct mbox_params *mbcp)
  464. {
  465. int status;
  466. unsigned long count;
  467. mutex_lock(&qdev->mpi_mutex);
  468. /* Begin polled mode for MPI */
  469. ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));
  470. /* Load the mailbox registers and wake up MPI RISC. */
  471. status = ql_exec_mb_cmd(qdev, mbcp);
  472. if (status)
  473. goto end;
  474. /* If we're generating a system error, then there's nothing
  475. * to wait for.
  476. */
  477. if (mbcp->mbox_in[0] == MB_CMD_MAKE_SYS_ERR)
  478. goto end;
  479. /* Wait for the command to complete. We loop
  480. * here because some AEN might arrive while
  481. * we're waiting for the mailbox command to
  482. * complete. If more than 5 seconds expire we can
  483. * assume something is wrong. */
  484. count = jiffies + HZ * MAILBOX_TIMEOUT;
  485. do {
  486. /* Wait for the interrupt to come in. */
  487. status = ql_wait_mbx_cmd_cmplt(qdev);
  488. if (status)
  489. continue;
  490. /* Process the event. If it's an AEN, it
  491. * will be handled in-line or a worker
  492. * will be spawned. If it's our completion
  493. * we will catch it below.
  494. */
  495. status = ql_mpi_handler(qdev, mbcp);
  496. if (status)
  497. goto end;
  498. /* It's either the completion for our mailbox
  499. * command complete or an AEN. If it's our
  500. * completion then get out.
  501. */
  502. if (((mbcp->mbox_out[0] & 0x0000f000) ==
  503. MB_CMD_STS_GOOD) ||
  504. ((mbcp->mbox_out[0] & 0x0000f000) ==
  505. MB_CMD_STS_INTRMDT))
  506. goto done;
  507. } while (time_before(jiffies, count));
  508. netif_err(qdev, drv, qdev->ndev,
  509. "Timed out waiting for mailbox complete.\n");
  510. status = -ETIMEDOUT;
  511. goto end;
  512. done:
  513. /* Now we can clear the interrupt condition
  514. * and look at our status.
  515. */
  516. ql_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT);
  517. if (((mbcp->mbox_out[0] & 0x0000f000) !=
  518. MB_CMD_STS_GOOD) &&
  519. ((mbcp->mbox_out[0] & 0x0000f000) !=
  520. MB_CMD_STS_INTRMDT)) {
  521. status = -EIO;
  522. }
  523. end:
  524. /* End polled mode for MPI */
  525. ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
  526. mutex_unlock(&qdev->mpi_mutex);
  527. return status;
  528. }
  529. /* Get MPI firmware version. This will be used for
  530. * driver banner and for ethtool info.
  531. * Returns zero on success.
  532. */
  533. int ql_mb_about_fw(struct ql_adapter *qdev)
  534. {
  535. struct mbox_params mbc;
  536. struct mbox_params *mbcp = &mbc;
  537. int status = 0;
  538. memset(mbcp, 0, sizeof(struct mbox_params));
  539. mbcp->in_count = 1;
  540. mbcp->out_count = 3;
  541. mbcp->mbox_in[0] = MB_CMD_ABOUT_FW;
  542. status = ql_mailbox_command(qdev, mbcp);
  543. if (status)
  544. return status;
  545. if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
  546. netif_err(qdev, drv, qdev->ndev,
  547. "Failed about firmware command\n");
  548. status = -EIO;
  549. }
  550. /* Store the firmware version */
  551. qdev->fw_rev_id = mbcp->mbox_out[1];
  552. return status;
  553. }
  554. /* Get functional state for MPI firmware.
  555. * Returns zero on success.
  556. */
  557. int ql_mb_get_fw_state(struct ql_adapter *qdev)
  558. {
  559. struct mbox_params mbc;
  560. struct mbox_params *mbcp = &mbc;
  561. int status = 0;
  562. memset(mbcp, 0, sizeof(struct mbox_params));
  563. mbcp->in_count = 1;
  564. mbcp->out_count = 2;
  565. mbcp->mbox_in[0] = MB_CMD_GET_FW_STATE;
  566. status = ql_mailbox_command(qdev, mbcp);
  567. if (status)
  568. return status;
  569. if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
  570. netif_err(qdev, drv, qdev->ndev,
  571. "Failed Get Firmware State.\n");
  572. status = -EIO;
  573. }
  574. /* If bit zero is set in mbx 1 then the firmware is
  575. * running, but not initialized. This should never
  576. * happen.
  577. */
  578. if (mbcp->mbox_out[1] & 1) {
  579. netif_err(qdev, drv, qdev->ndev,
  580. "Firmware waiting for initialization.\n");
  581. status = -EIO;
  582. }
  583. return status;
  584. }
  585. /* Send and ACK mailbox command to the firmware to
  586. * let it continue with the change.
  587. */
  588. static int ql_mb_idc_ack(struct ql_adapter *qdev)
  589. {
  590. struct mbox_params mbc;
  591. struct mbox_params *mbcp = &mbc;
  592. int status = 0;
  593. memset(mbcp, 0, sizeof(struct mbox_params));
  594. mbcp->in_count = 5;
  595. mbcp->out_count = 1;
  596. mbcp->mbox_in[0] = MB_CMD_IDC_ACK;
  597. mbcp->mbox_in[1] = qdev->idc_mbc.mbox_out[1];
  598. mbcp->mbox_in[2] = qdev->idc_mbc.mbox_out[2];
  599. mbcp->mbox_in[3] = qdev->idc_mbc.mbox_out[3];
  600. mbcp->mbox_in[4] = qdev->idc_mbc.mbox_out[4];
  601. status = ql_mailbox_command(qdev, mbcp);
  602. if (status)
  603. return status;
  604. if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
  605. netif_err(qdev, drv, qdev->ndev, "Failed IDC ACK send.\n");
  606. status = -EIO;
  607. }
  608. return status;
  609. }
  610. /* Get link settings and maximum frame size settings
  611. * for the current port.
  612. * Most likely will block.
  613. */
  614. int ql_mb_set_port_cfg(struct ql_adapter *qdev)
  615. {
  616. struct mbox_params mbc;
  617. struct mbox_params *mbcp = &mbc;
  618. int status = 0;
  619. memset(mbcp, 0, sizeof(struct mbox_params));
  620. mbcp->in_count = 3;
  621. mbcp->out_count = 1;
  622. mbcp->mbox_in[0] = MB_CMD_SET_PORT_CFG;
  623. mbcp->mbox_in[1] = qdev->link_config;
  624. mbcp->mbox_in[2] = qdev->max_frame_size;
  625. status = ql_mailbox_command(qdev, mbcp);
  626. if (status)
  627. return status;
  628. if (mbcp->mbox_out[0] == MB_CMD_STS_INTRMDT) {
  629. netif_err(qdev, drv, qdev->ndev,
  630. "Port Config sent, wait for IDC.\n");
  631. } else if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
  632. netif_err(qdev, drv, qdev->ndev,
  633. "Failed Set Port Configuration.\n");
  634. status = -EIO;
  635. }
  636. return status;
  637. }
  638. static int ql_mb_dump_ram(struct ql_adapter *qdev, u64 req_dma, u32 addr,
  639. u32 size)
  640. {
  641. int status = 0;
  642. struct mbox_params mbc;
  643. struct mbox_params *mbcp = &mbc;
  644. memset(mbcp, 0, sizeof(struct mbox_params));
  645. mbcp->in_count = 9;
  646. mbcp->out_count = 1;
  647. mbcp->mbox_in[0] = MB_CMD_DUMP_RISC_RAM;
  648. mbcp->mbox_in[1] = LSW(addr);
  649. mbcp->mbox_in[2] = MSW(req_dma);
  650. mbcp->mbox_in[3] = LSW(req_dma);
  651. mbcp->mbox_in[4] = MSW(size);
  652. mbcp->mbox_in[5] = LSW(size);
  653. mbcp->mbox_in[6] = MSW(MSD(req_dma));
  654. mbcp->mbox_in[7] = LSW(MSD(req_dma));
  655. mbcp->mbox_in[8] = MSW(addr);
  656. status = ql_mailbox_command(qdev, mbcp);
  657. if (status)
  658. return status;
  659. if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
  660. netif_err(qdev, drv, qdev->ndev, "Failed to dump risc RAM.\n");
  661. status = -EIO;
  662. }
  663. return status;
  664. }
  665. /* Issue a mailbox command to dump RISC RAM. */
  666. int ql_dump_risc_ram_area(struct ql_adapter *qdev, void *buf,
  667. u32 ram_addr, int word_count)
  668. {
  669. int status;
  670. char *my_buf;
  671. dma_addr_t buf_dma;
  672. my_buf = pci_alloc_consistent(qdev->pdev, word_count * sizeof(u32),
  673. &buf_dma);
  674. if (!my_buf)
  675. return -EIO;
  676. status = ql_mb_dump_ram(qdev, buf_dma, ram_addr, word_count);
  677. if (!status)
  678. memcpy(buf, my_buf, word_count * sizeof(u32));
  679. pci_free_consistent(qdev->pdev, word_count * sizeof(u32), my_buf,
  680. buf_dma);
  681. return status;
  682. }
  683. /* Get link settings and maximum frame size settings
  684. * for the current port.
  685. * Most likely will block.
  686. */
  687. int ql_mb_get_port_cfg(struct ql_adapter *qdev)
  688. {
  689. struct mbox_params mbc;
  690. struct mbox_params *mbcp = &mbc;
  691. int status = 0;
  692. memset(mbcp, 0, sizeof(struct mbox_params));
  693. mbcp->in_count = 1;
  694. mbcp->out_count = 3;
  695. mbcp->mbox_in[0] = MB_CMD_GET_PORT_CFG;
  696. status = ql_mailbox_command(qdev, mbcp);
  697. if (status)
  698. return status;
  699. if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
  700. netif_err(qdev, drv, qdev->ndev,
  701. "Failed Get Port Configuration.\n");
  702. status = -EIO;
  703. } else {
  704. netif_printk(qdev, drv, KERN_DEBUG, qdev->ndev,
  705. "Passed Get Port Configuration.\n");
  706. qdev->link_config = mbcp->mbox_out[1];
  707. qdev->max_frame_size = mbcp->mbox_out[2];
  708. }
  709. return status;
  710. }
  711. int ql_mb_wol_mode(struct ql_adapter *qdev, u32 wol)
  712. {
  713. struct mbox_params mbc;
  714. struct mbox_params *mbcp = &mbc;
  715. int status;
  716. memset(mbcp, 0, sizeof(struct mbox_params));
  717. mbcp->in_count = 2;
  718. mbcp->out_count = 1;
  719. mbcp->mbox_in[0] = MB_CMD_SET_WOL_MODE;
  720. mbcp->mbox_in[1] = wol;
  721. status = ql_mailbox_command(qdev, mbcp);
  722. if (status)
  723. return status;
  724. if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
  725. netif_err(qdev, drv, qdev->ndev, "Failed to set WOL mode.\n");
  726. status = -EIO;
  727. }
  728. return status;
  729. }
  730. int ql_mb_wol_set_magic(struct ql_adapter *qdev, u32 enable_wol)
  731. {
  732. struct mbox_params mbc;
  733. struct mbox_params *mbcp = &mbc;
  734. int status;
  735. u8 *addr = qdev->ndev->dev_addr;
  736. memset(mbcp, 0, sizeof(struct mbox_params));
  737. mbcp->in_count = 8;
  738. mbcp->out_count = 1;
  739. mbcp->mbox_in[0] = MB_CMD_SET_WOL_MAGIC;
  740. if (enable_wol) {
  741. mbcp->mbox_in[1] = (u32)addr[0];
  742. mbcp->mbox_in[2] = (u32)addr[1];
  743. mbcp->mbox_in[3] = (u32)addr[2];
  744. mbcp->mbox_in[4] = (u32)addr[3];
  745. mbcp->mbox_in[5] = (u32)addr[4];
  746. mbcp->mbox_in[6] = (u32)addr[5];
  747. mbcp->mbox_in[7] = 0;
  748. } else {
  749. mbcp->mbox_in[1] = 0;
  750. mbcp->mbox_in[2] = 1;
  751. mbcp->mbox_in[3] = 1;
  752. mbcp->mbox_in[4] = 1;
  753. mbcp->mbox_in[5] = 1;
  754. mbcp->mbox_in[6] = 1;
  755. mbcp->mbox_in[7] = 0;
  756. }
  757. status = ql_mailbox_command(qdev, mbcp);
  758. if (status)
  759. return status;
  760. if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
  761. netif_err(qdev, drv, qdev->ndev, "Failed to set WOL mode.\n");
  762. status = -EIO;
  763. }
  764. return status;
  765. }
  766. /* IDC - Inter Device Communication...
  767. * Some firmware commands require consent of adjacent FCOE
  768. * function. This function waits for the OK, or a
  769. * counter-request for a little more time.i
  770. * The firmware will complete the request if the other
  771. * function doesn't respond.
  772. */
  773. static int ql_idc_wait(struct ql_adapter *qdev)
  774. {
  775. int status = -ETIMEDOUT;
  776. long wait_time = 1 * HZ;
  777. struct mbox_params *mbcp = &qdev->idc_mbc;
  778. do {
  779. /* Wait here for the command to complete
  780. * via the IDC process.
  781. */
  782. wait_time =
  783. wait_for_completion_timeout(&qdev->ide_completion,
  784. wait_time);
  785. if (!wait_time) {
  786. netif_err(qdev, drv, qdev->ndev, "IDC Timeout.\n");
  787. break;
  788. }
  789. /* Now examine the response from the IDC process.
  790. * We might have a good completion or a request for
  791. * more wait time.
  792. */
  793. if (mbcp->mbox_out[0] == AEN_IDC_EXT) {
  794. netif_err(qdev, drv, qdev->ndev,
  795. "IDC Time Extension from function.\n");
  796. wait_time += (mbcp->mbox_out[1] >> 8) & 0x0000000f;
  797. } else if (mbcp->mbox_out[0] == AEN_IDC_CMPLT) {
  798. netif_err(qdev, drv, qdev->ndev, "IDC Success.\n");
  799. status = 0;
  800. break;
  801. } else {
  802. netif_err(qdev, drv, qdev->ndev,
  803. "IDC: Invalid State 0x%.04x.\n",
  804. mbcp->mbox_out[0]);
  805. status = -EIO;
  806. break;
  807. }
  808. } while (wait_time);
  809. return status;
  810. }
  811. int ql_mb_set_led_cfg(struct ql_adapter *qdev, u32 led_config)
  812. {
  813. struct mbox_params mbc;
  814. struct mbox_params *mbcp = &mbc;
  815. int status;
  816. memset(mbcp, 0, sizeof(struct mbox_params));
  817. mbcp->in_count = 2;
  818. mbcp->out_count = 1;
  819. mbcp->mbox_in[0] = MB_CMD_SET_LED_CFG;
  820. mbcp->mbox_in[1] = led_config;
  821. status = ql_mailbox_command(qdev, mbcp);
  822. if (status)
  823. return status;
  824. if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
  825. netif_err(qdev, drv, qdev->ndev,
  826. "Failed to set LED Configuration.\n");
  827. status = -EIO;
  828. }
  829. return status;
  830. }
  831. int ql_mb_get_led_cfg(struct ql_adapter *qdev)
  832. {
  833. struct mbox_params mbc;
  834. struct mbox_params *mbcp = &mbc;
  835. int status;
  836. memset(mbcp, 0, sizeof(struct mbox_params));
  837. mbcp->in_count = 1;
  838. mbcp->out_count = 2;
  839. mbcp->mbox_in[0] = MB_CMD_GET_LED_CFG;
  840. status = ql_mailbox_command(qdev, mbcp);
  841. if (status)
  842. return status;
  843. if (mbcp->mbox_out[0] != MB_CMD_STS_GOOD) {
  844. netif_err(qdev, drv, qdev->ndev,
  845. "Failed to get LED Configuration.\n");
  846. status = -EIO;
  847. } else
  848. qdev->led_config = mbcp->mbox_out[1];
  849. return status;
  850. }
  851. int ql_mb_set_mgmnt_traffic_ctl(struct ql_adapter *qdev, u32 control)
  852. {
  853. struct mbox_params mbc;
  854. struct mbox_params *mbcp = &mbc;
  855. int status;
  856. memset(mbcp, 0, sizeof(struct mbox_params));
  857. mbcp->in_count = 1;
  858. mbcp->out_count = 2;
  859. mbcp->mbox_in[0] = MB_CMD_SET_MGMNT_TFK_CTL;
  860. mbcp->mbox_in[1] = control;
  861. status = ql_mailbox_command(qdev, mbcp);
  862. if (status)
  863. return status;
  864. if (mbcp->mbox_out[0] == MB_CMD_STS_GOOD)
  865. return status;
  866. if (mbcp->mbox_out[0] == MB_CMD_STS_INVLD_CMD) {
  867. netif_err(qdev, drv, qdev->ndev,
  868. "Command not supported by firmware.\n");
  869. status = -EINVAL;
  870. } else if (mbcp->mbox_out[0] == MB_CMD_STS_ERR) {
  871. /* This indicates that the firmware is
  872. * already in the state we are trying to
  873. * change it to.
  874. */
  875. netif_err(qdev, drv, qdev->ndev,
  876. "Command parameters make no change.\n");
  877. }
  878. return status;
  879. }
  880. /* Returns a negative error code or the mailbox command status. */
  881. static int ql_mb_get_mgmnt_traffic_ctl(struct ql_adapter *qdev, u32 *control)
  882. {
  883. struct mbox_params mbc;
  884. struct mbox_params *mbcp = &mbc;
  885. int status;
  886. memset(mbcp, 0, sizeof(struct mbox_params));
  887. *control = 0;
  888. mbcp->in_count = 1;
  889. mbcp->out_count = 1;
  890. mbcp->mbox_in[0] = MB_CMD_GET_MGMNT_TFK_CTL;
  891. status = ql_mailbox_command(qdev, mbcp);
  892. if (status)
  893. return status;
  894. if (mbcp->mbox_out[0] == MB_CMD_STS_GOOD) {
  895. *control = mbcp->mbox_in[1];
  896. return status;
  897. }
  898. if (mbcp->mbox_out[0] == MB_CMD_STS_INVLD_CMD) {
  899. netif_err(qdev, drv, qdev->ndev,
  900. "Command not supported by firmware.\n");
  901. status = -EINVAL;
  902. } else if (mbcp->mbox_out[0] == MB_CMD_STS_ERR) {
  903. netif_err(qdev, drv, qdev->ndev,
  904. "Failed to get MPI traffic control.\n");
  905. status = -EIO;
  906. }
  907. return status;
  908. }
  909. int ql_wait_fifo_empty(struct ql_adapter *qdev)
  910. {
  911. int count = 5;
  912. u32 mgmnt_fifo_empty;
  913. u32 nic_fifo_empty;
  914. do {
  915. nic_fifo_empty = ql_read32(qdev, STS) & STS_NFE;
  916. ql_mb_get_mgmnt_traffic_ctl(qdev, &mgmnt_fifo_empty);
  917. mgmnt_fifo_empty &= MB_GET_MPI_TFK_FIFO_EMPTY;
  918. if (nic_fifo_empty && mgmnt_fifo_empty)
  919. return 0;
  920. msleep(100);
  921. } while (count-- > 0);
  922. return -ETIMEDOUT;
  923. }
  924. /* API called in work thread context to set new TX/RX
  925. * maximum frame size values to match MTU.
  926. */
  927. static int ql_set_port_cfg(struct ql_adapter *qdev)
  928. {
  929. int status;
  930. status = ql_mb_set_port_cfg(qdev);
  931. if (status)
  932. return status;
  933. status = ql_idc_wait(qdev);
  934. return status;
  935. }
  936. /* The following routines are worker threads that process
  937. * events that may sleep waiting for completion.
  938. */
  939. /* This thread gets the maximum TX and RX frame size values
  940. * from the firmware and, if necessary, changes them to match
  941. * the MTU setting.
  942. */
  943. void ql_mpi_port_cfg_work(struct work_struct *work)
  944. {
  945. struct ql_adapter *qdev =
  946. container_of(work, struct ql_adapter, mpi_port_cfg_work.work);
  947. int status;
  948. status = ql_mb_get_port_cfg(qdev);
  949. if (status) {
  950. netif_err(qdev, drv, qdev->ndev,
  951. "Bug: Failed to get port config data.\n");
  952. goto err;
  953. }
  954. if (qdev->link_config & CFG_JUMBO_FRAME_SIZE &&
  955. qdev->max_frame_size ==
  956. CFG_DEFAULT_MAX_FRAME_SIZE)
  957. goto end;
  958. qdev->link_config |= CFG_JUMBO_FRAME_SIZE;
  959. qdev->max_frame_size = CFG_DEFAULT_MAX_FRAME_SIZE;
  960. status = ql_set_port_cfg(qdev);
  961. if (status) {
  962. netif_err(qdev, drv, qdev->ndev,
  963. "Bug: Failed to set port config data.\n");
  964. goto err;
  965. }
  966. end:
  967. clear_bit(QL_PORT_CFG, &qdev->flags);
  968. return;
  969. err:
  970. ql_queue_fw_error(qdev);
  971. goto end;
  972. }
  973. /* Process an inter-device request. This is issues by
  974. * the firmware in response to another function requesting
  975. * a change to the port. We set a flag to indicate a change
  976. * has been made and then send a mailbox command ACKing
  977. * the change request.
  978. */
  979. void ql_mpi_idc_work(struct work_struct *work)
  980. {
  981. struct ql_adapter *qdev =
  982. container_of(work, struct ql_adapter, mpi_idc_work.work);
  983. int status;
  984. struct mbox_params *mbcp = &qdev->idc_mbc;
  985. u32 aen;
  986. int timeout;
  987. aen = mbcp->mbox_out[1] >> 16;
  988. timeout = (mbcp->mbox_out[1] >> 8) & 0xf;
  989. switch (aen) {
  990. default:
  991. netif_err(qdev, drv, qdev->ndev,
  992. "Bug: Unhandled IDC action.\n");
  993. break;
  994. case MB_CMD_PORT_RESET:
  995. case MB_CMD_STOP_FW:
  996. ql_link_off(qdev);
  997. case MB_CMD_SET_PORT_CFG:
  998. /* Signal the resulting link up AEN
  999. * that the frame routing and mac addr
  1000. * needs to be set.
  1001. * */
  1002. set_bit(QL_CAM_RT_SET, &qdev->flags);
  1003. /* Do ACK if required */
  1004. if (timeout) {
  1005. status = ql_mb_idc_ack(qdev);
  1006. if (status)
  1007. netif_err(qdev, drv, qdev->ndev,
  1008. "Bug: No pending IDC!\n");
  1009. } else {
  1010. netif_printk(qdev, drv, KERN_DEBUG, qdev->ndev,
  1011. "IDC ACK not required\n");
  1012. status = 0; /* success */
  1013. }
  1014. break;
  1015. /* These sub-commands issued by another (FCoE)
  1016. * function are requesting to do an operation
  1017. * on the shared resource (MPI environment).
  1018. * We currently don't issue these so we just
  1019. * ACK the request.
  1020. */
  1021. case MB_CMD_IOP_RESTART_MPI:
  1022. case MB_CMD_IOP_PREP_LINK_DOWN:
  1023. /* Drop the link, reload the routing
  1024. * table when link comes up.
  1025. */
  1026. ql_link_off(qdev);
  1027. set_bit(QL_CAM_RT_SET, &qdev->flags);
  1028. /* Fall through. */
  1029. case MB_CMD_IOP_DVR_START:
  1030. case MB_CMD_IOP_FLASH_ACC:
  1031. case MB_CMD_IOP_CORE_DUMP_MPI:
  1032. case MB_CMD_IOP_PREP_UPDATE_MPI:
  1033. case MB_CMD_IOP_COMP_UPDATE_MPI:
  1034. case MB_CMD_IOP_NONE: /* an IDC without params */
  1035. /* Do ACK if required */
  1036. if (timeout) {
  1037. status = ql_mb_idc_ack(qdev);
  1038. if (status)
  1039. netif_err(qdev, drv, qdev->ndev,
  1040. "Bug: No pending IDC!\n");
  1041. } else {
  1042. netif_printk(qdev, drv, KERN_DEBUG, qdev->ndev,
  1043. "IDC ACK not required\n");
  1044. status = 0; /* success */
  1045. }
  1046. break;
  1047. }
  1048. }
  1049. void ql_mpi_work(struct work_struct *work)
  1050. {
  1051. struct ql_adapter *qdev =
  1052. container_of(work, struct ql_adapter, mpi_work.work);
  1053. struct mbox_params mbc;
  1054. struct mbox_params *mbcp = &mbc;
  1055. int err = 0;
  1056. mutex_lock(&qdev->mpi_mutex);
  1057. /* Begin polled mode for MPI */
  1058. ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));
  1059. while (ql_read32(qdev, STS) & STS_PI) {
  1060. memset(mbcp, 0, sizeof(struct mbox_params));
  1061. mbcp->out_count = 1;
  1062. /* Don't continue if an async event
  1063. * did not complete properly.
  1064. */
  1065. err = ql_mpi_handler(qdev, mbcp);
  1066. if (err)
  1067. break;
  1068. }
  1069. /* End polled mode for MPI */
  1070. ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
  1071. mutex_unlock(&qdev->mpi_mutex);
  1072. ql_enable_completion_interrupt(qdev, 0);
  1073. }
  1074. void ql_mpi_reset_work(struct work_struct *work)
  1075. {
  1076. struct ql_adapter *qdev =
  1077. container_of(work, struct ql_adapter, mpi_reset_work.work);
  1078. cancel_delayed_work_sync(&qdev->mpi_work);
  1079. cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
  1080. cancel_delayed_work_sync(&qdev->mpi_idc_work);
  1081. /* If we're not the dominant NIC function,
  1082. * then there is nothing to do.
  1083. */
  1084. if (!ql_own_firmware(qdev)) {
  1085. netif_err(qdev, drv, qdev->ndev, "Don't own firmware!\n");
  1086. return;
  1087. }
  1088. if (!ql_core_dump(qdev, qdev->mpi_coredump)) {
  1089. netif_err(qdev, drv, qdev->ndev, "Core is dumped!\n");
  1090. qdev->core_is_dumped = 1;
  1091. queue_delayed_work(qdev->workqueue,
  1092. &qdev->mpi_core_to_log, 5 * HZ);
  1093. }
  1094. ql_soft_reset_mpi_risc(qdev);
  1095. }