national.c 4.1 KB

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  1. /*
  2. * drivers/net/phy/national.c
  3. *
  4. * Driver for National Semiconductor PHYs
  5. *
  6. * Author: Stuart Menefy <stuart.menefy@st.com>
  7. * Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  8. *
  9. * Copyright (c) 2008 STMicroelectronics Limited
  10. *
  11. * This program is free software; you can redistribute it and/or modify it
  12. * under the terms of the GNU General Public License as published by the
  13. * Free Software Foundation; either version 2 of the License, or (at your
  14. * option) any later version.
  15. *
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/mii.h>
  20. #include <linux/ethtool.h>
  21. #include <linux/phy.h>
  22. #include <linux/netdevice.h>
  23. /* DP83865 phy identifier values */
  24. #define DP83865_PHY_ID 0x20005c7a
  25. #define DP83865_INT_MASK_REG 0x15
  26. #define DP83865_INT_MASK_STATUS 0x14
  27. #define DP83865_INT_REMOTE_FAULT 0x0008
  28. #define DP83865_INT_ANE_COMPLETED 0x0010
  29. #define DP83865_INT_LINK_CHANGE 0xe000
  30. #define DP83865_INT_MASK_DEFAULT (DP83865_INT_REMOTE_FAULT | \
  31. DP83865_INT_ANE_COMPLETED | \
  32. DP83865_INT_LINK_CHANGE)
  33. /* Advanced proprietary configuration */
  34. #define NS_EXP_MEM_CTL 0x16
  35. #define NS_EXP_MEM_DATA 0x1d
  36. #define NS_EXP_MEM_ADD 0x1e
  37. #define LED_CTRL_REG 0x13
  38. #define AN_FALLBACK_AN 0x0001
  39. #define AN_FALLBACK_CRC 0x0002
  40. #define AN_FALLBACK_IE 0x0004
  41. #define ALL_FALLBACK_ON (AN_FALLBACK_AN | AN_FALLBACK_CRC | AN_FALLBACK_IE)
  42. enum hdx_loopback {
  43. hdx_loopback_on = 0,
  44. hdx_loopback_off = 1,
  45. };
  46. static u8 ns_exp_read(struct phy_device *phydev, u16 reg)
  47. {
  48. phy_write(phydev, NS_EXP_MEM_ADD, reg);
  49. return phy_read(phydev, NS_EXP_MEM_DATA);
  50. }
  51. static void ns_exp_write(struct phy_device *phydev, u16 reg, u8 data)
  52. {
  53. phy_write(phydev, NS_EXP_MEM_ADD, reg);
  54. phy_write(phydev, NS_EXP_MEM_DATA, data);
  55. }
  56. static int ns_config_intr(struct phy_device *phydev)
  57. {
  58. int err;
  59. if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  60. err = phy_write(phydev, DP83865_INT_MASK_REG,
  61. DP83865_INT_MASK_DEFAULT);
  62. else
  63. err = phy_write(phydev, DP83865_INT_MASK_REG, 0);
  64. return err;
  65. }
  66. static int ns_ack_interrupt(struct phy_device *phydev)
  67. {
  68. int ret = phy_read(phydev, DP83865_INT_MASK_STATUS);
  69. if (ret < 0)
  70. return ret;
  71. return 0;
  72. }
  73. static void ns_giga_speed_fallback(struct phy_device *phydev, int mode)
  74. {
  75. int bmcr = phy_read(phydev, MII_BMCR);
  76. phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN));
  77. /* Enable 8 bit expended memory read/write (no auto increment) */
  78. phy_write(phydev, NS_EXP_MEM_CTL, 0);
  79. phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0);
  80. phy_write(phydev, NS_EXP_MEM_DATA, 0x0008);
  81. phy_write(phydev, MII_BMCR, (bmcr & ~BMCR_PDOWN));
  82. phy_write(phydev, LED_CTRL_REG, mode);
  83. }
  84. static void ns_10_base_t_hdx_loopack(struct phy_device *phydev, int disable)
  85. {
  86. if (disable)
  87. ns_exp_write(phydev, 0x1c0, ns_exp_read(phydev, 0x1c0) | 1);
  88. else
  89. ns_exp_write(phydev, 0x1c0,
  90. ns_exp_read(phydev, 0x1c0) & 0xfffe);
  91. printk(KERN_DEBUG "DP83865 PHY: 10BASE-T HDX loopback %s\n",
  92. (ns_exp_read(phydev, 0x1c0) & 0x0001) ? "off" : "on");
  93. }
  94. static int ns_config_init(struct phy_device *phydev)
  95. {
  96. ns_giga_speed_fallback(phydev, ALL_FALLBACK_ON);
  97. /* In the latest MAC or switches design, the 10 Mbps loopback
  98. is desired to be turned off. */
  99. ns_10_base_t_hdx_loopack(phydev, hdx_loopback_off);
  100. return ns_ack_interrupt(phydev);
  101. }
  102. static struct phy_driver dp83865_driver = {
  103. .phy_id = DP83865_PHY_ID,
  104. .phy_id_mask = 0xfffffff0,
  105. .name = "NatSemi DP83865",
  106. .features = PHY_GBIT_FEATURES | SUPPORTED_Pause | SUPPORTED_Asym_Pause,
  107. .flags = PHY_HAS_INTERRUPT,
  108. .config_init = ns_config_init,
  109. .config_aneg = genphy_config_aneg,
  110. .read_status = genphy_read_status,
  111. .ack_interrupt = ns_ack_interrupt,
  112. .config_intr = ns_config_intr,
  113. .driver = {.owner = THIS_MODULE,}
  114. };
  115. static int __init ns_init(void)
  116. {
  117. return phy_driver_register(&dp83865_driver);
  118. }
  119. static void __exit ns_exit(void)
  120. {
  121. phy_driver_unregister(&dp83865_driver);
  122. }
  123. MODULE_DESCRIPTION("NatSemi PHY driver");
  124. MODULE_AUTHOR("Stuart Menefy");
  125. MODULE_LICENSE("GPL");
  126. module_init(ns_init);
  127. module_exit(ns_exit);
  128. static struct mdio_device_id __maybe_unused ns_tbl[] = {
  129. { DP83865_PHY_ID, 0xfffffff0 },
  130. { }
  131. };
  132. MODULE_DEVICE_TABLE(mdio, ns_tbl);