netxen_nic_init.c 45 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896
  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * Copyright (C) 2009 - QLogic Corporation.
  4. * All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  19. * MA 02111-1307, USA.
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called "COPYING".
  23. *
  24. */
  25. #include <linux/netdevice.h>
  26. #include <linux/delay.h>
  27. #include <linux/slab.h>
  28. #include "netxen_nic.h"
  29. #include "netxen_nic_hw.h"
  30. struct crb_addr_pair {
  31. u32 addr;
  32. u32 data;
  33. };
  34. #define NETXEN_MAX_CRB_XFORM 60
  35. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  36. #define NETXEN_ADDR_ERROR (0xffffffff)
  37. #define crb_addr_transform(name) \
  38. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  39. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  40. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  41. static void
  42. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  43. struct nx_host_rds_ring *rds_ring);
  44. static int netxen_p3_has_mn(struct netxen_adapter *adapter);
  45. static void crb_addr_transform_setup(void)
  46. {
  47. crb_addr_transform(XDMA);
  48. crb_addr_transform(TIMR);
  49. crb_addr_transform(SRE);
  50. crb_addr_transform(SQN3);
  51. crb_addr_transform(SQN2);
  52. crb_addr_transform(SQN1);
  53. crb_addr_transform(SQN0);
  54. crb_addr_transform(SQS3);
  55. crb_addr_transform(SQS2);
  56. crb_addr_transform(SQS1);
  57. crb_addr_transform(SQS0);
  58. crb_addr_transform(RPMX7);
  59. crb_addr_transform(RPMX6);
  60. crb_addr_transform(RPMX5);
  61. crb_addr_transform(RPMX4);
  62. crb_addr_transform(RPMX3);
  63. crb_addr_transform(RPMX2);
  64. crb_addr_transform(RPMX1);
  65. crb_addr_transform(RPMX0);
  66. crb_addr_transform(ROMUSB);
  67. crb_addr_transform(SN);
  68. crb_addr_transform(QMN);
  69. crb_addr_transform(QMS);
  70. crb_addr_transform(PGNI);
  71. crb_addr_transform(PGND);
  72. crb_addr_transform(PGN3);
  73. crb_addr_transform(PGN2);
  74. crb_addr_transform(PGN1);
  75. crb_addr_transform(PGN0);
  76. crb_addr_transform(PGSI);
  77. crb_addr_transform(PGSD);
  78. crb_addr_transform(PGS3);
  79. crb_addr_transform(PGS2);
  80. crb_addr_transform(PGS1);
  81. crb_addr_transform(PGS0);
  82. crb_addr_transform(PS);
  83. crb_addr_transform(PH);
  84. crb_addr_transform(NIU);
  85. crb_addr_transform(I2Q);
  86. crb_addr_transform(EG);
  87. crb_addr_transform(MN);
  88. crb_addr_transform(MS);
  89. crb_addr_transform(CAS2);
  90. crb_addr_transform(CAS1);
  91. crb_addr_transform(CAS0);
  92. crb_addr_transform(CAM);
  93. crb_addr_transform(C2C1);
  94. crb_addr_transform(C2C0);
  95. crb_addr_transform(SMB);
  96. crb_addr_transform(OCM0);
  97. crb_addr_transform(I2C0);
  98. }
  99. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  100. {
  101. struct netxen_recv_context *recv_ctx;
  102. struct nx_host_rds_ring *rds_ring;
  103. struct netxen_rx_buffer *rx_buf;
  104. int i, ring;
  105. recv_ctx = &adapter->recv_ctx;
  106. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  107. rds_ring = &recv_ctx->rds_rings[ring];
  108. for (i = 0; i < rds_ring->num_desc; ++i) {
  109. rx_buf = &(rds_ring->rx_buf_arr[i]);
  110. if (rx_buf->state == NETXEN_BUFFER_FREE)
  111. continue;
  112. pci_unmap_single(adapter->pdev,
  113. rx_buf->dma,
  114. rds_ring->dma_size,
  115. PCI_DMA_FROMDEVICE);
  116. if (rx_buf->skb != NULL)
  117. dev_kfree_skb_any(rx_buf->skb);
  118. }
  119. }
  120. }
  121. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  122. {
  123. struct netxen_cmd_buffer *cmd_buf;
  124. struct netxen_skb_frag *buffrag;
  125. int i, j;
  126. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  127. cmd_buf = tx_ring->cmd_buf_arr;
  128. for (i = 0; i < tx_ring->num_desc; i++) {
  129. buffrag = cmd_buf->frag_array;
  130. if (buffrag->dma) {
  131. pci_unmap_single(adapter->pdev, buffrag->dma,
  132. buffrag->length, PCI_DMA_TODEVICE);
  133. buffrag->dma = 0ULL;
  134. }
  135. for (j = 0; j < cmd_buf->frag_count; j++) {
  136. buffrag++;
  137. if (buffrag->dma) {
  138. pci_unmap_page(adapter->pdev, buffrag->dma,
  139. buffrag->length,
  140. PCI_DMA_TODEVICE);
  141. buffrag->dma = 0ULL;
  142. }
  143. }
  144. if (cmd_buf->skb) {
  145. dev_kfree_skb_any(cmd_buf->skb);
  146. cmd_buf->skb = NULL;
  147. }
  148. cmd_buf++;
  149. }
  150. }
  151. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  152. {
  153. struct netxen_recv_context *recv_ctx;
  154. struct nx_host_rds_ring *rds_ring;
  155. struct nx_host_tx_ring *tx_ring;
  156. int ring;
  157. recv_ctx = &adapter->recv_ctx;
  158. if (recv_ctx->rds_rings == NULL)
  159. goto skip_rds;
  160. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  161. rds_ring = &recv_ctx->rds_rings[ring];
  162. vfree(rds_ring->rx_buf_arr);
  163. rds_ring->rx_buf_arr = NULL;
  164. }
  165. kfree(recv_ctx->rds_rings);
  166. skip_rds:
  167. if (adapter->tx_ring == NULL)
  168. return;
  169. tx_ring = adapter->tx_ring;
  170. vfree(tx_ring->cmd_buf_arr);
  171. kfree(tx_ring);
  172. adapter->tx_ring = NULL;
  173. }
  174. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  175. {
  176. struct netxen_recv_context *recv_ctx;
  177. struct nx_host_rds_ring *rds_ring;
  178. struct nx_host_sds_ring *sds_ring;
  179. struct nx_host_tx_ring *tx_ring;
  180. struct netxen_rx_buffer *rx_buf;
  181. int ring, i, size;
  182. struct netxen_cmd_buffer *cmd_buf_arr;
  183. struct net_device *netdev = adapter->netdev;
  184. struct pci_dev *pdev = adapter->pdev;
  185. size = sizeof(struct nx_host_tx_ring);
  186. tx_ring = kzalloc(size, GFP_KERNEL);
  187. if (tx_ring == NULL) {
  188. dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
  189. netdev->name);
  190. return -ENOMEM;
  191. }
  192. adapter->tx_ring = tx_ring;
  193. tx_ring->num_desc = adapter->num_txd;
  194. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  195. cmd_buf_arr = vzalloc(TX_BUFF_RINGSIZE(tx_ring));
  196. if (cmd_buf_arr == NULL) {
  197. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  198. netdev->name);
  199. goto err_out;
  200. }
  201. tx_ring->cmd_buf_arr = cmd_buf_arr;
  202. recv_ctx = &adapter->recv_ctx;
  203. size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
  204. rds_ring = kzalloc(size, GFP_KERNEL);
  205. if (rds_ring == NULL) {
  206. dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
  207. netdev->name);
  208. goto err_out;
  209. }
  210. recv_ctx->rds_rings = rds_ring;
  211. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  212. rds_ring = &recv_ctx->rds_rings[ring];
  213. switch (ring) {
  214. case RCV_RING_NORMAL:
  215. rds_ring->num_desc = adapter->num_rxd;
  216. if (adapter->ahw.cut_through) {
  217. rds_ring->dma_size =
  218. NX_CT_DEFAULT_RX_BUF_LEN;
  219. rds_ring->skb_size =
  220. NX_CT_DEFAULT_RX_BUF_LEN;
  221. } else {
  222. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  223. rds_ring->dma_size =
  224. NX_P3_RX_BUF_MAX_LEN;
  225. else
  226. rds_ring->dma_size =
  227. NX_P2_RX_BUF_MAX_LEN;
  228. rds_ring->skb_size =
  229. rds_ring->dma_size + NET_IP_ALIGN;
  230. }
  231. break;
  232. case RCV_RING_JUMBO:
  233. rds_ring->num_desc = adapter->num_jumbo_rxd;
  234. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  235. rds_ring->dma_size =
  236. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  237. else
  238. rds_ring->dma_size =
  239. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  240. if (adapter->capabilities & NX_CAP0_HW_LRO)
  241. rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
  242. rds_ring->skb_size =
  243. rds_ring->dma_size + NET_IP_ALIGN;
  244. break;
  245. case RCV_RING_LRO:
  246. rds_ring->num_desc = adapter->num_lro_rxd;
  247. rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
  248. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  249. break;
  250. }
  251. rds_ring->rx_buf_arr = vzalloc(RCV_BUFF_RINGSIZE(rds_ring));
  252. if (rds_ring->rx_buf_arr == NULL) {
  253. printk(KERN_ERR "%s: Failed to allocate "
  254. "rx buffer ring %d\n",
  255. netdev->name, ring);
  256. /* free whatever was already allocated */
  257. goto err_out;
  258. }
  259. INIT_LIST_HEAD(&rds_ring->free_list);
  260. /*
  261. * Now go through all of them, set reference handles
  262. * and put them in the queues.
  263. */
  264. rx_buf = rds_ring->rx_buf_arr;
  265. for (i = 0; i < rds_ring->num_desc; i++) {
  266. list_add_tail(&rx_buf->list,
  267. &rds_ring->free_list);
  268. rx_buf->ref_handle = i;
  269. rx_buf->state = NETXEN_BUFFER_FREE;
  270. rx_buf++;
  271. }
  272. spin_lock_init(&rds_ring->lock);
  273. }
  274. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  275. sds_ring = &recv_ctx->sds_rings[ring];
  276. sds_ring->irq = adapter->msix_entries[ring].vector;
  277. sds_ring->adapter = adapter;
  278. sds_ring->num_desc = adapter->num_rxd;
  279. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  280. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  281. }
  282. return 0;
  283. err_out:
  284. netxen_free_sw_resources(adapter);
  285. return -ENOMEM;
  286. }
  287. /*
  288. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  289. * address to external PCI CRB address.
  290. */
  291. static u32 netxen_decode_crb_addr(u32 addr)
  292. {
  293. int i;
  294. u32 base_addr, offset, pci_base;
  295. crb_addr_transform_setup();
  296. pci_base = NETXEN_ADDR_ERROR;
  297. base_addr = addr & 0xfff00000;
  298. offset = addr & 0x000fffff;
  299. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  300. if (crb_addr_xform[i] == base_addr) {
  301. pci_base = i << 20;
  302. break;
  303. }
  304. }
  305. if (pci_base == NETXEN_ADDR_ERROR)
  306. return pci_base;
  307. else
  308. return pci_base + offset;
  309. }
  310. #define NETXEN_MAX_ROM_WAIT_USEC 100
  311. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  312. {
  313. long timeout = 0;
  314. long done = 0;
  315. cond_resched();
  316. while (done == 0) {
  317. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  318. done &= 2;
  319. if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
  320. dev_err(&adapter->pdev->dev,
  321. "Timeout reached waiting for rom done");
  322. return -EIO;
  323. }
  324. udelay(1);
  325. }
  326. return 0;
  327. }
  328. static int do_rom_fast_read(struct netxen_adapter *adapter,
  329. int addr, int *valp)
  330. {
  331. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  332. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  333. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  334. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  335. if (netxen_wait_rom_done(adapter)) {
  336. printk("Error waiting for rom done\n");
  337. return -EIO;
  338. }
  339. /* reset abyte_cnt and dummy_byte_cnt */
  340. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  341. udelay(10);
  342. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  343. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  344. return 0;
  345. }
  346. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  347. u8 *bytes, size_t size)
  348. {
  349. int addridx;
  350. int ret = 0;
  351. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  352. int v;
  353. ret = do_rom_fast_read(adapter, addridx, &v);
  354. if (ret != 0)
  355. break;
  356. *(__le32 *)bytes = cpu_to_le32(v);
  357. bytes += 4;
  358. }
  359. return ret;
  360. }
  361. int
  362. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  363. u8 *bytes, size_t size)
  364. {
  365. int ret;
  366. ret = netxen_rom_lock(adapter);
  367. if (ret < 0)
  368. return ret;
  369. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  370. netxen_rom_unlock(adapter);
  371. return ret;
  372. }
  373. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  374. {
  375. int ret;
  376. if (netxen_rom_lock(adapter) != 0)
  377. return -EIO;
  378. ret = do_rom_fast_read(adapter, addr, valp);
  379. netxen_rom_unlock(adapter);
  380. return ret;
  381. }
  382. #define NETXEN_BOARDTYPE 0x4008
  383. #define NETXEN_BOARDNUM 0x400c
  384. #define NETXEN_CHIPNUM 0x4010
  385. int netxen_pinit_from_rom(struct netxen_adapter *adapter)
  386. {
  387. int addr, val;
  388. int i, n, init_delay = 0;
  389. struct crb_addr_pair *buf;
  390. unsigned offset;
  391. u32 off;
  392. /* resetall */
  393. netxen_rom_lock(adapter);
  394. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
  395. netxen_rom_unlock(adapter);
  396. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  397. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  398. (n != 0xcafecafe) ||
  399. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  400. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  401. "n: %08x\n", netxen_nic_driver_name, n);
  402. return -EIO;
  403. }
  404. offset = n & 0xffffU;
  405. n = (n >> 16) & 0xffffU;
  406. } else {
  407. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  408. !(n & 0x80000000)) {
  409. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  410. "n: %08x\n", netxen_nic_driver_name, n);
  411. return -EIO;
  412. }
  413. offset = 1;
  414. n &= ~0x80000000;
  415. }
  416. if (n >= 1024) {
  417. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  418. " initialized.\n", __func__, n);
  419. return -EIO;
  420. }
  421. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  422. if (buf == NULL) {
  423. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  424. netxen_nic_driver_name);
  425. return -ENOMEM;
  426. }
  427. for (i = 0; i < n; i++) {
  428. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  429. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  430. kfree(buf);
  431. return -EIO;
  432. }
  433. buf[i].addr = addr;
  434. buf[i].data = val;
  435. }
  436. for (i = 0; i < n; i++) {
  437. off = netxen_decode_crb_addr(buf[i].addr);
  438. if (off == NETXEN_ADDR_ERROR) {
  439. printk(KERN_ERR"CRB init value out of range %x\n",
  440. buf[i].addr);
  441. continue;
  442. }
  443. off += NETXEN_PCI_CRBSPACE;
  444. if (off & 1)
  445. continue;
  446. /* skipping cold reboot MAGIC */
  447. if (off == NETXEN_CAM_RAM(0x1fc))
  448. continue;
  449. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  450. if (off == (NETXEN_CRB_I2C0 + 0x1c))
  451. continue;
  452. /* do not reset PCI */
  453. if (off == (ROMUSB_GLB + 0xbc))
  454. continue;
  455. if (off == (ROMUSB_GLB + 0xa8))
  456. continue;
  457. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  458. continue;
  459. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  460. continue;
  461. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  462. continue;
  463. if ((off & 0x0ff00000) == NETXEN_CRB_DDR_NET)
  464. continue;
  465. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18) &&
  466. !NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  467. buf[i].data = 0x1020;
  468. /* skip the function enable register */
  469. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  470. continue;
  471. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  472. continue;
  473. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  474. continue;
  475. }
  476. init_delay = 1;
  477. /* After writing this register, HW needs time for CRB */
  478. /* to quiet down (else crb_window returns 0xffffffff) */
  479. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  480. init_delay = 1000;
  481. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  482. /* hold xdma in reset also */
  483. buf[i].data = NETXEN_NIC_XDMA_RESET;
  484. buf[i].data = 0x8000ff;
  485. }
  486. }
  487. NXWR32(adapter, off, buf[i].data);
  488. msleep(init_delay);
  489. }
  490. kfree(buf);
  491. /* disable_peg_cache_all */
  492. /* unreset_net_cache */
  493. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  494. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  495. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  496. }
  497. /* p2dn replyCount */
  498. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  499. /* disable_peg_cache 0 */
  500. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  501. /* disable_peg_cache 1 */
  502. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  503. /* peg_clr_all */
  504. /* peg_clr 0 */
  505. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  506. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  507. /* peg_clr 1 */
  508. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  509. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  510. /* peg_clr 2 */
  511. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  512. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  513. /* peg_clr 3 */
  514. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  515. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  516. return 0;
  517. }
  518. static struct uni_table_desc *nx_get_table_desc(const u8 *unirom, int section)
  519. {
  520. uint32_t i;
  521. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  522. __le32 entries = cpu_to_le32(directory->num_entries);
  523. for (i = 0; i < entries; i++) {
  524. __le32 offs = cpu_to_le32(directory->findex) +
  525. (i * cpu_to_le32(directory->entry_size));
  526. __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
  527. if (tab_type == section)
  528. return (struct uni_table_desc *) &unirom[offs];
  529. }
  530. return NULL;
  531. }
  532. #define QLCNIC_FILEHEADER_SIZE (14 * 4)
  533. static int
  534. netxen_nic_validate_header(struct netxen_adapter *adapter)
  535. {
  536. const u8 *unirom = adapter->fw->data;
  537. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  538. u32 fw_file_size = adapter->fw->size;
  539. u32 tab_size;
  540. __le32 entries;
  541. __le32 entry_size;
  542. if (fw_file_size < QLCNIC_FILEHEADER_SIZE)
  543. return -EINVAL;
  544. entries = cpu_to_le32(directory->num_entries);
  545. entry_size = cpu_to_le32(directory->entry_size);
  546. tab_size = cpu_to_le32(directory->findex) + (entries * entry_size);
  547. if (fw_file_size < tab_size)
  548. return -EINVAL;
  549. return 0;
  550. }
  551. static int
  552. netxen_nic_validate_bootld(struct netxen_adapter *adapter)
  553. {
  554. struct uni_table_desc *tab_desc;
  555. struct uni_data_desc *descr;
  556. const u8 *unirom = adapter->fw->data;
  557. __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  558. NX_UNI_BOOTLD_IDX_OFF));
  559. u32 offs;
  560. u32 tab_size;
  561. u32 data_size;
  562. tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_BOOTLD);
  563. if (!tab_desc)
  564. return -EINVAL;
  565. tab_size = cpu_to_le32(tab_desc->findex) +
  566. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  567. if (adapter->fw->size < tab_size)
  568. return -EINVAL;
  569. offs = cpu_to_le32(tab_desc->findex) +
  570. (cpu_to_le32(tab_desc->entry_size) * (idx));
  571. descr = (struct uni_data_desc *)&unirom[offs];
  572. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  573. if (adapter->fw->size < data_size)
  574. return -EINVAL;
  575. return 0;
  576. }
  577. static int
  578. netxen_nic_validate_fw(struct netxen_adapter *adapter)
  579. {
  580. struct uni_table_desc *tab_desc;
  581. struct uni_data_desc *descr;
  582. const u8 *unirom = adapter->fw->data;
  583. __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  584. NX_UNI_FIRMWARE_IDX_OFF));
  585. u32 offs;
  586. u32 tab_size;
  587. u32 data_size;
  588. tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_FW);
  589. if (!tab_desc)
  590. return -EINVAL;
  591. tab_size = cpu_to_le32(tab_desc->findex) +
  592. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  593. if (adapter->fw->size < tab_size)
  594. return -EINVAL;
  595. offs = cpu_to_le32(tab_desc->findex) +
  596. (cpu_to_le32(tab_desc->entry_size) * (idx));
  597. descr = (struct uni_data_desc *)&unirom[offs];
  598. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  599. if (adapter->fw->size < data_size)
  600. return -EINVAL;
  601. return 0;
  602. }
  603. static int
  604. netxen_nic_validate_product_offs(struct netxen_adapter *adapter)
  605. {
  606. struct uni_table_desc *ptab_descr;
  607. const u8 *unirom = adapter->fw->data;
  608. int mn_present = (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ?
  609. 1 : netxen_p3_has_mn(adapter);
  610. __le32 entries;
  611. __le32 entry_size;
  612. u32 tab_size;
  613. u32 i;
  614. ptab_descr = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_PRODUCT_TBL);
  615. if (ptab_descr == NULL)
  616. return -EINVAL;
  617. entries = cpu_to_le32(ptab_descr->num_entries);
  618. entry_size = cpu_to_le32(ptab_descr->entry_size);
  619. tab_size = cpu_to_le32(ptab_descr->findex) + (entries * entry_size);
  620. if (adapter->fw->size < tab_size)
  621. return -EINVAL;
  622. nomn:
  623. for (i = 0; i < entries; i++) {
  624. __le32 flags, file_chiprev, offs;
  625. u8 chiprev = adapter->ahw.revision_id;
  626. uint32_t flagbit;
  627. offs = cpu_to_le32(ptab_descr->findex) +
  628. (i * cpu_to_le32(ptab_descr->entry_size));
  629. flags = cpu_to_le32(*((int *)&unirom[offs] + NX_UNI_FLAGS_OFF));
  630. file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
  631. NX_UNI_CHIP_REV_OFF));
  632. flagbit = mn_present ? 1 : 2;
  633. if ((chiprev == file_chiprev) &&
  634. ((1ULL << flagbit) & flags)) {
  635. adapter->file_prd_off = offs;
  636. return 0;
  637. }
  638. }
  639. if (mn_present && NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  640. mn_present = 0;
  641. goto nomn;
  642. }
  643. return -EINVAL;
  644. }
  645. static int
  646. netxen_nic_validate_unified_romimage(struct netxen_adapter *adapter)
  647. {
  648. if (netxen_nic_validate_header(adapter)) {
  649. dev_err(&adapter->pdev->dev,
  650. "unified image: header validation failed\n");
  651. return -EINVAL;
  652. }
  653. if (netxen_nic_validate_product_offs(adapter)) {
  654. dev_err(&adapter->pdev->dev,
  655. "unified image: product validation failed\n");
  656. return -EINVAL;
  657. }
  658. if (netxen_nic_validate_bootld(adapter)) {
  659. dev_err(&adapter->pdev->dev,
  660. "unified image: bootld validation failed\n");
  661. return -EINVAL;
  662. }
  663. if (netxen_nic_validate_fw(adapter)) {
  664. dev_err(&adapter->pdev->dev,
  665. "unified image: firmware validation failed\n");
  666. return -EINVAL;
  667. }
  668. return 0;
  669. }
  670. static struct uni_data_desc *nx_get_data_desc(struct netxen_adapter *adapter,
  671. u32 section, u32 idx_offset)
  672. {
  673. const u8 *unirom = adapter->fw->data;
  674. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  675. idx_offset));
  676. struct uni_table_desc *tab_desc;
  677. __le32 offs;
  678. tab_desc = nx_get_table_desc(unirom, section);
  679. if (tab_desc == NULL)
  680. return NULL;
  681. offs = cpu_to_le32(tab_desc->findex) +
  682. (cpu_to_le32(tab_desc->entry_size) * idx);
  683. return (struct uni_data_desc *)&unirom[offs];
  684. }
  685. static u8 *
  686. nx_get_bootld_offs(struct netxen_adapter *adapter)
  687. {
  688. u32 offs = NETXEN_BOOTLD_START;
  689. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  690. offs = cpu_to_le32((nx_get_data_desc(adapter,
  691. NX_UNI_DIR_SECT_BOOTLD,
  692. NX_UNI_BOOTLD_IDX_OFF))->findex);
  693. return (u8 *)&adapter->fw->data[offs];
  694. }
  695. static u8 *
  696. nx_get_fw_offs(struct netxen_adapter *adapter)
  697. {
  698. u32 offs = NETXEN_IMAGE_START;
  699. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  700. offs = cpu_to_le32((nx_get_data_desc(adapter,
  701. NX_UNI_DIR_SECT_FW,
  702. NX_UNI_FIRMWARE_IDX_OFF))->findex);
  703. return (u8 *)&adapter->fw->data[offs];
  704. }
  705. static __le32
  706. nx_get_fw_size(struct netxen_adapter *adapter)
  707. {
  708. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  709. return cpu_to_le32((nx_get_data_desc(adapter,
  710. NX_UNI_DIR_SECT_FW,
  711. NX_UNI_FIRMWARE_IDX_OFF))->size);
  712. else
  713. return cpu_to_le32(
  714. *(u32 *)&adapter->fw->data[NX_FW_SIZE_OFFSET]);
  715. }
  716. static __le32
  717. nx_get_fw_version(struct netxen_adapter *adapter)
  718. {
  719. struct uni_data_desc *fw_data_desc;
  720. const struct firmware *fw = adapter->fw;
  721. __le32 major, minor, sub;
  722. const u8 *ver_str;
  723. int i, ret = 0;
  724. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  725. fw_data_desc = nx_get_data_desc(adapter,
  726. NX_UNI_DIR_SECT_FW, NX_UNI_FIRMWARE_IDX_OFF);
  727. ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
  728. cpu_to_le32(fw_data_desc->size) - 17;
  729. for (i = 0; i < 12; i++) {
  730. if (!strncmp(&ver_str[i], "REV=", 4)) {
  731. ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
  732. &major, &minor, &sub);
  733. break;
  734. }
  735. }
  736. if (ret != 3)
  737. return 0;
  738. return major + (minor << 8) + (sub << 16);
  739. } else
  740. return cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  741. }
  742. static __le32
  743. nx_get_bios_version(struct netxen_adapter *adapter)
  744. {
  745. const struct firmware *fw = adapter->fw;
  746. __le32 bios_ver, prd_off = adapter->file_prd_off;
  747. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  748. bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
  749. + NX_UNI_BIOS_VERSION_OFF));
  750. return (bios_ver << 16) + ((bios_ver >> 8) & 0xff00) +
  751. (bios_ver >> 24);
  752. } else
  753. return cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  754. }
  755. int
  756. netxen_need_fw_reset(struct netxen_adapter *adapter)
  757. {
  758. u32 count, old_count;
  759. u32 val, version, major, minor, build;
  760. int i, timeout;
  761. u8 fw_type;
  762. /* NX2031 firmware doesn't support heartbit */
  763. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  764. return 1;
  765. if (adapter->need_fw_reset)
  766. return 1;
  767. /* last attempt had failed */
  768. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  769. return 1;
  770. old_count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  771. for (i = 0; i < 10; i++) {
  772. timeout = msleep_interruptible(200);
  773. if (timeout) {
  774. NXWR32(adapter, CRB_CMDPEG_STATE,
  775. PHAN_INITIALIZE_FAILED);
  776. return -EINTR;
  777. }
  778. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  779. if (count != old_count)
  780. break;
  781. }
  782. /* firmware is dead */
  783. if (count == old_count)
  784. return 1;
  785. /* check if we have got newer or different file firmware */
  786. if (adapter->fw) {
  787. val = nx_get_fw_version(adapter);
  788. version = NETXEN_DECODE_VERSION(val);
  789. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  790. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  791. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  792. if (version > NETXEN_VERSION_CODE(major, minor, build))
  793. return 1;
  794. if (version == NETXEN_VERSION_CODE(major, minor, build) &&
  795. adapter->fw_type != NX_UNIFIED_ROMIMAGE) {
  796. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  797. fw_type = (val & 0x4) ?
  798. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  799. if (adapter->fw_type != fw_type)
  800. return 1;
  801. }
  802. }
  803. return 0;
  804. }
  805. static char *fw_name[] = {
  806. NX_P2_MN_ROMIMAGE_NAME,
  807. NX_P3_CT_ROMIMAGE_NAME,
  808. NX_P3_MN_ROMIMAGE_NAME,
  809. NX_UNIFIED_ROMIMAGE_NAME,
  810. NX_FLASH_ROMIMAGE_NAME,
  811. };
  812. int
  813. netxen_load_firmware(struct netxen_adapter *adapter)
  814. {
  815. u64 *ptr64;
  816. u32 i, flashaddr, size;
  817. const struct firmware *fw = adapter->fw;
  818. struct pci_dev *pdev = adapter->pdev;
  819. dev_info(&pdev->dev, "loading firmware from %s\n",
  820. fw_name[adapter->fw_type]);
  821. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  822. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  823. if (fw) {
  824. __le64 data;
  825. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  826. ptr64 = (u64 *)nx_get_bootld_offs(adapter);
  827. flashaddr = NETXEN_BOOTLD_START;
  828. for (i = 0; i < size; i++) {
  829. data = cpu_to_le64(ptr64[i]);
  830. if (adapter->pci_mem_write(adapter, flashaddr, data))
  831. return -EIO;
  832. flashaddr += 8;
  833. }
  834. size = (__force u32)nx_get_fw_size(adapter) / 8;
  835. ptr64 = (u64 *)nx_get_fw_offs(adapter);
  836. flashaddr = NETXEN_IMAGE_START;
  837. for (i = 0; i < size; i++) {
  838. data = cpu_to_le64(ptr64[i]);
  839. if (adapter->pci_mem_write(adapter,
  840. flashaddr, data))
  841. return -EIO;
  842. flashaddr += 8;
  843. }
  844. size = (__force u32)nx_get_fw_size(adapter) % 8;
  845. if (size) {
  846. data = cpu_to_le64(ptr64[i]);
  847. if (adapter->pci_mem_write(adapter,
  848. flashaddr, data))
  849. return -EIO;
  850. }
  851. } else {
  852. u64 data;
  853. u32 hi, lo;
  854. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  855. flashaddr = NETXEN_BOOTLD_START;
  856. for (i = 0; i < size; i++) {
  857. if (netxen_rom_fast_read(adapter,
  858. flashaddr, (int *)&lo) != 0)
  859. return -EIO;
  860. if (netxen_rom_fast_read(adapter,
  861. flashaddr + 4, (int *)&hi) != 0)
  862. return -EIO;
  863. /* hi, lo are already in host endian byteorder */
  864. data = (((u64)hi << 32) | lo);
  865. if (adapter->pci_mem_write(adapter,
  866. flashaddr, data))
  867. return -EIO;
  868. flashaddr += 8;
  869. }
  870. }
  871. msleep(1);
  872. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
  873. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x18, 0x1020);
  874. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001e);
  875. } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  876. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  877. else {
  878. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  879. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  880. }
  881. return 0;
  882. }
  883. static int
  884. netxen_validate_firmware(struct netxen_adapter *adapter)
  885. {
  886. __le32 val;
  887. u32 ver, min_ver, bios;
  888. struct pci_dev *pdev = adapter->pdev;
  889. const struct firmware *fw = adapter->fw;
  890. u8 fw_type = adapter->fw_type;
  891. if (fw_type == NX_UNIFIED_ROMIMAGE) {
  892. if (netxen_nic_validate_unified_romimage(adapter))
  893. return -EINVAL;
  894. } else {
  895. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  896. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  897. return -EINVAL;
  898. if (fw->size < NX_FW_MIN_SIZE)
  899. return -EINVAL;
  900. }
  901. val = nx_get_fw_version(adapter);
  902. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  903. min_ver = NETXEN_VERSION_CODE(4, 0, 216);
  904. else
  905. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  906. ver = NETXEN_DECODE_VERSION(val);
  907. if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
  908. dev_err(&pdev->dev,
  909. "%s: firmware version %d.%d.%d unsupported\n",
  910. fw_name[fw_type], _major(ver), _minor(ver), _build(ver));
  911. return -EINVAL;
  912. }
  913. val = nx_get_bios_version(adapter);
  914. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  915. if ((__force u32)val != bios) {
  916. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  917. fw_name[fw_type]);
  918. return -EINVAL;
  919. }
  920. /* check if flashed firmware is newer */
  921. if (netxen_rom_fast_read(adapter,
  922. NX_FW_VERSION_OFFSET, (int *)&val))
  923. return -EIO;
  924. val = NETXEN_DECODE_VERSION(val);
  925. if (val > ver) {
  926. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  927. fw_name[fw_type]);
  928. return -EINVAL;
  929. }
  930. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  931. return 0;
  932. }
  933. static void
  934. nx_get_next_fwtype(struct netxen_adapter *adapter)
  935. {
  936. u8 fw_type;
  937. switch (adapter->fw_type) {
  938. case NX_UNKNOWN_ROMIMAGE:
  939. fw_type = NX_UNIFIED_ROMIMAGE;
  940. break;
  941. case NX_UNIFIED_ROMIMAGE:
  942. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  943. fw_type = NX_FLASH_ROMIMAGE;
  944. else if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  945. fw_type = NX_P2_MN_ROMIMAGE;
  946. else if (netxen_p3_has_mn(adapter))
  947. fw_type = NX_P3_MN_ROMIMAGE;
  948. else
  949. fw_type = NX_P3_CT_ROMIMAGE;
  950. break;
  951. case NX_P3_MN_ROMIMAGE:
  952. fw_type = NX_P3_CT_ROMIMAGE;
  953. break;
  954. case NX_P2_MN_ROMIMAGE:
  955. case NX_P3_CT_ROMIMAGE:
  956. default:
  957. fw_type = NX_FLASH_ROMIMAGE;
  958. break;
  959. }
  960. adapter->fw_type = fw_type;
  961. }
  962. static int
  963. netxen_p3_has_mn(struct netxen_adapter *adapter)
  964. {
  965. u32 capability, flashed_ver;
  966. capability = 0;
  967. /* NX2031 always had MN */
  968. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  969. return 1;
  970. netxen_rom_fast_read(adapter,
  971. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  972. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  973. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  974. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  975. if (capability & NX_PEG_TUNE_MN_PRESENT)
  976. return 1;
  977. }
  978. return 0;
  979. }
  980. void netxen_request_firmware(struct netxen_adapter *adapter)
  981. {
  982. struct pci_dev *pdev = adapter->pdev;
  983. int rc = 0;
  984. adapter->fw_type = NX_UNKNOWN_ROMIMAGE;
  985. next:
  986. nx_get_next_fwtype(adapter);
  987. if (adapter->fw_type == NX_FLASH_ROMIMAGE) {
  988. adapter->fw = NULL;
  989. } else {
  990. rc = request_firmware(&adapter->fw,
  991. fw_name[adapter->fw_type], &pdev->dev);
  992. if (rc != 0)
  993. goto next;
  994. rc = netxen_validate_firmware(adapter);
  995. if (rc != 0) {
  996. release_firmware(adapter->fw);
  997. msleep(1);
  998. goto next;
  999. }
  1000. }
  1001. }
  1002. void
  1003. netxen_release_firmware(struct netxen_adapter *adapter)
  1004. {
  1005. if (adapter->fw)
  1006. release_firmware(adapter->fw);
  1007. adapter->fw = NULL;
  1008. }
  1009. int netxen_init_dummy_dma(struct netxen_adapter *adapter)
  1010. {
  1011. u64 addr;
  1012. u32 hi, lo;
  1013. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1014. return 0;
  1015. adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
  1016. NETXEN_HOST_DUMMY_DMA_SIZE,
  1017. &adapter->dummy_dma.phys_addr);
  1018. if (adapter->dummy_dma.addr == NULL) {
  1019. dev_err(&adapter->pdev->dev,
  1020. "ERROR: Could not allocate dummy DMA memory\n");
  1021. return -ENOMEM;
  1022. }
  1023. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  1024. hi = (addr >> 32) & 0xffffffff;
  1025. lo = addr & 0xffffffff;
  1026. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  1027. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  1028. return 0;
  1029. }
  1030. /*
  1031. * NetXen DMA watchdog control:
  1032. *
  1033. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  1034. * Bit 1 : disable_request => 1 req disable dma watchdog
  1035. * Bit 2 : enable_request => 1 req enable dma watchdog
  1036. * Bit 3-31 : unused
  1037. */
  1038. void netxen_free_dummy_dma(struct netxen_adapter *adapter)
  1039. {
  1040. int i = 100;
  1041. u32 ctrl;
  1042. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1043. return;
  1044. if (!adapter->dummy_dma.addr)
  1045. return;
  1046. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  1047. if ((ctrl & 0x1) != 0) {
  1048. NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
  1049. while ((ctrl & 0x1) != 0) {
  1050. msleep(50);
  1051. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  1052. if (--i == 0)
  1053. break;
  1054. };
  1055. }
  1056. if (i) {
  1057. pci_free_consistent(adapter->pdev,
  1058. NETXEN_HOST_DUMMY_DMA_SIZE,
  1059. adapter->dummy_dma.addr,
  1060. adapter->dummy_dma.phys_addr);
  1061. adapter->dummy_dma.addr = NULL;
  1062. } else
  1063. dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
  1064. }
  1065. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  1066. {
  1067. u32 val = 0;
  1068. int retries = 60;
  1069. if (pegtune_val)
  1070. return 0;
  1071. do {
  1072. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  1073. switch (val) {
  1074. case PHAN_INITIALIZE_COMPLETE:
  1075. case PHAN_INITIALIZE_ACK:
  1076. return 0;
  1077. case PHAN_INITIALIZE_FAILED:
  1078. goto out_err;
  1079. default:
  1080. break;
  1081. }
  1082. msleep(500);
  1083. } while (--retries);
  1084. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  1085. out_err:
  1086. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  1087. return -EIO;
  1088. }
  1089. static int
  1090. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  1091. {
  1092. u32 val = 0;
  1093. int retries = 2000;
  1094. do {
  1095. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  1096. if (val == PHAN_PEG_RCV_INITIALIZED)
  1097. return 0;
  1098. msleep(10);
  1099. } while (--retries);
  1100. if (!retries) {
  1101. printk(KERN_ERR "Receive Peg initialization not "
  1102. "complete, state: 0x%x.\n", val);
  1103. return -EIO;
  1104. }
  1105. return 0;
  1106. }
  1107. int netxen_init_firmware(struct netxen_adapter *adapter)
  1108. {
  1109. int err;
  1110. err = netxen_receive_peg_ready(adapter);
  1111. if (err)
  1112. return err;
  1113. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  1114. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  1115. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  1116. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1117. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  1118. return err;
  1119. }
  1120. static void
  1121. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  1122. {
  1123. u32 cable_OUI;
  1124. u16 cable_len;
  1125. u16 link_speed;
  1126. u8 link_status, module, duplex, autoneg;
  1127. struct net_device *netdev = adapter->netdev;
  1128. adapter->has_link_events = 1;
  1129. cable_OUI = msg->body[1] & 0xffffffff;
  1130. cable_len = (msg->body[1] >> 32) & 0xffff;
  1131. link_speed = (msg->body[1] >> 48) & 0xffff;
  1132. link_status = msg->body[2] & 0xff;
  1133. duplex = (msg->body[2] >> 16) & 0xff;
  1134. autoneg = (msg->body[2] >> 24) & 0xff;
  1135. module = (msg->body[2] >> 8) & 0xff;
  1136. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  1137. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  1138. netdev->name, cable_OUI, cable_len);
  1139. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  1140. printk(KERN_INFO "%s: unsupported cable length %d\n",
  1141. netdev->name, cable_len);
  1142. }
  1143. netxen_advert_link_change(adapter, link_status);
  1144. /* update link parameters */
  1145. if (duplex == LINKEVENT_FULL_DUPLEX)
  1146. adapter->link_duplex = DUPLEX_FULL;
  1147. else
  1148. adapter->link_duplex = DUPLEX_HALF;
  1149. adapter->module_type = module;
  1150. adapter->link_autoneg = autoneg;
  1151. adapter->link_speed = link_speed;
  1152. }
  1153. static void
  1154. netxen_handle_fw_message(int desc_cnt, int index,
  1155. struct nx_host_sds_ring *sds_ring)
  1156. {
  1157. nx_fw_msg_t msg;
  1158. struct status_desc *desc;
  1159. int i = 0, opcode;
  1160. while (desc_cnt > 0 && i < 8) {
  1161. desc = &sds_ring->desc_head[index];
  1162. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  1163. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  1164. index = get_next_index(index, sds_ring->num_desc);
  1165. desc_cnt--;
  1166. }
  1167. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  1168. switch (opcode) {
  1169. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  1170. netxen_handle_linkevent(sds_ring->adapter, &msg);
  1171. break;
  1172. default:
  1173. break;
  1174. }
  1175. }
  1176. static int
  1177. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  1178. struct nx_host_rds_ring *rds_ring,
  1179. struct netxen_rx_buffer *buffer)
  1180. {
  1181. struct sk_buff *skb;
  1182. dma_addr_t dma;
  1183. struct pci_dev *pdev = adapter->pdev;
  1184. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  1185. if (!buffer->skb)
  1186. return 1;
  1187. skb = buffer->skb;
  1188. if (!adapter->ahw.cut_through)
  1189. skb_reserve(skb, 2);
  1190. dma = pci_map_single(pdev, skb->data,
  1191. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  1192. if (pci_dma_mapping_error(pdev, dma)) {
  1193. dev_kfree_skb_any(skb);
  1194. buffer->skb = NULL;
  1195. return 1;
  1196. }
  1197. buffer->skb = skb;
  1198. buffer->dma = dma;
  1199. buffer->state = NETXEN_BUFFER_BUSY;
  1200. return 0;
  1201. }
  1202. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  1203. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1204. {
  1205. struct netxen_rx_buffer *buffer;
  1206. struct sk_buff *skb;
  1207. buffer = &rds_ring->rx_buf_arr[index];
  1208. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1209. PCI_DMA_FROMDEVICE);
  1210. skb = buffer->skb;
  1211. if (!skb)
  1212. goto no_skb;
  1213. if (likely((adapter->netdev->features & NETIF_F_RXCSUM)
  1214. && cksum == STATUS_CKSUM_OK)) {
  1215. adapter->stats.csummed++;
  1216. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1217. } else
  1218. skb->ip_summed = CHECKSUM_NONE;
  1219. skb->dev = adapter->netdev;
  1220. buffer->skb = NULL;
  1221. no_skb:
  1222. buffer->state = NETXEN_BUFFER_FREE;
  1223. return skb;
  1224. }
  1225. static struct netxen_rx_buffer *
  1226. netxen_process_rcv(struct netxen_adapter *adapter,
  1227. struct nx_host_sds_ring *sds_ring,
  1228. int ring, u64 sts_data0)
  1229. {
  1230. struct net_device *netdev = adapter->netdev;
  1231. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1232. struct netxen_rx_buffer *buffer;
  1233. struct sk_buff *skb;
  1234. struct nx_host_rds_ring *rds_ring;
  1235. int index, length, cksum, pkt_offset;
  1236. if (unlikely(ring >= adapter->max_rds_rings))
  1237. return NULL;
  1238. rds_ring = &recv_ctx->rds_rings[ring];
  1239. index = netxen_get_sts_refhandle(sts_data0);
  1240. if (unlikely(index >= rds_ring->num_desc))
  1241. return NULL;
  1242. buffer = &rds_ring->rx_buf_arr[index];
  1243. length = netxen_get_sts_totallength(sts_data0);
  1244. cksum = netxen_get_sts_status(sts_data0);
  1245. pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
  1246. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1247. if (!skb)
  1248. return buffer;
  1249. if (length > rds_ring->skb_size)
  1250. skb_put(skb, rds_ring->skb_size);
  1251. else
  1252. skb_put(skb, length);
  1253. if (pkt_offset)
  1254. skb_pull(skb, pkt_offset);
  1255. skb->protocol = eth_type_trans(skb, netdev);
  1256. napi_gro_receive(&sds_ring->napi, skb);
  1257. adapter->stats.rx_pkts++;
  1258. adapter->stats.rxbytes += length;
  1259. return buffer;
  1260. }
  1261. #define TCP_HDR_SIZE 20
  1262. #define TCP_TS_OPTION_SIZE 12
  1263. #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
  1264. static struct netxen_rx_buffer *
  1265. netxen_process_lro(struct netxen_adapter *adapter,
  1266. struct nx_host_sds_ring *sds_ring,
  1267. int ring, u64 sts_data0, u64 sts_data1)
  1268. {
  1269. struct net_device *netdev = adapter->netdev;
  1270. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1271. struct netxen_rx_buffer *buffer;
  1272. struct sk_buff *skb;
  1273. struct nx_host_rds_ring *rds_ring;
  1274. struct iphdr *iph;
  1275. struct tcphdr *th;
  1276. bool push, timestamp;
  1277. int l2_hdr_offset, l4_hdr_offset;
  1278. int index;
  1279. u16 lro_length, length, data_offset;
  1280. u32 seq_number;
  1281. if (unlikely(ring > adapter->max_rds_rings))
  1282. return NULL;
  1283. rds_ring = &recv_ctx->rds_rings[ring];
  1284. index = netxen_get_lro_sts_refhandle(sts_data0);
  1285. if (unlikely(index > rds_ring->num_desc))
  1286. return NULL;
  1287. buffer = &rds_ring->rx_buf_arr[index];
  1288. timestamp = netxen_get_lro_sts_timestamp(sts_data0);
  1289. lro_length = netxen_get_lro_sts_length(sts_data0);
  1290. l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
  1291. l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
  1292. push = netxen_get_lro_sts_push_flag(sts_data0);
  1293. seq_number = netxen_get_lro_sts_seq_number(sts_data1);
  1294. skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1295. if (!skb)
  1296. return buffer;
  1297. if (timestamp)
  1298. data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
  1299. else
  1300. data_offset = l4_hdr_offset + TCP_HDR_SIZE;
  1301. skb_put(skb, lro_length + data_offset);
  1302. skb_pull(skb, l2_hdr_offset);
  1303. skb->protocol = eth_type_trans(skb, netdev);
  1304. iph = (struct iphdr *)skb->data;
  1305. th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
  1306. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1307. iph->tot_len = htons(length);
  1308. iph->check = 0;
  1309. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1310. th->psh = push;
  1311. th->seq = htonl(seq_number);
  1312. length = skb->len;
  1313. netif_receive_skb(skb);
  1314. adapter->stats.lro_pkts++;
  1315. adapter->stats.rxbytes += length;
  1316. return buffer;
  1317. }
  1318. #define netxen_merge_rx_buffers(list, head) \
  1319. do { list_splice_tail_init(list, head); } while (0);
  1320. int
  1321. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1322. {
  1323. struct netxen_adapter *adapter = sds_ring->adapter;
  1324. struct list_head *cur;
  1325. struct status_desc *desc;
  1326. struct netxen_rx_buffer *rxbuf;
  1327. u32 consumer = sds_ring->consumer;
  1328. int count = 0;
  1329. u64 sts_data0, sts_data1;
  1330. int opcode, ring = 0, desc_cnt;
  1331. while (count < max) {
  1332. desc = &sds_ring->desc_head[consumer];
  1333. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1334. if (!(sts_data0 & STATUS_OWNER_HOST))
  1335. break;
  1336. desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
  1337. opcode = netxen_get_sts_opcode(sts_data0);
  1338. switch (opcode) {
  1339. case NETXEN_NIC_RXPKT_DESC:
  1340. case NETXEN_OLD_RXPKT_DESC:
  1341. case NETXEN_NIC_SYN_OFFLOAD:
  1342. ring = netxen_get_sts_type(sts_data0);
  1343. rxbuf = netxen_process_rcv(adapter, sds_ring,
  1344. ring, sts_data0);
  1345. break;
  1346. case NETXEN_NIC_LRO_DESC:
  1347. ring = netxen_get_lro_sts_type(sts_data0);
  1348. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1349. rxbuf = netxen_process_lro(adapter, sds_ring,
  1350. ring, sts_data0, sts_data1);
  1351. break;
  1352. case NETXEN_NIC_RESPONSE_DESC:
  1353. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1354. default:
  1355. goto skip;
  1356. }
  1357. WARN_ON(desc_cnt > 1);
  1358. if (rxbuf)
  1359. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1360. skip:
  1361. for (; desc_cnt > 0; desc_cnt--) {
  1362. desc = &sds_ring->desc_head[consumer];
  1363. desc->status_desc_data[0] =
  1364. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1365. consumer = get_next_index(consumer, sds_ring->num_desc);
  1366. }
  1367. count++;
  1368. }
  1369. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1370. struct nx_host_rds_ring *rds_ring =
  1371. &adapter->recv_ctx.rds_rings[ring];
  1372. if (!list_empty(&sds_ring->free_list[ring])) {
  1373. list_for_each(cur, &sds_ring->free_list[ring]) {
  1374. rxbuf = list_entry(cur,
  1375. struct netxen_rx_buffer, list);
  1376. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1377. }
  1378. spin_lock(&rds_ring->lock);
  1379. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1380. &rds_ring->free_list);
  1381. spin_unlock(&rds_ring->lock);
  1382. }
  1383. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1384. }
  1385. if (count) {
  1386. sds_ring->consumer = consumer;
  1387. NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
  1388. }
  1389. return count;
  1390. }
  1391. /* Process Command status ring */
  1392. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1393. {
  1394. u32 sw_consumer, hw_consumer;
  1395. int count = 0, i;
  1396. struct netxen_cmd_buffer *buffer;
  1397. struct pci_dev *pdev = adapter->pdev;
  1398. struct net_device *netdev = adapter->netdev;
  1399. struct netxen_skb_frag *frag;
  1400. int done = 0;
  1401. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1402. if (!spin_trylock(&adapter->tx_clean_lock))
  1403. return 1;
  1404. sw_consumer = tx_ring->sw_consumer;
  1405. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1406. while (sw_consumer != hw_consumer) {
  1407. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1408. if (buffer->skb) {
  1409. frag = &buffer->frag_array[0];
  1410. pci_unmap_single(pdev, frag->dma, frag->length,
  1411. PCI_DMA_TODEVICE);
  1412. frag->dma = 0ULL;
  1413. for (i = 1; i < buffer->frag_count; i++) {
  1414. frag++; /* Get the next frag */
  1415. pci_unmap_page(pdev, frag->dma, frag->length,
  1416. PCI_DMA_TODEVICE);
  1417. frag->dma = 0ULL;
  1418. }
  1419. adapter->stats.xmitfinished++;
  1420. dev_kfree_skb_any(buffer->skb);
  1421. buffer->skb = NULL;
  1422. }
  1423. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1424. if (++count >= MAX_STATUS_HANDLE)
  1425. break;
  1426. }
  1427. if (count && netif_running(netdev)) {
  1428. tx_ring->sw_consumer = sw_consumer;
  1429. smp_mb();
  1430. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev))
  1431. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
  1432. netif_wake_queue(netdev);
  1433. adapter->tx_timeo_cnt = 0;
  1434. }
  1435. /*
  1436. * If everything is freed up to consumer then check if the ring is full
  1437. * If the ring is full then check if more needs to be freed and
  1438. * schedule the call back again.
  1439. *
  1440. * This happens when there are 2 CPUs. One could be freeing and the
  1441. * other filling it. If the ring is full when we get out of here and
  1442. * the card has already interrupted the host then the host can miss the
  1443. * interrupt.
  1444. *
  1445. * There is still a possible race condition and the host could miss an
  1446. * interrupt. The card has to take care of this.
  1447. */
  1448. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1449. done = (sw_consumer == hw_consumer);
  1450. spin_unlock(&adapter->tx_clean_lock);
  1451. return done;
  1452. }
  1453. void
  1454. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1455. struct nx_host_rds_ring *rds_ring)
  1456. {
  1457. struct rcv_desc *pdesc;
  1458. struct netxen_rx_buffer *buffer;
  1459. int producer, count = 0;
  1460. netxen_ctx_msg msg = 0;
  1461. struct list_head *head;
  1462. producer = rds_ring->producer;
  1463. head = &rds_ring->free_list;
  1464. while (!list_empty(head)) {
  1465. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1466. if (!buffer->skb) {
  1467. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1468. break;
  1469. }
  1470. count++;
  1471. list_del(&buffer->list);
  1472. /* make a rcv descriptor */
  1473. pdesc = &rds_ring->desc_head[producer];
  1474. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1475. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1476. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1477. producer = get_next_index(producer, rds_ring->num_desc);
  1478. }
  1479. if (count) {
  1480. rds_ring->producer = producer;
  1481. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1482. (producer-1) & (rds_ring->num_desc-1));
  1483. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  1484. /*
  1485. * Write a doorbell msg to tell phanmon of change in
  1486. * receive ring producer
  1487. * Only for firmware version < 4.0.0
  1488. */
  1489. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1490. netxen_set_msg_privid(msg);
  1491. netxen_set_msg_count(msg,
  1492. ((producer - 1) &
  1493. (rds_ring->num_desc - 1)));
  1494. netxen_set_msg_ctxid(msg, adapter->portnum);
  1495. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1496. NXWRIO(adapter, DB_NORMALIZE(adapter,
  1497. NETXEN_RCV_PRODUCER_OFFSET), msg);
  1498. }
  1499. }
  1500. }
  1501. static void
  1502. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1503. struct nx_host_rds_ring *rds_ring)
  1504. {
  1505. struct rcv_desc *pdesc;
  1506. struct netxen_rx_buffer *buffer;
  1507. int producer, count = 0;
  1508. struct list_head *head;
  1509. if (!spin_trylock(&rds_ring->lock))
  1510. return;
  1511. producer = rds_ring->producer;
  1512. head = &rds_ring->free_list;
  1513. while (!list_empty(head)) {
  1514. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1515. if (!buffer->skb) {
  1516. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1517. break;
  1518. }
  1519. count++;
  1520. list_del(&buffer->list);
  1521. /* make a rcv descriptor */
  1522. pdesc = &rds_ring->desc_head[producer];
  1523. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1524. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1525. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1526. producer = get_next_index(producer, rds_ring->num_desc);
  1527. }
  1528. if (count) {
  1529. rds_ring->producer = producer;
  1530. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1531. (producer - 1) & (rds_ring->num_desc - 1));
  1532. }
  1533. spin_unlock(&rds_ring->lock);
  1534. }
  1535. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1536. {
  1537. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1538. }