en_port.c 9.2 KB

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  1. /*
  2. * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. *
  32. */
  33. #include <linux/if_vlan.h>
  34. #include <linux/mlx4/device.h>
  35. #include <linux/mlx4/cmd.h>
  36. #include "en_port.h"
  37. #include "mlx4_en.h"
  38. int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port,
  39. u64 mac, u64 clear, u8 mode)
  40. {
  41. return mlx4_cmd(dev, (mac | (clear << 63)), port, mode,
  42. MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B);
  43. }
  44. int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, struct vlan_group *grp)
  45. {
  46. struct mlx4_cmd_mailbox *mailbox;
  47. struct mlx4_set_vlan_fltr_mbox *filter;
  48. int i;
  49. int j;
  50. int index = 0;
  51. u32 entry;
  52. int err = 0;
  53. mailbox = mlx4_alloc_cmd_mailbox(dev);
  54. if (IS_ERR(mailbox))
  55. return PTR_ERR(mailbox);
  56. filter = mailbox->buf;
  57. if (grp) {
  58. memset(filter, 0, sizeof *filter);
  59. for (i = VLAN_FLTR_SIZE - 1; i >= 0; i--) {
  60. entry = 0;
  61. for (j = 0; j < 32; j++)
  62. if (vlan_group_get_device(grp, index++))
  63. entry |= 1 << j;
  64. filter->entry[i] = cpu_to_be32(entry);
  65. }
  66. } else {
  67. /* When no vlans are configured we block all vlans */
  68. memset(filter, 0, sizeof(*filter));
  69. }
  70. err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_SET_VLAN_FLTR,
  71. MLX4_CMD_TIME_CLASS_B);
  72. mlx4_free_cmd_mailbox(dev, mailbox);
  73. return err;
  74. }
  75. int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
  76. u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx)
  77. {
  78. struct mlx4_cmd_mailbox *mailbox;
  79. struct mlx4_set_port_general_context *context;
  80. int err;
  81. u32 in_mod;
  82. mailbox = mlx4_alloc_cmd_mailbox(dev);
  83. if (IS_ERR(mailbox))
  84. return PTR_ERR(mailbox);
  85. context = mailbox->buf;
  86. memset(context, 0, sizeof *context);
  87. context->flags = SET_PORT_GEN_ALL_VALID;
  88. context->mtu = cpu_to_be16(mtu);
  89. context->pptx = (pptx * (!pfctx)) << 7;
  90. context->pfctx = pfctx;
  91. context->pprx = (pprx * (!pfcrx)) << 7;
  92. context->pfcrx = pfcrx;
  93. in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
  94. err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
  95. MLX4_CMD_TIME_CLASS_B);
  96. mlx4_free_cmd_mailbox(dev, mailbox);
  97. return err;
  98. }
  99. int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
  100. u8 promisc)
  101. {
  102. struct mlx4_cmd_mailbox *mailbox;
  103. struct mlx4_set_port_rqp_calc_context *context;
  104. int err;
  105. u32 in_mod;
  106. u32 m_promisc = (dev->caps.vep_mc_steering) ? MCAST_DIRECT : MCAST_DEFAULT;
  107. if (dev->caps.vep_mc_steering && dev->caps.vep_uc_steering)
  108. return 0;
  109. mailbox = mlx4_alloc_cmd_mailbox(dev);
  110. if (IS_ERR(mailbox))
  111. return PTR_ERR(mailbox);
  112. context = mailbox->buf;
  113. memset(context, 0, sizeof *context);
  114. context->base_qpn = cpu_to_be32(base_qpn);
  115. context->n_mac = 0x7;
  116. context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT |
  117. base_qpn);
  118. context->mcast = cpu_to_be32(m_promisc << SET_PORT_MC_PROMISC_SHIFT |
  119. base_qpn);
  120. context->intra_no_vlan = 0;
  121. context->no_vlan = MLX4_NO_VLAN_IDX;
  122. context->intra_vlan_miss = 0;
  123. context->vlan_miss = MLX4_VLAN_MISS_IDX;
  124. in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port;
  125. err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
  126. MLX4_CMD_TIME_CLASS_B);
  127. mlx4_free_cmd_mailbox(dev, mailbox);
  128. return err;
  129. }
  130. int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port)
  131. {
  132. struct mlx4_en_query_port_context *qport_context;
  133. struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
  134. struct mlx4_en_port_state *state = &priv->port_state;
  135. struct mlx4_cmd_mailbox *mailbox;
  136. int err;
  137. mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
  138. if (IS_ERR(mailbox))
  139. return PTR_ERR(mailbox);
  140. memset(mailbox->buf, 0, sizeof(*qport_context));
  141. err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
  142. MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B);
  143. if (err)
  144. goto out;
  145. qport_context = mailbox->buf;
  146. /* This command is always accessed from Ethtool context
  147. * already synchronized, no need in locking */
  148. state->link_state = !!(qport_context->link_up & MLX4_EN_LINK_UP_MASK);
  149. if ((qport_context->link_speed & MLX4_EN_SPEED_MASK) ==
  150. MLX4_EN_1G_SPEED)
  151. state->link_speed = 1000;
  152. else
  153. state->link_speed = 10000;
  154. state->transciver = qport_context->transceiver;
  155. out:
  156. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  157. return err;
  158. }
  159. int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset)
  160. {
  161. struct mlx4_en_stat_out_mbox *mlx4_en_stats;
  162. struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
  163. struct net_device_stats *stats = &priv->stats;
  164. struct mlx4_cmd_mailbox *mailbox;
  165. u64 in_mod = reset << 8 | port;
  166. int err;
  167. int i;
  168. mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
  169. if (IS_ERR(mailbox))
  170. return PTR_ERR(mailbox);
  171. memset(mailbox->buf, 0, sizeof(*mlx4_en_stats));
  172. err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, in_mod, 0,
  173. MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B);
  174. if (err)
  175. goto out;
  176. mlx4_en_stats = mailbox->buf;
  177. spin_lock_bh(&priv->stats_lock);
  178. stats->rx_packets = 0;
  179. stats->rx_bytes = 0;
  180. for (i = 0; i < priv->rx_ring_num; i++) {
  181. stats->rx_packets += priv->rx_ring[i].packets;
  182. stats->rx_bytes += priv->rx_ring[i].bytes;
  183. }
  184. stats->tx_packets = 0;
  185. stats->tx_bytes = 0;
  186. for (i = 0; i < priv->tx_ring_num; i++) {
  187. stats->tx_packets += priv->tx_ring[i].packets;
  188. stats->tx_bytes += priv->tx_ring[i].bytes;
  189. }
  190. stats->rx_errors = be64_to_cpu(mlx4_en_stats->PCS) +
  191. be32_to_cpu(mlx4_en_stats->RdropLength) +
  192. be32_to_cpu(mlx4_en_stats->RJBBR) +
  193. be32_to_cpu(mlx4_en_stats->RCRC) +
  194. be32_to_cpu(mlx4_en_stats->RRUNT);
  195. stats->tx_errors = be32_to_cpu(mlx4_en_stats->TDROP);
  196. stats->multicast = be64_to_cpu(mlx4_en_stats->MCAST_prio_0) +
  197. be64_to_cpu(mlx4_en_stats->MCAST_prio_1) +
  198. be64_to_cpu(mlx4_en_stats->MCAST_prio_2) +
  199. be64_to_cpu(mlx4_en_stats->MCAST_prio_3) +
  200. be64_to_cpu(mlx4_en_stats->MCAST_prio_4) +
  201. be64_to_cpu(mlx4_en_stats->MCAST_prio_5) +
  202. be64_to_cpu(mlx4_en_stats->MCAST_prio_6) +
  203. be64_to_cpu(mlx4_en_stats->MCAST_prio_7) +
  204. be64_to_cpu(mlx4_en_stats->MCAST_novlan);
  205. stats->collisions = 0;
  206. stats->rx_length_errors = be32_to_cpu(mlx4_en_stats->RdropLength);
  207. stats->rx_over_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
  208. stats->rx_crc_errors = be32_to_cpu(mlx4_en_stats->RCRC);
  209. stats->rx_frame_errors = 0;
  210. stats->rx_fifo_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
  211. stats->rx_missed_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
  212. stats->tx_aborted_errors = 0;
  213. stats->tx_carrier_errors = 0;
  214. stats->tx_fifo_errors = 0;
  215. stats->tx_heartbeat_errors = 0;
  216. stats->tx_window_errors = 0;
  217. priv->pkstats.broadcast =
  218. be64_to_cpu(mlx4_en_stats->RBCAST_prio_0) +
  219. be64_to_cpu(mlx4_en_stats->RBCAST_prio_1) +
  220. be64_to_cpu(mlx4_en_stats->RBCAST_prio_2) +
  221. be64_to_cpu(mlx4_en_stats->RBCAST_prio_3) +
  222. be64_to_cpu(mlx4_en_stats->RBCAST_prio_4) +
  223. be64_to_cpu(mlx4_en_stats->RBCAST_prio_5) +
  224. be64_to_cpu(mlx4_en_stats->RBCAST_prio_6) +
  225. be64_to_cpu(mlx4_en_stats->RBCAST_prio_7) +
  226. be64_to_cpu(mlx4_en_stats->RBCAST_novlan);
  227. priv->pkstats.rx_prio[0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_0);
  228. priv->pkstats.rx_prio[1] = be64_to_cpu(mlx4_en_stats->RTOT_prio_1);
  229. priv->pkstats.rx_prio[2] = be64_to_cpu(mlx4_en_stats->RTOT_prio_2);
  230. priv->pkstats.rx_prio[3] = be64_to_cpu(mlx4_en_stats->RTOT_prio_3);
  231. priv->pkstats.rx_prio[4] = be64_to_cpu(mlx4_en_stats->RTOT_prio_4);
  232. priv->pkstats.rx_prio[5] = be64_to_cpu(mlx4_en_stats->RTOT_prio_5);
  233. priv->pkstats.rx_prio[6] = be64_to_cpu(mlx4_en_stats->RTOT_prio_6);
  234. priv->pkstats.rx_prio[7] = be64_to_cpu(mlx4_en_stats->RTOT_prio_7);
  235. priv->pkstats.tx_prio[0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_0);
  236. priv->pkstats.tx_prio[1] = be64_to_cpu(mlx4_en_stats->TTOT_prio_1);
  237. priv->pkstats.tx_prio[2] = be64_to_cpu(mlx4_en_stats->TTOT_prio_2);
  238. priv->pkstats.tx_prio[3] = be64_to_cpu(mlx4_en_stats->TTOT_prio_3);
  239. priv->pkstats.tx_prio[4] = be64_to_cpu(mlx4_en_stats->TTOT_prio_4);
  240. priv->pkstats.tx_prio[5] = be64_to_cpu(mlx4_en_stats->TTOT_prio_5);
  241. priv->pkstats.tx_prio[6] = be64_to_cpu(mlx4_en_stats->TTOT_prio_6);
  242. priv->pkstats.tx_prio[7] = be64_to_cpu(mlx4_en_stats->TTOT_prio_7);
  243. spin_unlock_bh(&priv->stats_lock);
  244. out:
  245. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  246. return err;
  247. }