ftmac100.c 30 KB

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  1. /*
  2. * Faraday FTMAC100 10/100 Ethernet
  3. *
  4. * (C) Copyright 2009-2011 Faraday Technology
  5. * Po-Yu Chuang <ratbert@faraday-tech.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22. #include <linux/dma-mapping.h>
  23. #include <linux/etherdevice.h>
  24. #include <linux/ethtool.h>
  25. #include <linux/init.h>
  26. #include <linux/io.h>
  27. #include <linux/mii.h>
  28. #include <linux/module.h>
  29. #include <linux/netdevice.h>
  30. #include <linux/platform_device.h>
  31. #include "ftmac100.h"
  32. #define DRV_NAME "ftmac100"
  33. #define DRV_VERSION "0.2"
  34. #define RX_QUEUE_ENTRIES 128 /* must be power of 2 */
  35. #define TX_QUEUE_ENTRIES 16 /* must be power of 2 */
  36. #define MAX_PKT_SIZE 1518
  37. #define RX_BUF_SIZE 2044 /* must be smaller than 0x7ff */
  38. #if MAX_PKT_SIZE > 0x7ff
  39. #error invalid MAX_PKT_SIZE
  40. #endif
  41. #if RX_BUF_SIZE > 0x7ff || RX_BUF_SIZE > PAGE_SIZE
  42. #error invalid RX_BUF_SIZE
  43. #endif
  44. /******************************************************************************
  45. * private data
  46. *****************************************************************************/
  47. struct ftmac100_descs {
  48. struct ftmac100_rxdes rxdes[RX_QUEUE_ENTRIES];
  49. struct ftmac100_txdes txdes[TX_QUEUE_ENTRIES];
  50. };
  51. struct ftmac100 {
  52. struct resource *res;
  53. void __iomem *base;
  54. int irq;
  55. struct ftmac100_descs *descs;
  56. dma_addr_t descs_dma_addr;
  57. unsigned int rx_pointer;
  58. unsigned int tx_clean_pointer;
  59. unsigned int tx_pointer;
  60. unsigned int tx_pending;
  61. spinlock_t tx_lock;
  62. struct net_device *netdev;
  63. struct device *dev;
  64. struct napi_struct napi;
  65. struct mii_if_info mii;
  66. };
  67. static int ftmac100_alloc_rx_page(struct ftmac100 *priv,
  68. struct ftmac100_rxdes *rxdes, gfp_t gfp);
  69. /******************************************************************************
  70. * internal functions (hardware register access)
  71. *****************************************************************************/
  72. #define INT_MASK_ALL_ENABLED (FTMAC100_INT_RPKT_FINISH | \
  73. FTMAC100_INT_NORXBUF | \
  74. FTMAC100_INT_XPKT_OK | \
  75. FTMAC100_INT_XPKT_LOST | \
  76. FTMAC100_INT_RPKT_LOST | \
  77. FTMAC100_INT_AHB_ERR | \
  78. FTMAC100_INT_PHYSTS_CHG)
  79. #define INT_MASK_ALL_DISABLED 0
  80. static void ftmac100_enable_all_int(struct ftmac100 *priv)
  81. {
  82. iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTMAC100_OFFSET_IMR);
  83. }
  84. static void ftmac100_disable_all_int(struct ftmac100 *priv)
  85. {
  86. iowrite32(INT_MASK_ALL_DISABLED, priv->base + FTMAC100_OFFSET_IMR);
  87. }
  88. static void ftmac100_set_rx_ring_base(struct ftmac100 *priv, dma_addr_t addr)
  89. {
  90. iowrite32(addr, priv->base + FTMAC100_OFFSET_RXR_BADR);
  91. }
  92. static void ftmac100_set_tx_ring_base(struct ftmac100 *priv, dma_addr_t addr)
  93. {
  94. iowrite32(addr, priv->base + FTMAC100_OFFSET_TXR_BADR);
  95. }
  96. static void ftmac100_txdma_start_polling(struct ftmac100 *priv)
  97. {
  98. iowrite32(1, priv->base + FTMAC100_OFFSET_TXPD);
  99. }
  100. static int ftmac100_reset(struct ftmac100 *priv)
  101. {
  102. struct net_device *netdev = priv->netdev;
  103. int i;
  104. /* NOTE: reset clears all registers */
  105. iowrite32(FTMAC100_MACCR_SW_RST, priv->base + FTMAC100_OFFSET_MACCR);
  106. for (i = 0; i < 5; i++) {
  107. unsigned int maccr;
  108. maccr = ioread32(priv->base + FTMAC100_OFFSET_MACCR);
  109. if (!(maccr & FTMAC100_MACCR_SW_RST)) {
  110. /*
  111. * FTMAC100_MACCR_SW_RST cleared does not indicate
  112. * that hardware reset completed (what the f*ck).
  113. * We still need to wait for a while.
  114. */
  115. udelay(500);
  116. return 0;
  117. }
  118. udelay(1000);
  119. }
  120. netdev_err(netdev, "software reset failed\n");
  121. return -EIO;
  122. }
  123. static void ftmac100_set_mac(struct ftmac100 *priv, const unsigned char *mac)
  124. {
  125. unsigned int maddr = mac[0] << 8 | mac[1];
  126. unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
  127. iowrite32(maddr, priv->base + FTMAC100_OFFSET_MAC_MADR);
  128. iowrite32(laddr, priv->base + FTMAC100_OFFSET_MAC_LADR);
  129. }
  130. #define MACCR_ENABLE_ALL (FTMAC100_MACCR_XMT_EN | \
  131. FTMAC100_MACCR_RCV_EN | \
  132. FTMAC100_MACCR_XDMA_EN | \
  133. FTMAC100_MACCR_RDMA_EN | \
  134. FTMAC100_MACCR_CRC_APD | \
  135. FTMAC100_MACCR_FULLDUP | \
  136. FTMAC100_MACCR_RX_RUNT | \
  137. FTMAC100_MACCR_RX_BROADPKT)
  138. static int ftmac100_start_hw(struct ftmac100 *priv)
  139. {
  140. struct net_device *netdev = priv->netdev;
  141. if (ftmac100_reset(priv))
  142. return -EIO;
  143. /* setup ring buffer base registers */
  144. ftmac100_set_rx_ring_base(priv,
  145. priv->descs_dma_addr +
  146. offsetof(struct ftmac100_descs, rxdes));
  147. ftmac100_set_tx_ring_base(priv,
  148. priv->descs_dma_addr +
  149. offsetof(struct ftmac100_descs, txdes));
  150. iowrite32(FTMAC100_APTC_RXPOLL_CNT(1), priv->base + FTMAC100_OFFSET_APTC);
  151. ftmac100_set_mac(priv, netdev->dev_addr);
  152. iowrite32(MACCR_ENABLE_ALL, priv->base + FTMAC100_OFFSET_MACCR);
  153. return 0;
  154. }
  155. static void ftmac100_stop_hw(struct ftmac100 *priv)
  156. {
  157. iowrite32(0, priv->base + FTMAC100_OFFSET_MACCR);
  158. }
  159. /******************************************************************************
  160. * internal functions (receive descriptor)
  161. *****************************************************************************/
  162. static bool ftmac100_rxdes_first_segment(struct ftmac100_rxdes *rxdes)
  163. {
  164. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_FRS);
  165. }
  166. static bool ftmac100_rxdes_last_segment(struct ftmac100_rxdes *rxdes)
  167. {
  168. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_LRS);
  169. }
  170. static bool ftmac100_rxdes_owned_by_dma(struct ftmac100_rxdes *rxdes)
  171. {
  172. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_RXDMA_OWN);
  173. }
  174. static void ftmac100_rxdes_set_dma_own(struct ftmac100_rxdes *rxdes)
  175. {
  176. /* clear status bits */
  177. rxdes->rxdes0 = cpu_to_le32(FTMAC100_RXDES0_RXDMA_OWN);
  178. }
  179. static bool ftmac100_rxdes_rx_error(struct ftmac100_rxdes *rxdes)
  180. {
  181. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_RX_ERR);
  182. }
  183. static bool ftmac100_rxdes_crc_error(struct ftmac100_rxdes *rxdes)
  184. {
  185. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_CRC_ERR);
  186. }
  187. static bool ftmac100_rxdes_frame_too_long(struct ftmac100_rxdes *rxdes)
  188. {
  189. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_FTL);
  190. }
  191. static bool ftmac100_rxdes_runt(struct ftmac100_rxdes *rxdes)
  192. {
  193. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_RUNT);
  194. }
  195. static bool ftmac100_rxdes_odd_nibble(struct ftmac100_rxdes *rxdes)
  196. {
  197. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_RX_ODD_NB);
  198. }
  199. static unsigned int ftmac100_rxdes_frame_length(struct ftmac100_rxdes *rxdes)
  200. {
  201. return le32_to_cpu(rxdes->rxdes0) & FTMAC100_RXDES0_RFL;
  202. }
  203. static bool ftmac100_rxdes_multicast(struct ftmac100_rxdes *rxdes)
  204. {
  205. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_MULTICAST);
  206. }
  207. static void ftmac100_rxdes_set_buffer_size(struct ftmac100_rxdes *rxdes,
  208. unsigned int size)
  209. {
  210. rxdes->rxdes1 &= cpu_to_le32(FTMAC100_RXDES1_EDORR);
  211. rxdes->rxdes1 |= cpu_to_le32(FTMAC100_RXDES1_RXBUF_SIZE(size));
  212. }
  213. static void ftmac100_rxdes_set_end_of_ring(struct ftmac100_rxdes *rxdes)
  214. {
  215. rxdes->rxdes1 |= cpu_to_le32(FTMAC100_RXDES1_EDORR);
  216. }
  217. static void ftmac100_rxdes_set_dma_addr(struct ftmac100_rxdes *rxdes,
  218. dma_addr_t addr)
  219. {
  220. rxdes->rxdes2 = cpu_to_le32(addr);
  221. }
  222. static dma_addr_t ftmac100_rxdes_get_dma_addr(struct ftmac100_rxdes *rxdes)
  223. {
  224. return le32_to_cpu(rxdes->rxdes2);
  225. }
  226. /*
  227. * rxdes3 is not used by hardware. We use it to keep track of page.
  228. * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
  229. */
  230. static void ftmac100_rxdes_set_page(struct ftmac100_rxdes *rxdes, struct page *page)
  231. {
  232. rxdes->rxdes3 = (unsigned int)page;
  233. }
  234. static struct page *ftmac100_rxdes_get_page(struct ftmac100_rxdes *rxdes)
  235. {
  236. return (struct page *)rxdes->rxdes3;
  237. }
  238. /******************************************************************************
  239. * internal functions (receive)
  240. *****************************************************************************/
  241. static int ftmac100_next_rx_pointer(int pointer)
  242. {
  243. return (pointer + 1) & (RX_QUEUE_ENTRIES - 1);
  244. }
  245. static void ftmac100_rx_pointer_advance(struct ftmac100 *priv)
  246. {
  247. priv->rx_pointer = ftmac100_next_rx_pointer(priv->rx_pointer);
  248. }
  249. static struct ftmac100_rxdes *ftmac100_current_rxdes(struct ftmac100 *priv)
  250. {
  251. return &priv->descs->rxdes[priv->rx_pointer];
  252. }
  253. static struct ftmac100_rxdes *
  254. ftmac100_rx_locate_first_segment(struct ftmac100 *priv)
  255. {
  256. struct ftmac100_rxdes *rxdes = ftmac100_current_rxdes(priv);
  257. while (!ftmac100_rxdes_owned_by_dma(rxdes)) {
  258. if (ftmac100_rxdes_first_segment(rxdes))
  259. return rxdes;
  260. ftmac100_rxdes_set_dma_own(rxdes);
  261. ftmac100_rx_pointer_advance(priv);
  262. rxdes = ftmac100_current_rxdes(priv);
  263. }
  264. return NULL;
  265. }
  266. static bool ftmac100_rx_packet_error(struct ftmac100 *priv,
  267. struct ftmac100_rxdes *rxdes)
  268. {
  269. struct net_device *netdev = priv->netdev;
  270. bool error = false;
  271. if (unlikely(ftmac100_rxdes_rx_error(rxdes))) {
  272. if (net_ratelimit())
  273. netdev_info(netdev, "rx err\n");
  274. netdev->stats.rx_errors++;
  275. error = true;
  276. }
  277. if (unlikely(ftmac100_rxdes_crc_error(rxdes))) {
  278. if (net_ratelimit())
  279. netdev_info(netdev, "rx crc err\n");
  280. netdev->stats.rx_crc_errors++;
  281. error = true;
  282. }
  283. if (unlikely(ftmac100_rxdes_frame_too_long(rxdes))) {
  284. if (net_ratelimit())
  285. netdev_info(netdev, "rx frame too long\n");
  286. netdev->stats.rx_length_errors++;
  287. error = true;
  288. } else if (unlikely(ftmac100_rxdes_runt(rxdes))) {
  289. if (net_ratelimit())
  290. netdev_info(netdev, "rx runt\n");
  291. netdev->stats.rx_length_errors++;
  292. error = true;
  293. } else if (unlikely(ftmac100_rxdes_odd_nibble(rxdes))) {
  294. if (net_ratelimit())
  295. netdev_info(netdev, "rx odd nibble\n");
  296. netdev->stats.rx_length_errors++;
  297. error = true;
  298. }
  299. return error;
  300. }
  301. static void ftmac100_rx_drop_packet(struct ftmac100 *priv)
  302. {
  303. struct net_device *netdev = priv->netdev;
  304. struct ftmac100_rxdes *rxdes = ftmac100_current_rxdes(priv);
  305. bool done = false;
  306. if (net_ratelimit())
  307. netdev_dbg(netdev, "drop packet %p\n", rxdes);
  308. do {
  309. if (ftmac100_rxdes_last_segment(rxdes))
  310. done = true;
  311. ftmac100_rxdes_set_dma_own(rxdes);
  312. ftmac100_rx_pointer_advance(priv);
  313. rxdes = ftmac100_current_rxdes(priv);
  314. } while (!done && !ftmac100_rxdes_owned_by_dma(rxdes));
  315. netdev->stats.rx_dropped++;
  316. }
  317. static bool ftmac100_rx_packet(struct ftmac100 *priv, int *processed)
  318. {
  319. struct net_device *netdev = priv->netdev;
  320. struct ftmac100_rxdes *rxdes;
  321. struct sk_buff *skb;
  322. struct page *page;
  323. dma_addr_t map;
  324. int length;
  325. rxdes = ftmac100_rx_locate_first_segment(priv);
  326. if (!rxdes)
  327. return false;
  328. if (unlikely(ftmac100_rx_packet_error(priv, rxdes))) {
  329. ftmac100_rx_drop_packet(priv);
  330. return true;
  331. }
  332. /*
  333. * It is impossible to get multi-segment packets
  334. * because we always provide big enough receive buffers.
  335. */
  336. if (unlikely(!ftmac100_rxdes_last_segment(rxdes)))
  337. BUG();
  338. /* start processing */
  339. skb = netdev_alloc_skb_ip_align(netdev, 128);
  340. if (unlikely(!skb)) {
  341. if (net_ratelimit())
  342. netdev_err(netdev, "rx skb alloc failed\n");
  343. ftmac100_rx_drop_packet(priv);
  344. return true;
  345. }
  346. if (unlikely(ftmac100_rxdes_multicast(rxdes)))
  347. netdev->stats.multicast++;
  348. map = ftmac100_rxdes_get_dma_addr(rxdes);
  349. dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
  350. length = ftmac100_rxdes_frame_length(rxdes);
  351. page = ftmac100_rxdes_get_page(rxdes);
  352. skb_fill_page_desc(skb, 0, page, 0, length);
  353. skb->len += length;
  354. skb->data_len += length;
  355. skb->truesize += length;
  356. __pskb_pull_tail(skb, min(length, 64));
  357. ftmac100_alloc_rx_page(priv, rxdes, GFP_ATOMIC);
  358. ftmac100_rx_pointer_advance(priv);
  359. skb->protocol = eth_type_trans(skb, netdev);
  360. netdev->stats.rx_packets++;
  361. netdev->stats.rx_bytes += skb->len;
  362. /* push packet to protocol stack */
  363. netif_receive_skb(skb);
  364. (*processed)++;
  365. return true;
  366. }
  367. /******************************************************************************
  368. * internal functions (transmit descriptor)
  369. *****************************************************************************/
  370. static void ftmac100_txdes_reset(struct ftmac100_txdes *txdes)
  371. {
  372. /* clear all except end of ring bit */
  373. txdes->txdes0 = 0;
  374. txdes->txdes1 &= cpu_to_le32(FTMAC100_TXDES1_EDOTR);
  375. txdes->txdes2 = 0;
  376. txdes->txdes3 = 0;
  377. }
  378. static bool ftmac100_txdes_owned_by_dma(struct ftmac100_txdes *txdes)
  379. {
  380. return txdes->txdes0 & cpu_to_le32(FTMAC100_TXDES0_TXDMA_OWN);
  381. }
  382. static void ftmac100_txdes_set_dma_own(struct ftmac100_txdes *txdes)
  383. {
  384. /*
  385. * Make sure dma own bit will not be set before any other
  386. * descriptor fields.
  387. */
  388. wmb();
  389. txdes->txdes0 |= cpu_to_le32(FTMAC100_TXDES0_TXDMA_OWN);
  390. }
  391. static bool ftmac100_txdes_excessive_collision(struct ftmac100_txdes *txdes)
  392. {
  393. return txdes->txdes0 & cpu_to_le32(FTMAC100_TXDES0_TXPKT_EXSCOL);
  394. }
  395. static bool ftmac100_txdes_late_collision(struct ftmac100_txdes *txdes)
  396. {
  397. return txdes->txdes0 & cpu_to_le32(FTMAC100_TXDES0_TXPKT_LATECOL);
  398. }
  399. static void ftmac100_txdes_set_end_of_ring(struct ftmac100_txdes *txdes)
  400. {
  401. txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_EDOTR);
  402. }
  403. static void ftmac100_txdes_set_first_segment(struct ftmac100_txdes *txdes)
  404. {
  405. txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_FTS);
  406. }
  407. static void ftmac100_txdes_set_last_segment(struct ftmac100_txdes *txdes)
  408. {
  409. txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_LTS);
  410. }
  411. static void ftmac100_txdes_set_txint(struct ftmac100_txdes *txdes)
  412. {
  413. txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_TXIC);
  414. }
  415. static void ftmac100_txdes_set_buffer_size(struct ftmac100_txdes *txdes,
  416. unsigned int len)
  417. {
  418. txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_TXBUF_SIZE(len));
  419. }
  420. static void ftmac100_txdes_set_dma_addr(struct ftmac100_txdes *txdes,
  421. dma_addr_t addr)
  422. {
  423. txdes->txdes2 = cpu_to_le32(addr);
  424. }
  425. static dma_addr_t ftmac100_txdes_get_dma_addr(struct ftmac100_txdes *txdes)
  426. {
  427. return le32_to_cpu(txdes->txdes2);
  428. }
  429. /*
  430. * txdes3 is not used by hardware. We use it to keep track of socket buffer.
  431. * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
  432. */
  433. static void ftmac100_txdes_set_skb(struct ftmac100_txdes *txdes, struct sk_buff *skb)
  434. {
  435. txdes->txdes3 = (unsigned int)skb;
  436. }
  437. static struct sk_buff *ftmac100_txdes_get_skb(struct ftmac100_txdes *txdes)
  438. {
  439. return (struct sk_buff *)txdes->txdes3;
  440. }
  441. /******************************************************************************
  442. * internal functions (transmit)
  443. *****************************************************************************/
  444. static int ftmac100_next_tx_pointer(int pointer)
  445. {
  446. return (pointer + 1) & (TX_QUEUE_ENTRIES - 1);
  447. }
  448. static void ftmac100_tx_pointer_advance(struct ftmac100 *priv)
  449. {
  450. priv->tx_pointer = ftmac100_next_tx_pointer(priv->tx_pointer);
  451. }
  452. static void ftmac100_tx_clean_pointer_advance(struct ftmac100 *priv)
  453. {
  454. priv->tx_clean_pointer = ftmac100_next_tx_pointer(priv->tx_clean_pointer);
  455. }
  456. static struct ftmac100_txdes *ftmac100_current_txdes(struct ftmac100 *priv)
  457. {
  458. return &priv->descs->txdes[priv->tx_pointer];
  459. }
  460. static struct ftmac100_txdes *ftmac100_current_clean_txdes(struct ftmac100 *priv)
  461. {
  462. return &priv->descs->txdes[priv->tx_clean_pointer];
  463. }
  464. static bool ftmac100_tx_complete_packet(struct ftmac100 *priv)
  465. {
  466. struct net_device *netdev = priv->netdev;
  467. struct ftmac100_txdes *txdes;
  468. struct sk_buff *skb;
  469. dma_addr_t map;
  470. if (priv->tx_pending == 0)
  471. return false;
  472. txdes = ftmac100_current_clean_txdes(priv);
  473. if (ftmac100_txdes_owned_by_dma(txdes))
  474. return false;
  475. skb = ftmac100_txdes_get_skb(txdes);
  476. map = ftmac100_txdes_get_dma_addr(txdes);
  477. if (unlikely(ftmac100_txdes_excessive_collision(txdes) ||
  478. ftmac100_txdes_late_collision(txdes))) {
  479. /*
  480. * packet transmitted to ethernet lost due to late collision
  481. * or excessive collision
  482. */
  483. netdev->stats.tx_aborted_errors++;
  484. } else {
  485. netdev->stats.tx_packets++;
  486. netdev->stats.tx_bytes += skb->len;
  487. }
  488. dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
  489. dev_kfree_skb(skb);
  490. ftmac100_txdes_reset(txdes);
  491. ftmac100_tx_clean_pointer_advance(priv);
  492. spin_lock(&priv->tx_lock);
  493. priv->tx_pending--;
  494. spin_unlock(&priv->tx_lock);
  495. netif_wake_queue(netdev);
  496. return true;
  497. }
  498. static void ftmac100_tx_complete(struct ftmac100 *priv)
  499. {
  500. while (ftmac100_tx_complete_packet(priv))
  501. ;
  502. }
  503. static int ftmac100_xmit(struct ftmac100 *priv, struct sk_buff *skb,
  504. dma_addr_t map)
  505. {
  506. struct net_device *netdev = priv->netdev;
  507. struct ftmac100_txdes *txdes;
  508. unsigned int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
  509. txdes = ftmac100_current_txdes(priv);
  510. ftmac100_tx_pointer_advance(priv);
  511. /* setup TX descriptor */
  512. ftmac100_txdes_set_skb(txdes, skb);
  513. ftmac100_txdes_set_dma_addr(txdes, map);
  514. ftmac100_txdes_set_first_segment(txdes);
  515. ftmac100_txdes_set_last_segment(txdes);
  516. ftmac100_txdes_set_txint(txdes);
  517. ftmac100_txdes_set_buffer_size(txdes, len);
  518. spin_lock(&priv->tx_lock);
  519. priv->tx_pending++;
  520. if (priv->tx_pending == TX_QUEUE_ENTRIES)
  521. netif_stop_queue(netdev);
  522. /* start transmit */
  523. ftmac100_txdes_set_dma_own(txdes);
  524. spin_unlock(&priv->tx_lock);
  525. ftmac100_txdma_start_polling(priv);
  526. return NETDEV_TX_OK;
  527. }
  528. /******************************************************************************
  529. * internal functions (buffer)
  530. *****************************************************************************/
  531. static int ftmac100_alloc_rx_page(struct ftmac100 *priv,
  532. struct ftmac100_rxdes *rxdes, gfp_t gfp)
  533. {
  534. struct net_device *netdev = priv->netdev;
  535. struct page *page;
  536. dma_addr_t map;
  537. page = alloc_page(gfp);
  538. if (!page) {
  539. if (net_ratelimit())
  540. netdev_err(netdev, "failed to allocate rx page\n");
  541. return -ENOMEM;
  542. }
  543. map = dma_map_page(priv->dev, page, 0, RX_BUF_SIZE, DMA_FROM_DEVICE);
  544. if (unlikely(dma_mapping_error(priv->dev, map))) {
  545. if (net_ratelimit())
  546. netdev_err(netdev, "failed to map rx page\n");
  547. __free_page(page);
  548. return -ENOMEM;
  549. }
  550. ftmac100_rxdes_set_page(rxdes, page);
  551. ftmac100_rxdes_set_dma_addr(rxdes, map);
  552. ftmac100_rxdes_set_buffer_size(rxdes, RX_BUF_SIZE);
  553. ftmac100_rxdes_set_dma_own(rxdes);
  554. return 0;
  555. }
  556. static void ftmac100_free_buffers(struct ftmac100 *priv)
  557. {
  558. int i;
  559. for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
  560. struct ftmac100_rxdes *rxdes = &priv->descs->rxdes[i];
  561. struct page *page = ftmac100_rxdes_get_page(rxdes);
  562. dma_addr_t map = ftmac100_rxdes_get_dma_addr(rxdes);
  563. if (!page)
  564. continue;
  565. dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
  566. __free_page(page);
  567. }
  568. for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
  569. struct ftmac100_txdes *txdes = &priv->descs->txdes[i];
  570. struct sk_buff *skb = ftmac100_txdes_get_skb(txdes);
  571. dma_addr_t map = ftmac100_txdes_get_dma_addr(txdes);
  572. if (!skb)
  573. continue;
  574. dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
  575. dev_kfree_skb(skb);
  576. }
  577. dma_free_coherent(priv->dev, sizeof(struct ftmac100_descs),
  578. priv->descs, priv->descs_dma_addr);
  579. }
  580. static int ftmac100_alloc_buffers(struct ftmac100 *priv)
  581. {
  582. int i;
  583. priv->descs = dma_alloc_coherent(priv->dev, sizeof(struct ftmac100_descs),
  584. &priv->descs_dma_addr, GFP_KERNEL);
  585. if (!priv->descs)
  586. return -ENOMEM;
  587. memset(priv->descs, 0, sizeof(struct ftmac100_descs));
  588. /* initialize RX ring */
  589. ftmac100_rxdes_set_end_of_ring(&priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]);
  590. for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
  591. struct ftmac100_rxdes *rxdes = &priv->descs->rxdes[i];
  592. if (ftmac100_alloc_rx_page(priv, rxdes, GFP_KERNEL))
  593. goto err;
  594. }
  595. /* initialize TX ring */
  596. ftmac100_txdes_set_end_of_ring(&priv->descs->txdes[TX_QUEUE_ENTRIES - 1]);
  597. return 0;
  598. err:
  599. ftmac100_free_buffers(priv);
  600. return -ENOMEM;
  601. }
  602. /******************************************************************************
  603. * struct mii_if_info functions
  604. *****************************************************************************/
  605. static int ftmac100_mdio_read(struct net_device *netdev, int phy_id, int reg)
  606. {
  607. struct ftmac100 *priv = netdev_priv(netdev);
  608. unsigned int phycr;
  609. int i;
  610. phycr = FTMAC100_PHYCR_PHYAD(phy_id) |
  611. FTMAC100_PHYCR_REGAD(reg) |
  612. FTMAC100_PHYCR_MIIRD;
  613. iowrite32(phycr, priv->base + FTMAC100_OFFSET_PHYCR);
  614. for (i = 0; i < 10; i++) {
  615. phycr = ioread32(priv->base + FTMAC100_OFFSET_PHYCR);
  616. if ((phycr & FTMAC100_PHYCR_MIIRD) == 0)
  617. return phycr & FTMAC100_PHYCR_MIIRDATA;
  618. udelay(100);
  619. }
  620. netdev_err(netdev, "mdio read timed out\n");
  621. return 0;
  622. }
  623. static void ftmac100_mdio_write(struct net_device *netdev, int phy_id, int reg,
  624. int data)
  625. {
  626. struct ftmac100 *priv = netdev_priv(netdev);
  627. unsigned int phycr;
  628. int i;
  629. phycr = FTMAC100_PHYCR_PHYAD(phy_id) |
  630. FTMAC100_PHYCR_REGAD(reg) |
  631. FTMAC100_PHYCR_MIIWR;
  632. data = FTMAC100_PHYWDATA_MIIWDATA(data);
  633. iowrite32(data, priv->base + FTMAC100_OFFSET_PHYWDATA);
  634. iowrite32(phycr, priv->base + FTMAC100_OFFSET_PHYCR);
  635. for (i = 0; i < 10; i++) {
  636. phycr = ioread32(priv->base + FTMAC100_OFFSET_PHYCR);
  637. if ((phycr & FTMAC100_PHYCR_MIIWR) == 0)
  638. return;
  639. udelay(100);
  640. }
  641. netdev_err(netdev, "mdio write timed out\n");
  642. }
  643. /******************************************************************************
  644. * struct ethtool_ops functions
  645. *****************************************************************************/
  646. static void ftmac100_get_drvinfo(struct net_device *netdev,
  647. struct ethtool_drvinfo *info)
  648. {
  649. strcpy(info->driver, DRV_NAME);
  650. strcpy(info->version, DRV_VERSION);
  651. strcpy(info->bus_info, dev_name(&netdev->dev));
  652. }
  653. static int ftmac100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  654. {
  655. struct ftmac100 *priv = netdev_priv(netdev);
  656. return mii_ethtool_gset(&priv->mii, cmd);
  657. }
  658. static int ftmac100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  659. {
  660. struct ftmac100 *priv = netdev_priv(netdev);
  661. return mii_ethtool_sset(&priv->mii, cmd);
  662. }
  663. static int ftmac100_nway_reset(struct net_device *netdev)
  664. {
  665. struct ftmac100 *priv = netdev_priv(netdev);
  666. return mii_nway_restart(&priv->mii);
  667. }
  668. static u32 ftmac100_get_link(struct net_device *netdev)
  669. {
  670. struct ftmac100 *priv = netdev_priv(netdev);
  671. return mii_link_ok(&priv->mii);
  672. }
  673. static const struct ethtool_ops ftmac100_ethtool_ops = {
  674. .set_settings = ftmac100_set_settings,
  675. .get_settings = ftmac100_get_settings,
  676. .get_drvinfo = ftmac100_get_drvinfo,
  677. .nway_reset = ftmac100_nway_reset,
  678. .get_link = ftmac100_get_link,
  679. };
  680. /******************************************************************************
  681. * interrupt handler
  682. *****************************************************************************/
  683. static irqreturn_t ftmac100_interrupt(int irq, void *dev_id)
  684. {
  685. struct net_device *netdev = dev_id;
  686. struct ftmac100 *priv = netdev_priv(netdev);
  687. if (likely(netif_running(netdev))) {
  688. /* Disable interrupts for polling */
  689. ftmac100_disable_all_int(priv);
  690. napi_schedule(&priv->napi);
  691. }
  692. return IRQ_HANDLED;
  693. }
  694. /******************************************************************************
  695. * struct napi_struct functions
  696. *****************************************************************************/
  697. static int ftmac100_poll(struct napi_struct *napi, int budget)
  698. {
  699. struct ftmac100 *priv = container_of(napi, struct ftmac100, napi);
  700. struct net_device *netdev = priv->netdev;
  701. unsigned int status;
  702. bool completed = true;
  703. int rx = 0;
  704. status = ioread32(priv->base + FTMAC100_OFFSET_ISR);
  705. if (status & (FTMAC100_INT_RPKT_FINISH | FTMAC100_INT_NORXBUF)) {
  706. /*
  707. * FTMAC100_INT_RPKT_FINISH:
  708. * RX DMA has received packets into RX buffer successfully
  709. *
  710. * FTMAC100_INT_NORXBUF:
  711. * RX buffer unavailable
  712. */
  713. bool retry;
  714. do {
  715. retry = ftmac100_rx_packet(priv, &rx);
  716. } while (retry && rx < budget);
  717. if (retry && rx == budget)
  718. completed = false;
  719. }
  720. if (status & (FTMAC100_INT_XPKT_OK | FTMAC100_INT_XPKT_LOST)) {
  721. /*
  722. * FTMAC100_INT_XPKT_OK:
  723. * packet transmitted to ethernet successfully
  724. *
  725. * FTMAC100_INT_XPKT_LOST:
  726. * packet transmitted to ethernet lost due to late
  727. * collision or excessive collision
  728. */
  729. ftmac100_tx_complete(priv);
  730. }
  731. if (status & (FTMAC100_INT_NORXBUF | FTMAC100_INT_RPKT_LOST |
  732. FTMAC100_INT_AHB_ERR | FTMAC100_INT_PHYSTS_CHG)) {
  733. if (net_ratelimit())
  734. netdev_info(netdev, "[ISR] = 0x%x: %s%s%s%s\n", status,
  735. status & FTMAC100_INT_NORXBUF ? "NORXBUF " : "",
  736. status & FTMAC100_INT_RPKT_LOST ? "RPKT_LOST " : "",
  737. status & FTMAC100_INT_AHB_ERR ? "AHB_ERR " : "",
  738. status & FTMAC100_INT_PHYSTS_CHG ? "PHYSTS_CHG" : "");
  739. if (status & FTMAC100_INT_NORXBUF) {
  740. /* RX buffer unavailable */
  741. netdev->stats.rx_over_errors++;
  742. }
  743. if (status & FTMAC100_INT_RPKT_LOST) {
  744. /* received packet lost due to RX FIFO full */
  745. netdev->stats.rx_fifo_errors++;
  746. }
  747. if (status & FTMAC100_INT_PHYSTS_CHG) {
  748. /* PHY link status change */
  749. mii_check_link(&priv->mii);
  750. }
  751. }
  752. if (completed) {
  753. /* stop polling */
  754. napi_complete(napi);
  755. ftmac100_enable_all_int(priv);
  756. }
  757. return rx;
  758. }
  759. /******************************************************************************
  760. * struct net_device_ops functions
  761. *****************************************************************************/
  762. static int ftmac100_open(struct net_device *netdev)
  763. {
  764. struct ftmac100 *priv = netdev_priv(netdev);
  765. int err;
  766. err = ftmac100_alloc_buffers(priv);
  767. if (err) {
  768. netdev_err(netdev, "failed to allocate buffers\n");
  769. goto err_alloc;
  770. }
  771. err = request_irq(priv->irq, ftmac100_interrupt, 0, netdev->name, netdev);
  772. if (err) {
  773. netdev_err(netdev, "failed to request irq %d\n", priv->irq);
  774. goto err_irq;
  775. }
  776. priv->rx_pointer = 0;
  777. priv->tx_clean_pointer = 0;
  778. priv->tx_pointer = 0;
  779. priv->tx_pending = 0;
  780. err = ftmac100_start_hw(priv);
  781. if (err)
  782. goto err_hw;
  783. napi_enable(&priv->napi);
  784. netif_start_queue(netdev);
  785. ftmac100_enable_all_int(priv);
  786. return 0;
  787. err_hw:
  788. free_irq(priv->irq, netdev);
  789. err_irq:
  790. ftmac100_free_buffers(priv);
  791. err_alloc:
  792. return err;
  793. }
  794. static int ftmac100_stop(struct net_device *netdev)
  795. {
  796. struct ftmac100 *priv = netdev_priv(netdev);
  797. ftmac100_disable_all_int(priv);
  798. netif_stop_queue(netdev);
  799. napi_disable(&priv->napi);
  800. ftmac100_stop_hw(priv);
  801. free_irq(priv->irq, netdev);
  802. ftmac100_free_buffers(priv);
  803. return 0;
  804. }
  805. static int ftmac100_hard_start_xmit(struct sk_buff *skb, struct net_device *netdev)
  806. {
  807. struct ftmac100 *priv = netdev_priv(netdev);
  808. dma_addr_t map;
  809. if (unlikely(skb->len > MAX_PKT_SIZE)) {
  810. if (net_ratelimit())
  811. netdev_dbg(netdev, "tx packet too big\n");
  812. netdev->stats.tx_dropped++;
  813. dev_kfree_skb(skb);
  814. return NETDEV_TX_OK;
  815. }
  816. map = dma_map_single(priv->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
  817. if (unlikely(dma_mapping_error(priv->dev, map))) {
  818. /* drop packet */
  819. if (net_ratelimit())
  820. netdev_err(netdev, "map socket buffer failed\n");
  821. netdev->stats.tx_dropped++;
  822. dev_kfree_skb(skb);
  823. return NETDEV_TX_OK;
  824. }
  825. return ftmac100_xmit(priv, skb, map);
  826. }
  827. /* optional */
  828. static int ftmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
  829. {
  830. struct ftmac100 *priv = netdev_priv(netdev);
  831. struct mii_ioctl_data *data = if_mii(ifr);
  832. return generic_mii_ioctl(&priv->mii, data, cmd, NULL);
  833. }
  834. static const struct net_device_ops ftmac100_netdev_ops = {
  835. .ndo_open = ftmac100_open,
  836. .ndo_stop = ftmac100_stop,
  837. .ndo_start_xmit = ftmac100_hard_start_xmit,
  838. .ndo_set_mac_address = eth_mac_addr,
  839. .ndo_validate_addr = eth_validate_addr,
  840. .ndo_do_ioctl = ftmac100_do_ioctl,
  841. };
  842. /******************************************************************************
  843. * struct platform_driver functions
  844. *****************************************************************************/
  845. static int ftmac100_probe(struct platform_device *pdev)
  846. {
  847. struct resource *res;
  848. int irq;
  849. struct net_device *netdev;
  850. struct ftmac100 *priv;
  851. int err;
  852. if (!pdev)
  853. return -ENODEV;
  854. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  855. if (!res)
  856. return -ENXIO;
  857. irq = platform_get_irq(pdev, 0);
  858. if (irq < 0)
  859. return irq;
  860. /* setup net_device */
  861. netdev = alloc_etherdev(sizeof(*priv));
  862. if (!netdev) {
  863. err = -ENOMEM;
  864. goto err_alloc_etherdev;
  865. }
  866. SET_NETDEV_DEV(netdev, &pdev->dev);
  867. SET_ETHTOOL_OPS(netdev, &ftmac100_ethtool_ops);
  868. netdev->netdev_ops = &ftmac100_netdev_ops;
  869. platform_set_drvdata(pdev, netdev);
  870. /* setup private data */
  871. priv = netdev_priv(netdev);
  872. priv->netdev = netdev;
  873. priv->dev = &pdev->dev;
  874. spin_lock_init(&priv->tx_lock);
  875. /* initialize NAPI */
  876. netif_napi_add(netdev, &priv->napi, ftmac100_poll, 64);
  877. /* map io memory */
  878. priv->res = request_mem_region(res->start, resource_size(res),
  879. dev_name(&pdev->dev));
  880. if (!priv->res) {
  881. dev_err(&pdev->dev, "Could not reserve memory region\n");
  882. err = -ENOMEM;
  883. goto err_req_mem;
  884. }
  885. priv->base = ioremap(res->start, resource_size(res));
  886. if (!priv->base) {
  887. dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
  888. err = -EIO;
  889. goto err_ioremap;
  890. }
  891. priv->irq = irq;
  892. /* initialize struct mii_if_info */
  893. priv->mii.phy_id = 0;
  894. priv->mii.phy_id_mask = 0x1f;
  895. priv->mii.reg_num_mask = 0x1f;
  896. priv->mii.dev = netdev;
  897. priv->mii.mdio_read = ftmac100_mdio_read;
  898. priv->mii.mdio_write = ftmac100_mdio_write;
  899. /* register network device */
  900. err = register_netdev(netdev);
  901. if (err) {
  902. dev_err(&pdev->dev, "Failed to register netdev\n");
  903. goto err_register_netdev;
  904. }
  905. netdev_info(netdev, "irq %d, mapped at %p\n", priv->irq, priv->base);
  906. if (!is_valid_ether_addr(netdev->dev_addr)) {
  907. random_ether_addr(netdev->dev_addr);
  908. netdev_info(netdev, "generated random MAC address %pM\n",
  909. netdev->dev_addr);
  910. }
  911. return 0;
  912. err_register_netdev:
  913. iounmap(priv->base);
  914. err_ioremap:
  915. release_resource(priv->res);
  916. err_req_mem:
  917. netif_napi_del(&priv->napi);
  918. platform_set_drvdata(pdev, NULL);
  919. free_netdev(netdev);
  920. err_alloc_etherdev:
  921. return err;
  922. }
  923. static int __exit ftmac100_remove(struct platform_device *pdev)
  924. {
  925. struct net_device *netdev;
  926. struct ftmac100 *priv;
  927. netdev = platform_get_drvdata(pdev);
  928. priv = netdev_priv(netdev);
  929. unregister_netdev(netdev);
  930. iounmap(priv->base);
  931. release_resource(priv->res);
  932. netif_napi_del(&priv->napi);
  933. platform_set_drvdata(pdev, NULL);
  934. free_netdev(netdev);
  935. return 0;
  936. }
  937. static struct platform_driver ftmac100_driver = {
  938. .probe = ftmac100_probe,
  939. .remove = __exit_p(ftmac100_remove),
  940. .driver = {
  941. .name = DRV_NAME,
  942. .owner = THIS_MODULE,
  943. },
  944. };
  945. /******************************************************************************
  946. * initialization / finalization
  947. *****************************************************************************/
  948. static int __init ftmac100_init(void)
  949. {
  950. pr_info("Loading version " DRV_VERSION " ...\n");
  951. return platform_driver_register(&ftmac100_driver);
  952. }
  953. static void __exit ftmac100_exit(void)
  954. {
  955. platform_driver_unregister(&ftmac100_driver);
  956. }
  957. module_init(ftmac100_init);
  958. module_exit(ftmac100_exit);
  959. MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
  960. MODULE_DESCRIPTION("FTMAC100 driver");
  961. MODULE_LICENSE("GPL");