ems_pci.c 10 KB

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  1. /*
  2. * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
  3. * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
  4. * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the version 2 of the GNU General Public License
  8. * as published by the Free Software Foundation
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software Foundation,
  17. * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/netdevice.h>
  23. #include <linux/delay.h>
  24. #include <linux/slab.h>
  25. #include <linux/pci.h>
  26. #include <linux/can/dev.h>
  27. #include <linux/io.h>
  28. #include "sja1000.h"
  29. #define DRV_NAME "ems_pci"
  30. MODULE_AUTHOR("Sebastian Haas <haas@ems-wuenche.com>");
  31. MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-PCI/PCIe/104P CAN cards");
  32. MODULE_SUPPORTED_DEVICE("EMS CPC-PCI/PCIe/104P CAN card");
  33. MODULE_LICENSE("GPL v2");
  34. #define EMS_PCI_V1_MAX_CHAN 2
  35. #define EMS_PCI_V2_MAX_CHAN 4
  36. #define EMS_PCI_MAX_CHAN EMS_PCI_V2_MAX_CHAN
  37. struct ems_pci_card {
  38. int version;
  39. int channels;
  40. struct pci_dev *pci_dev;
  41. struct net_device *net_dev[EMS_PCI_MAX_CHAN];
  42. void __iomem *conf_addr;
  43. void __iomem *base_addr;
  44. };
  45. #define EMS_PCI_CAN_CLOCK (16000000 / 2)
  46. /*
  47. * Register definitions and descriptions are from LinCAN 0.3.3.
  48. *
  49. * PSB4610 PITA-2 bridge control registers
  50. */
  51. #define PITA2_ICR 0x00 /* Interrupt Control Register */
  52. #define PITA2_ICR_INT0 0x00000002 /* [RC] INT0 Active/Clear */
  53. #define PITA2_ICR_INT0_EN 0x00020000 /* [RW] Enable INT0 */
  54. #define PITA2_MISC 0x1c /* Miscellaneous Register */
  55. #define PITA2_MISC_CONFIG 0x04000000 /* Multiplexed parallel interface */
  56. /*
  57. * Register definitions for the PLX 9030
  58. */
  59. #define PLX_ICSR 0x4c /* Interrupt Control/Status register */
  60. #define PLX_ICSR_LINTI1_ENA 0x0001 /* LINTi1 Enable */
  61. #define PLX_ICSR_PCIINT_ENA 0x0040 /* PCI Interrupt Enable */
  62. #define PLX_ICSR_LINTI1_CLR 0x0400 /* Local Edge Triggerable Interrupt Clear */
  63. #define PLX_ICSR_ENA_CLR (PLX_ICSR_LINTI1_ENA | PLX_ICSR_PCIINT_ENA | \
  64. PLX_ICSR_LINTI1_CLR)
  65. /*
  66. * The board configuration is probably following:
  67. * RX1 is connected to ground.
  68. * TX1 is not connected.
  69. * CLKO is not connected.
  70. * Setting the OCR register to 0xDA is a good idea.
  71. * This means normal output mode, push-pull and the correct polarity.
  72. */
  73. #define EMS_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
  74. /*
  75. * In the CDR register, you should set CBP to 1.
  76. * You will probably also want to set the clock divider value to 7
  77. * (meaning direct oscillator output) because the second SJA1000 chip
  78. * is driven by the first one CLKOUT output.
  79. */
  80. #define EMS_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK)
  81. #define EMS_PCI_V1_BASE_BAR 1
  82. #define EMS_PCI_V1_CONF_SIZE 4096 /* size of PITA control area */
  83. #define EMS_PCI_V2_BASE_BAR 2
  84. #define EMS_PCI_V2_CONF_SIZE 128 /* size of PLX control area */
  85. #define EMS_PCI_CAN_BASE_OFFSET 0x400 /* offset where the controllers starts */
  86. #define EMS_PCI_CAN_CTRL_SIZE 0x200 /* memory size for each controller */
  87. #define EMS_PCI_BASE_SIZE 4096 /* size of controller area */
  88. static DEFINE_PCI_DEVICE_TABLE(ems_pci_tbl) = {
  89. /* CPC-PCI v1 */
  90. {PCI_VENDOR_ID_SIEMENS, 0x2104, PCI_ANY_ID, PCI_ANY_ID,},
  91. /* CPC-PCI v2 */
  92. {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4000},
  93. /* CPC-104P v2 */
  94. {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4002},
  95. {0,}
  96. };
  97. MODULE_DEVICE_TABLE(pci, ems_pci_tbl);
  98. /*
  99. * Helper to read internal registers from card logic (not CAN)
  100. */
  101. static u8 ems_pci_v1_readb(struct ems_pci_card *card, unsigned int port)
  102. {
  103. return readb(card->base_addr + (port * 4));
  104. }
  105. static u8 ems_pci_v1_read_reg(const struct sja1000_priv *priv, int port)
  106. {
  107. return readb(priv->reg_base + (port * 4));
  108. }
  109. static void ems_pci_v1_write_reg(const struct sja1000_priv *priv,
  110. int port, u8 val)
  111. {
  112. writeb(val, priv->reg_base + (port * 4));
  113. }
  114. static void ems_pci_v1_post_irq(const struct sja1000_priv *priv)
  115. {
  116. struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
  117. /* reset int flag of pita */
  118. writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
  119. card->conf_addr + PITA2_ICR);
  120. }
  121. static u8 ems_pci_v2_read_reg(const struct sja1000_priv *priv, int port)
  122. {
  123. return readb(priv->reg_base + port);
  124. }
  125. static void ems_pci_v2_write_reg(const struct sja1000_priv *priv,
  126. int port, u8 val)
  127. {
  128. writeb(val, priv->reg_base + port);
  129. }
  130. static void ems_pci_v2_post_irq(const struct sja1000_priv *priv)
  131. {
  132. struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
  133. writel(PLX_ICSR_ENA_CLR, card->conf_addr + PLX_ICSR);
  134. }
  135. /*
  136. * Check if a CAN controller is present at the specified location
  137. * by trying to set 'em into the PeliCAN mode
  138. */
  139. static inline int ems_pci_check_chan(const struct sja1000_priv *priv)
  140. {
  141. unsigned char res;
  142. /* Make sure SJA1000 is in reset mode */
  143. priv->write_reg(priv, REG_MOD, 1);
  144. priv->write_reg(priv, REG_CDR, CDR_PELICAN);
  145. /* read reset-values */
  146. res = priv->read_reg(priv, REG_CDR);
  147. if (res == CDR_PELICAN)
  148. return 1;
  149. return 0;
  150. }
  151. static void ems_pci_del_card(struct pci_dev *pdev)
  152. {
  153. struct ems_pci_card *card = pci_get_drvdata(pdev);
  154. struct net_device *dev;
  155. int i = 0;
  156. for (i = 0; i < card->channels; i++) {
  157. dev = card->net_dev[i];
  158. if (!dev)
  159. continue;
  160. dev_info(&pdev->dev, "Removing %s.\n", dev->name);
  161. unregister_sja1000dev(dev);
  162. free_sja1000dev(dev);
  163. }
  164. if (card->base_addr != NULL)
  165. pci_iounmap(card->pci_dev, card->base_addr);
  166. if (card->conf_addr != NULL)
  167. pci_iounmap(card->pci_dev, card->conf_addr);
  168. kfree(card);
  169. pci_disable_device(pdev);
  170. pci_set_drvdata(pdev, NULL);
  171. }
  172. static void ems_pci_card_reset(struct ems_pci_card *card)
  173. {
  174. /* Request board reset */
  175. writeb(0, card->base_addr);
  176. }
  177. /*
  178. * Probe PCI device for EMS CAN signature and register each available
  179. * CAN channel to SJA1000 Socket-CAN subsystem.
  180. */
  181. static int __devinit ems_pci_add_card(struct pci_dev *pdev,
  182. const struct pci_device_id *ent)
  183. {
  184. struct sja1000_priv *priv;
  185. struct net_device *dev;
  186. struct ems_pci_card *card;
  187. int max_chan, conf_size, base_bar;
  188. int err, i;
  189. /* Enabling PCI device */
  190. if (pci_enable_device(pdev) < 0) {
  191. dev_err(&pdev->dev, "Enabling PCI device failed\n");
  192. return -ENODEV;
  193. }
  194. /* Allocating card structures to hold addresses, ... */
  195. card = kzalloc(sizeof(struct ems_pci_card), GFP_KERNEL);
  196. if (card == NULL) {
  197. dev_err(&pdev->dev, "Unable to allocate memory\n");
  198. pci_disable_device(pdev);
  199. return -ENOMEM;
  200. }
  201. pci_set_drvdata(pdev, card);
  202. card->pci_dev = pdev;
  203. card->channels = 0;
  204. if (pdev->vendor == PCI_VENDOR_ID_PLX) {
  205. card->version = 2; /* CPC-PCI v2 */
  206. max_chan = EMS_PCI_V2_MAX_CHAN;
  207. base_bar = EMS_PCI_V2_BASE_BAR;
  208. conf_size = EMS_PCI_V2_CONF_SIZE;
  209. } else {
  210. card->version = 1; /* CPC-PCI v1 */
  211. max_chan = EMS_PCI_V1_MAX_CHAN;
  212. base_bar = EMS_PCI_V1_BASE_BAR;
  213. conf_size = EMS_PCI_V1_CONF_SIZE;
  214. }
  215. /* Remap configuration space and controller memory area */
  216. card->conf_addr = pci_iomap(pdev, 0, conf_size);
  217. if (card->conf_addr == NULL) {
  218. err = -ENOMEM;
  219. goto failure_cleanup;
  220. }
  221. card->base_addr = pci_iomap(pdev, base_bar, EMS_PCI_BASE_SIZE);
  222. if (card->base_addr == NULL) {
  223. err = -ENOMEM;
  224. goto failure_cleanup;
  225. }
  226. if (card->version == 1) {
  227. /* Configure PITA-2 parallel interface (enable MUX) */
  228. writel(PITA2_MISC_CONFIG, card->conf_addr + PITA2_MISC);
  229. /* Check for unique EMS CAN signature */
  230. if (ems_pci_v1_readb(card, 0) != 0x55 ||
  231. ems_pci_v1_readb(card, 1) != 0xAA ||
  232. ems_pci_v1_readb(card, 2) != 0x01 ||
  233. ems_pci_v1_readb(card, 3) != 0xCB ||
  234. ems_pci_v1_readb(card, 4) != 0x11) {
  235. dev_err(&pdev->dev,
  236. "Not EMS Dr. Thomas Wuensche interface\n");
  237. err = -ENODEV;
  238. goto failure_cleanup;
  239. }
  240. }
  241. ems_pci_card_reset(card);
  242. /* Detect available channels */
  243. for (i = 0; i < max_chan; i++) {
  244. dev = alloc_sja1000dev(0);
  245. if (dev == NULL) {
  246. err = -ENOMEM;
  247. goto failure_cleanup;
  248. }
  249. card->net_dev[i] = dev;
  250. priv = netdev_priv(dev);
  251. priv->priv = card;
  252. priv->irq_flags = IRQF_SHARED;
  253. dev->irq = pdev->irq;
  254. priv->reg_base = card->base_addr + EMS_PCI_CAN_BASE_OFFSET
  255. + (i * EMS_PCI_CAN_CTRL_SIZE);
  256. if (card->version == 1) {
  257. priv->read_reg = ems_pci_v1_read_reg;
  258. priv->write_reg = ems_pci_v1_write_reg;
  259. priv->post_irq = ems_pci_v1_post_irq;
  260. } else {
  261. priv->read_reg = ems_pci_v2_read_reg;
  262. priv->write_reg = ems_pci_v2_write_reg;
  263. priv->post_irq = ems_pci_v2_post_irq;
  264. }
  265. /* Check if channel is present */
  266. if (ems_pci_check_chan(priv)) {
  267. priv->can.clock.freq = EMS_PCI_CAN_CLOCK;
  268. priv->ocr = EMS_PCI_OCR;
  269. priv->cdr = EMS_PCI_CDR;
  270. SET_NETDEV_DEV(dev, &pdev->dev);
  271. if (card->version == 1)
  272. /* reset int flag of pita */
  273. writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
  274. card->conf_addr + PITA2_ICR);
  275. else
  276. /* enable IRQ in PLX 9030 */
  277. writel(PLX_ICSR_ENA_CLR,
  278. card->conf_addr + PLX_ICSR);
  279. /* Register SJA1000 device */
  280. err = register_sja1000dev(dev);
  281. if (err) {
  282. dev_err(&pdev->dev, "Registering device failed "
  283. "(err=%d)\n", err);
  284. free_sja1000dev(dev);
  285. goto failure_cleanup;
  286. }
  287. card->channels++;
  288. dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d\n",
  289. i + 1, priv->reg_base, dev->irq);
  290. } else {
  291. free_sja1000dev(dev);
  292. }
  293. }
  294. return 0;
  295. failure_cleanup:
  296. dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
  297. ems_pci_del_card(pdev);
  298. return err;
  299. }
  300. static struct pci_driver ems_pci_driver = {
  301. .name = DRV_NAME,
  302. .id_table = ems_pci_tbl,
  303. .probe = ems_pci_add_card,
  304. .remove = ems_pci_del_card,
  305. };
  306. static int __init ems_pci_init(void)
  307. {
  308. return pci_register_driver(&ems_pci_driver);
  309. }
  310. static void __exit ems_pci_exit(void)
  311. {
  312. pci_unregister_driver(&ems_pci_driver);
  313. }
  314. module_init(ems_pci_init);
  315. module_exit(ems_pci_exit);