janz-ican3.c 44 KB

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  1. /*
  2. * Janz MODULbus VMOD-ICAN3 CAN Interface Driver
  3. *
  4. * Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/init.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/delay.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/netdevice.h>
  18. #include <linux/can.h>
  19. #include <linux/can/dev.h>
  20. #include <linux/can/error.h>
  21. #include <linux/mfd/janz.h>
  22. /* the DPM has 64k of memory, organized into 256x 256 byte pages */
  23. #define DPM_NUM_PAGES 256
  24. #define DPM_PAGE_SIZE 256
  25. #define DPM_PAGE_ADDR(p) ((p) * DPM_PAGE_SIZE)
  26. /* JANZ ICAN3 "old-style" host interface queue page numbers */
  27. #define QUEUE_OLD_CONTROL 0
  28. #define QUEUE_OLD_RB0 1
  29. #define QUEUE_OLD_RB1 2
  30. #define QUEUE_OLD_WB0 3
  31. #define QUEUE_OLD_WB1 4
  32. /* Janz ICAN3 "old-style" host interface control registers */
  33. #define MSYNC_PEER 0x00 /* ICAN only */
  34. #define MSYNC_LOCL 0x01 /* host only */
  35. #define TARGET_RUNNING 0x02
  36. #define MSYNC_RB0 0x01
  37. #define MSYNC_RB1 0x02
  38. #define MSYNC_RBLW 0x04
  39. #define MSYNC_RB_MASK (MSYNC_RB0 | MSYNC_RB1)
  40. #define MSYNC_WB0 0x10
  41. #define MSYNC_WB1 0x20
  42. #define MSYNC_WBLW 0x40
  43. #define MSYNC_WB_MASK (MSYNC_WB0 | MSYNC_WB1)
  44. /* Janz ICAN3 "new-style" host interface queue page numbers */
  45. #define QUEUE_TOHOST 5
  46. #define QUEUE_FROMHOST_MID 6
  47. #define QUEUE_FROMHOST_HIGH 7
  48. #define QUEUE_FROMHOST_LOW 8
  49. /* The first free page in the DPM is #9 */
  50. #define DPM_FREE_START 9
  51. /* Janz ICAN3 "new-style" and "fast" host interface descriptor flags */
  52. #define DESC_VALID 0x80
  53. #define DESC_WRAP 0x40
  54. #define DESC_INTERRUPT 0x20
  55. #define DESC_IVALID 0x10
  56. #define DESC_LEN(len) (len)
  57. /* Janz ICAN3 Firmware Messages */
  58. #define MSG_CONNECTI 0x02
  59. #define MSG_DISCONNECT 0x03
  60. #define MSG_IDVERS 0x04
  61. #define MSG_MSGLOST 0x05
  62. #define MSG_NEWHOSTIF 0x08
  63. #define MSG_INQUIRY 0x0a
  64. #define MSG_SETAFILMASK 0x10
  65. #define MSG_INITFDPMQUEUE 0x11
  66. #define MSG_HWCONF 0x12
  67. #define MSG_FMSGLOST 0x15
  68. #define MSG_CEVTIND 0x37
  69. #define MSG_CBTRREQ 0x41
  70. #define MSG_COFFREQ 0x42
  71. #define MSG_CONREQ 0x43
  72. #define MSG_CCONFREQ 0x47
  73. /*
  74. * Janz ICAN3 CAN Inquiry Message Types
  75. *
  76. * NOTE: there appears to be a firmware bug here. You must send
  77. * NOTE: INQUIRY_STATUS and expect to receive an INQUIRY_EXTENDED
  78. * NOTE: response. The controller never responds to a message with
  79. * NOTE: the INQUIRY_EXTENDED subspec :(
  80. */
  81. #define INQUIRY_STATUS 0x00
  82. #define INQUIRY_TERMINATION 0x01
  83. #define INQUIRY_EXTENDED 0x04
  84. /* Janz ICAN3 CAN Set Acceptance Filter Mask Message Types */
  85. #define SETAFILMASK_REJECT 0x00
  86. #define SETAFILMASK_FASTIF 0x02
  87. /* Janz ICAN3 CAN Hardware Configuration Message Types */
  88. #define HWCONF_TERMINATE_ON 0x01
  89. #define HWCONF_TERMINATE_OFF 0x00
  90. /* Janz ICAN3 CAN Event Indication Message Types */
  91. #define CEVTIND_EI 0x01
  92. #define CEVTIND_DOI 0x02
  93. #define CEVTIND_LOST 0x04
  94. #define CEVTIND_FULL 0x08
  95. #define CEVTIND_BEI 0x10
  96. #define CEVTIND_CHIP_SJA1000 0x02
  97. #define ICAN3_BUSERR_QUOTA_MAX 255
  98. /* Janz ICAN3 CAN Frame Conversion */
  99. #define ICAN3_ECHO 0x10
  100. #define ICAN3_EFF_RTR 0x40
  101. #define ICAN3_SFF_RTR 0x10
  102. #define ICAN3_EFF 0x80
  103. #define ICAN3_CAN_TYPE_MASK 0x0f
  104. #define ICAN3_CAN_TYPE_SFF 0x00
  105. #define ICAN3_CAN_TYPE_EFF 0x01
  106. #define ICAN3_CAN_DLC_MASK 0x0f
  107. /*
  108. * SJA1000 Status and Error Register Definitions
  109. *
  110. * Copied from drivers/net/can/sja1000/sja1000.h
  111. */
  112. /* status register content */
  113. #define SR_BS 0x80
  114. #define SR_ES 0x40
  115. #define SR_TS 0x20
  116. #define SR_RS 0x10
  117. #define SR_TCS 0x08
  118. #define SR_TBS 0x04
  119. #define SR_DOS 0x02
  120. #define SR_RBS 0x01
  121. #define SR_CRIT (SR_BS|SR_ES)
  122. /* ECC register */
  123. #define ECC_SEG 0x1F
  124. #define ECC_DIR 0x20
  125. #define ECC_ERR 6
  126. #define ECC_BIT 0x00
  127. #define ECC_FORM 0x40
  128. #define ECC_STUFF 0x80
  129. #define ECC_MASK 0xc0
  130. /* Number of buffers for use in the "new-style" host interface */
  131. #define ICAN3_NEW_BUFFERS 16
  132. /* Number of buffers for use in the "fast" host interface */
  133. #define ICAN3_TX_BUFFERS 512
  134. #define ICAN3_RX_BUFFERS 1024
  135. /* SJA1000 Clock Input */
  136. #define ICAN3_CAN_CLOCK 8000000
  137. /* Driver Name */
  138. #define DRV_NAME "janz-ican3"
  139. /* DPM Control Registers -- starts at offset 0x100 in the MODULbus registers */
  140. struct ican3_dpm_control {
  141. /* window address register */
  142. u8 window_address;
  143. u8 unused1;
  144. /*
  145. * Read access: clear interrupt from microcontroller
  146. * Write access: send interrupt to microcontroller
  147. */
  148. u8 interrupt;
  149. u8 unused2;
  150. /* write-only: reset all hardware on the module */
  151. u8 hwreset;
  152. u8 unused3;
  153. /* write-only: generate an interrupt to the TPU */
  154. u8 tpuinterrupt;
  155. };
  156. struct ican3_dev {
  157. /* must be the first member */
  158. struct can_priv can;
  159. /* CAN network device */
  160. struct net_device *ndev;
  161. struct napi_struct napi;
  162. /* Device for printing */
  163. struct device *dev;
  164. /* module number */
  165. unsigned int num;
  166. /* base address of registers and IRQ */
  167. struct janz_cmodio_onboard_regs __iomem *ctrl;
  168. struct ican3_dpm_control __iomem *dpmctrl;
  169. void __iomem *dpm;
  170. int irq;
  171. /* CAN bus termination status */
  172. struct completion termination_comp;
  173. bool termination_enabled;
  174. /* CAN bus error status registers */
  175. struct completion buserror_comp;
  176. struct can_berr_counter bec;
  177. /* old and new style host interface */
  178. unsigned int iftype;
  179. /*
  180. * Any function which changes the current DPM page must hold this
  181. * lock while it is performing data accesses. This ensures that the
  182. * function will not be preempted and end up reading data from a
  183. * different DPM page than it expects.
  184. */
  185. spinlock_t lock;
  186. /* new host interface */
  187. unsigned int rx_int;
  188. unsigned int rx_num;
  189. unsigned int tx_num;
  190. /* fast host interface */
  191. unsigned int fastrx_start;
  192. unsigned int fastrx_int;
  193. unsigned int fastrx_num;
  194. unsigned int fasttx_start;
  195. unsigned int fasttx_num;
  196. /* first free DPM page */
  197. unsigned int free_page;
  198. };
  199. struct ican3_msg {
  200. u8 control;
  201. u8 spec;
  202. __le16 len;
  203. u8 data[252];
  204. };
  205. struct ican3_new_desc {
  206. u8 control;
  207. u8 pointer;
  208. };
  209. struct ican3_fast_desc {
  210. u8 control;
  211. u8 command;
  212. u8 data[14];
  213. };
  214. /* write to the window basic address register */
  215. static inline void ican3_set_page(struct ican3_dev *mod, unsigned int page)
  216. {
  217. BUG_ON(page >= DPM_NUM_PAGES);
  218. iowrite8(page, &mod->dpmctrl->window_address);
  219. }
  220. /*
  221. * ICAN3 "old-style" host interface
  222. */
  223. /*
  224. * Receive a message from the ICAN3 "old-style" firmware interface
  225. *
  226. * LOCKING: must hold mod->lock
  227. *
  228. * returns 0 on success, -ENOMEM when no message exists
  229. */
  230. static int ican3_old_recv_msg(struct ican3_dev *mod, struct ican3_msg *msg)
  231. {
  232. unsigned int mbox, mbox_page;
  233. u8 locl, peer, xord;
  234. /* get the MSYNC registers */
  235. ican3_set_page(mod, QUEUE_OLD_CONTROL);
  236. peer = ioread8(mod->dpm + MSYNC_PEER);
  237. locl = ioread8(mod->dpm + MSYNC_LOCL);
  238. xord = locl ^ peer;
  239. if ((xord & MSYNC_RB_MASK) == 0x00) {
  240. dev_dbg(mod->dev, "no mbox for reading\n");
  241. return -ENOMEM;
  242. }
  243. /* find the first free mbox to read */
  244. if ((xord & MSYNC_RB_MASK) == MSYNC_RB_MASK)
  245. mbox = (xord & MSYNC_RBLW) ? MSYNC_RB0 : MSYNC_RB1;
  246. else
  247. mbox = (xord & MSYNC_RB0) ? MSYNC_RB0 : MSYNC_RB1;
  248. /* copy the message */
  249. mbox_page = (mbox == MSYNC_RB0) ? QUEUE_OLD_RB0 : QUEUE_OLD_RB1;
  250. ican3_set_page(mod, mbox_page);
  251. memcpy_fromio(msg, mod->dpm, sizeof(*msg));
  252. /*
  253. * notify the firmware that the read buffer is available
  254. * for it to fill again
  255. */
  256. locl ^= mbox;
  257. ican3_set_page(mod, QUEUE_OLD_CONTROL);
  258. iowrite8(locl, mod->dpm + MSYNC_LOCL);
  259. return 0;
  260. }
  261. /*
  262. * Send a message through the "old-style" firmware interface
  263. *
  264. * LOCKING: must hold mod->lock
  265. *
  266. * returns 0 on success, -ENOMEM when no free space exists
  267. */
  268. static int ican3_old_send_msg(struct ican3_dev *mod, struct ican3_msg *msg)
  269. {
  270. unsigned int mbox, mbox_page;
  271. u8 locl, peer, xord;
  272. /* get the MSYNC registers */
  273. ican3_set_page(mod, QUEUE_OLD_CONTROL);
  274. peer = ioread8(mod->dpm + MSYNC_PEER);
  275. locl = ioread8(mod->dpm + MSYNC_LOCL);
  276. xord = locl ^ peer;
  277. if ((xord & MSYNC_WB_MASK) == MSYNC_WB_MASK) {
  278. dev_err(mod->dev, "no mbox for writing\n");
  279. return -ENOMEM;
  280. }
  281. /* calculate a free mbox to use */
  282. mbox = (xord & MSYNC_WB0) ? MSYNC_WB1 : MSYNC_WB0;
  283. /* copy the message to the DPM */
  284. mbox_page = (mbox == MSYNC_WB0) ? QUEUE_OLD_WB0 : QUEUE_OLD_WB1;
  285. ican3_set_page(mod, mbox_page);
  286. memcpy_toio(mod->dpm, msg, sizeof(*msg));
  287. locl ^= mbox;
  288. if (mbox == MSYNC_WB1)
  289. locl |= MSYNC_WBLW;
  290. ican3_set_page(mod, QUEUE_OLD_CONTROL);
  291. iowrite8(locl, mod->dpm + MSYNC_LOCL);
  292. return 0;
  293. }
  294. /*
  295. * ICAN3 "new-style" Host Interface Setup
  296. */
  297. static void __devinit ican3_init_new_host_interface(struct ican3_dev *mod)
  298. {
  299. struct ican3_new_desc desc;
  300. unsigned long flags;
  301. void __iomem *dst;
  302. int i;
  303. spin_lock_irqsave(&mod->lock, flags);
  304. /* setup the internal datastructures for RX */
  305. mod->rx_num = 0;
  306. mod->rx_int = 0;
  307. /* tohost queue descriptors are in page 5 */
  308. ican3_set_page(mod, QUEUE_TOHOST);
  309. dst = mod->dpm;
  310. /* initialize the tohost (rx) queue descriptors: pages 9-24 */
  311. for (i = 0; i < ICAN3_NEW_BUFFERS; i++) {
  312. desc.control = DESC_INTERRUPT | DESC_LEN(1); /* I L=1 */
  313. desc.pointer = mod->free_page;
  314. /* set wrap flag on last buffer */
  315. if (i == ICAN3_NEW_BUFFERS - 1)
  316. desc.control |= DESC_WRAP;
  317. memcpy_toio(dst, &desc, sizeof(desc));
  318. dst += sizeof(desc);
  319. mod->free_page++;
  320. }
  321. /* fromhost (tx) mid queue descriptors are in page 6 */
  322. ican3_set_page(mod, QUEUE_FROMHOST_MID);
  323. dst = mod->dpm;
  324. /* setup the internal datastructures for TX */
  325. mod->tx_num = 0;
  326. /* initialize the fromhost mid queue descriptors: pages 25-40 */
  327. for (i = 0; i < ICAN3_NEW_BUFFERS; i++) {
  328. desc.control = DESC_VALID | DESC_LEN(1); /* V L=1 */
  329. desc.pointer = mod->free_page;
  330. /* set wrap flag on last buffer */
  331. if (i == ICAN3_NEW_BUFFERS - 1)
  332. desc.control |= DESC_WRAP;
  333. memcpy_toio(dst, &desc, sizeof(desc));
  334. dst += sizeof(desc);
  335. mod->free_page++;
  336. }
  337. /* fromhost hi queue descriptors are in page 7 */
  338. ican3_set_page(mod, QUEUE_FROMHOST_HIGH);
  339. dst = mod->dpm;
  340. /* initialize only a single buffer in the fromhost hi queue (unused) */
  341. desc.control = DESC_VALID | DESC_WRAP | DESC_LEN(1); /* VW L=1 */
  342. desc.pointer = mod->free_page;
  343. memcpy_toio(dst, &desc, sizeof(desc));
  344. mod->free_page++;
  345. /* fromhost low queue descriptors are in page 8 */
  346. ican3_set_page(mod, QUEUE_FROMHOST_LOW);
  347. dst = mod->dpm;
  348. /* initialize only a single buffer in the fromhost low queue (unused) */
  349. desc.control = DESC_VALID | DESC_WRAP | DESC_LEN(1); /* VW L=1 */
  350. desc.pointer = mod->free_page;
  351. memcpy_toio(dst, &desc, sizeof(desc));
  352. mod->free_page++;
  353. spin_unlock_irqrestore(&mod->lock, flags);
  354. }
  355. /*
  356. * ICAN3 Fast Host Interface Setup
  357. */
  358. static void __devinit ican3_init_fast_host_interface(struct ican3_dev *mod)
  359. {
  360. struct ican3_fast_desc desc;
  361. unsigned long flags;
  362. unsigned int addr;
  363. void __iomem *dst;
  364. int i;
  365. spin_lock_irqsave(&mod->lock, flags);
  366. /* save the start recv page */
  367. mod->fastrx_start = mod->free_page;
  368. mod->fastrx_num = 0;
  369. mod->fastrx_int = 0;
  370. /* build a single fast tohost queue descriptor */
  371. memset(&desc, 0, sizeof(desc));
  372. desc.control = 0x00;
  373. desc.command = 1;
  374. /* build the tohost queue descriptor ring in memory */
  375. addr = 0;
  376. for (i = 0; i < ICAN3_RX_BUFFERS; i++) {
  377. /* set the wrap bit on the last buffer */
  378. if (i == ICAN3_RX_BUFFERS - 1)
  379. desc.control |= DESC_WRAP;
  380. /* switch to the correct page */
  381. ican3_set_page(mod, mod->free_page);
  382. /* copy the descriptor to the DPM */
  383. dst = mod->dpm + addr;
  384. memcpy_toio(dst, &desc, sizeof(desc));
  385. addr += sizeof(desc);
  386. /* move to the next page if necessary */
  387. if (addr >= DPM_PAGE_SIZE) {
  388. addr = 0;
  389. mod->free_page++;
  390. }
  391. }
  392. /* make sure we page-align the next queue */
  393. if (addr != 0)
  394. mod->free_page++;
  395. /* save the start xmit page */
  396. mod->fasttx_start = mod->free_page;
  397. mod->fasttx_num = 0;
  398. /* build a single fast fromhost queue descriptor */
  399. memset(&desc, 0, sizeof(desc));
  400. desc.control = DESC_VALID;
  401. desc.command = 1;
  402. /* build the fromhost queue descriptor ring in memory */
  403. addr = 0;
  404. for (i = 0; i < ICAN3_TX_BUFFERS; i++) {
  405. /* set the wrap bit on the last buffer */
  406. if (i == ICAN3_TX_BUFFERS - 1)
  407. desc.control |= DESC_WRAP;
  408. /* switch to the correct page */
  409. ican3_set_page(mod, mod->free_page);
  410. /* copy the descriptor to the DPM */
  411. dst = mod->dpm + addr;
  412. memcpy_toio(dst, &desc, sizeof(desc));
  413. addr += sizeof(desc);
  414. /* move to the next page if necessary */
  415. if (addr >= DPM_PAGE_SIZE) {
  416. addr = 0;
  417. mod->free_page++;
  418. }
  419. }
  420. spin_unlock_irqrestore(&mod->lock, flags);
  421. }
  422. /*
  423. * ICAN3 "new-style" Host Interface Message Helpers
  424. */
  425. /*
  426. * LOCKING: must hold mod->lock
  427. */
  428. static int ican3_new_send_msg(struct ican3_dev *mod, struct ican3_msg *msg)
  429. {
  430. struct ican3_new_desc desc;
  431. void __iomem *desc_addr = mod->dpm + (mod->tx_num * sizeof(desc));
  432. /* switch to the fromhost mid queue, and read the buffer descriptor */
  433. ican3_set_page(mod, QUEUE_FROMHOST_MID);
  434. memcpy_fromio(&desc, desc_addr, sizeof(desc));
  435. if (!(desc.control & DESC_VALID)) {
  436. dev_dbg(mod->dev, "%s: no free buffers\n", __func__);
  437. return -ENOMEM;
  438. }
  439. /* switch to the data page, copy the data */
  440. ican3_set_page(mod, desc.pointer);
  441. memcpy_toio(mod->dpm, msg, sizeof(*msg));
  442. /* switch back to the descriptor, set the valid bit, write it back */
  443. ican3_set_page(mod, QUEUE_FROMHOST_MID);
  444. desc.control ^= DESC_VALID;
  445. memcpy_toio(desc_addr, &desc, sizeof(desc));
  446. /* update the tx number */
  447. mod->tx_num = (desc.control & DESC_WRAP) ? 0 : (mod->tx_num + 1);
  448. return 0;
  449. }
  450. /*
  451. * LOCKING: must hold mod->lock
  452. */
  453. static int ican3_new_recv_msg(struct ican3_dev *mod, struct ican3_msg *msg)
  454. {
  455. struct ican3_new_desc desc;
  456. void __iomem *desc_addr = mod->dpm + (mod->rx_num * sizeof(desc));
  457. /* switch to the tohost queue, and read the buffer descriptor */
  458. ican3_set_page(mod, QUEUE_TOHOST);
  459. memcpy_fromio(&desc, desc_addr, sizeof(desc));
  460. if (!(desc.control & DESC_VALID)) {
  461. dev_dbg(mod->dev, "%s: no buffers to recv\n", __func__);
  462. return -ENOMEM;
  463. }
  464. /* switch to the data page, copy the data */
  465. ican3_set_page(mod, desc.pointer);
  466. memcpy_fromio(msg, mod->dpm, sizeof(*msg));
  467. /* switch back to the descriptor, toggle the valid bit, write it back */
  468. ican3_set_page(mod, QUEUE_TOHOST);
  469. desc.control ^= DESC_VALID;
  470. memcpy_toio(desc_addr, &desc, sizeof(desc));
  471. /* update the rx number */
  472. mod->rx_num = (desc.control & DESC_WRAP) ? 0 : (mod->rx_num + 1);
  473. return 0;
  474. }
  475. /*
  476. * Message Send / Recv Helpers
  477. */
  478. static int ican3_send_msg(struct ican3_dev *mod, struct ican3_msg *msg)
  479. {
  480. unsigned long flags;
  481. int ret;
  482. spin_lock_irqsave(&mod->lock, flags);
  483. if (mod->iftype == 0)
  484. ret = ican3_old_send_msg(mod, msg);
  485. else
  486. ret = ican3_new_send_msg(mod, msg);
  487. spin_unlock_irqrestore(&mod->lock, flags);
  488. return ret;
  489. }
  490. static int ican3_recv_msg(struct ican3_dev *mod, struct ican3_msg *msg)
  491. {
  492. unsigned long flags;
  493. int ret;
  494. spin_lock_irqsave(&mod->lock, flags);
  495. if (mod->iftype == 0)
  496. ret = ican3_old_recv_msg(mod, msg);
  497. else
  498. ret = ican3_new_recv_msg(mod, msg);
  499. spin_unlock_irqrestore(&mod->lock, flags);
  500. return ret;
  501. }
  502. /*
  503. * Quick Pre-constructed Messages
  504. */
  505. static int __devinit ican3_msg_connect(struct ican3_dev *mod)
  506. {
  507. struct ican3_msg msg;
  508. memset(&msg, 0, sizeof(msg));
  509. msg.spec = MSG_CONNECTI;
  510. msg.len = cpu_to_le16(0);
  511. return ican3_send_msg(mod, &msg);
  512. }
  513. static int __devexit ican3_msg_disconnect(struct ican3_dev *mod)
  514. {
  515. struct ican3_msg msg;
  516. memset(&msg, 0, sizeof(msg));
  517. msg.spec = MSG_DISCONNECT;
  518. msg.len = cpu_to_le16(0);
  519. return ican3_send_msg(mod, &msg);
  520. }
  521. static int __devinit ican3_msg_newhostif(struct ican3_dev *mod)
  522. {
  523. struct ican3_msg msg;
  524. int ret;
  525. memset(&msg, 0, sizeof(msg));
  526. msg.spec = MSG_NEWHOSTIF;
  527. msg.len = cpu_to_le16(0);
  528. /* If we're not using the old interface, switching seems bogus */
  529. WARN_ON(mod->iftype != 0);
  530. ret = ican3_send_msg(mod, &msg);
  531. if (ret)
  532. return ret;
  533. /* mark the module as using the new host interface */
  534. mod->iftype = 1;
  535. return 0;
  536. }
  537. static int __devinit ican3_msg_fasthostif(struct ican3_dev *mod)
  538. {
  539. struct ican3_msg msg;
  540. unsigned int addr;
  541. memset(&msg, 0, sizeof(msg));
  542. msg.spec = MSG_INITFDPMQUEUE;
  543. msg.len = cpu_to_le16(8);
  544. /* write the tohost queue start address */
  545. addr = DPM_PAGE_ADDR(mod->fastrx_start);
  546. msg.data[0] = addr & 0xff;
  547. msg.data[1] = (addr >> 8) & 0xff;
  548. msg.data[2] = (addr >> 16) & 0xff;
  549. msg.data[3] = (addr >> 24) & 0xff;
  550. /* write the fromhost queue start address */
  551. addr = DPM_PAGE_ADDR(mod->fasttx_start);
  552. msg.data[4] = addr & 0xff;
  553. msg.data[5] = (addr >> 8) & 0xff;
  554. msg.data[6] = (addr >> 16) & 0xff;
  555. msg.data[7] = (addr >> 24) & 0xff;
  556. /* If we're not using the new interface yet, we cannot do this */
  557. WARN_ON(mod->iftype != 1);
  558. return ican3_send_msg(mod, &msg);
  559. }
  560. /*
  561. * Setup the CAN filter to either accept or reject all
  562. * messages from the CAN bus.
  563. */
  564. static int __devinit ican3_set_id_filter(struct ican3_dev *mod, bool accept)
  565. {
  566. struct ican3_msg msg;
  567. int ret;
  568. /* Standard Frame Format */
  569. memset(&msg, 0, sizeof(msg));
  570. msg.spec = MSG_SETAFILMASK;
  571. msg.len = cpu_to_le16(5);
  572. msg.data[0] = 0x00; /* IDLo LSB */
  573. msg.data[1] = 0x00; /* IDLo MSB */
  574. msg.data[2] = 0xff; /* IDHi LSB */
  575. msg.data[3] = 0x07; /* IDHi MSB */
  576. /* accept all frames for fast host if, or reject all frames */
  577. msg.data[4] = accept ? SETAFILMASK_FASTIF : SETAFILMASK_REJECT;
  578. ret = ican3_send_msg(mod, &msg);
  579. if (ret)
  580. return ret;
  581. /* Extended Frame Format */
  582. memset(&msg, 0, sizeof(msg));
  583. msg.spec = MSG_SETAFILMASK;
  584. msg.len = cpu_to_le16(13);
  585. msg.data[0] = 0; /* MUX = 0 */
  586. msg.data[1] = 0x00; /* IDLo LSB */
  587. msg.data[2] = 0x00;
  588. msg.data[3] = 0x00;
  589. msg.data[4] = 0x20; /* IDLo MSB */
  590. msg.data[5] = 0xff; /* IDHi LSB */
  591. msg.data[6] = 0xff;
  592. msg.data[7] = 0xff;
  593. msg.data[8] = 0x3f; /* IDHi MSB */
  594. /* accept all frames for fast host if, or reject all frames */
  595. msg.data[9] = accept ? SETAFILMASK_FASTIF : SETAFILMASK_REJECT;
  596. return ican3_send_msg(mod, &msg);
  597. }
  598. /*
  599. * Bring the CAN bus online or offline
  600. */
  601. static int ican3_set_bus_state(struct ican3_dev *mod, bool on)
  602. {
  603. struct ican3_msg msg;
  604. memset(&msg, 0, sizeof(msg));
  605. msg.spec = on ? MSG_CONREQ : MSG_COFFREQ;
  606. msg.len = cpu_to_le16(0);
  607. return ican3_send_msg(mod, &msg);
  608. }
  609. static int ican3_set_termination(struct ican3_dev *mod, bool on)
  610. {
  611. struct ican3_msg msg;
  612. memset(&msg, 0, sizeof(msg));
  613. msg.spec = MSG_HWCONF;
  614. msg.len = cpu_to_le16(2);
  615. msg.data[0] = 0x00;
  616. msg.data[1] = on ? HWCONF_TERMINATE_ON : HWCONF_TERMINATE_OFF;
  617. return ican3_send_msg(mod, &msg);
  618. }
  619. static int ican3_send_inquiry(struct ican3_dev *mod, u8 subspec)
  620. {
  621. struct ican3_msg msg;
  622. memset(&msg, 0, sizeof(msg));
  623. msg.spec = MSG_INQUIRY;
  624. msg.len = cpu_to_le16(2);
  625. msg.data[0] = subspec;
  626. msg.data[1] = 0x00;
  627. return ican3_send_msg(mod, &msg);
  628. }
  629. static int ican3_set_buserror(struct ican3_dev *mod, u8 quota)
  630. {
  631. struct ican3_msg msg;
  632. memset(&msg, 0, sizeof(msg));
  633. msg.spec = MSG_CCONFREQ;
  634. msg.len = cpu_to_le16(2);
  635. msg.data[0] = 0x00;
  636. msg.data[1] = quota;
  637. return ican3_send_msg(mod, &msg);
  638. }
  639. /*
  640. * ICAN3 to Linux CAN Frame Conversion
  641. */
  642. static void ican3_to_can_frame(struct ican3_dev *mod,
  643. struct ican3_fast_desc *desc,
  644. struct can_frame *cf)
  645. {
  646. if ((desc->command & ICAN3_CAN_TYPE_MASK) == ICAN3_CAN_TYPE_SFF) {
  647. if (desc->data[1] & ICAN3_SFF_RTR)
  648. cf->can_id |= CAN_RTR_FLAG;
  649. cf->can_id |= desc->data[0] << 3;
  650. cf->can_id |= (desc->data[1] & 0xe0) >> 5;
  651. cf->can_dlc = desc->data[1] & ICAN3_CAN_DLC_MASK;
  652. memcpy(cf->data, &desc->data[2], sizeof(cf->data));
  653. } else {
  654. cf->can_dlc = desc->data[0] & ICAN3_CAN_DLC_MASK;
  655. if (desc->data[0] & ICAN3_EFF_RTR)
  656. cf->can_id |= CAN_RTR_FLAG;
  657. if (desc->data[0] & ICAN3_EFF) {
  658. cf->can_id |= CAN_EFF_FLAG;
  659. cf->can_id |= desc->data[2] << 21; /* 28-21 */
  660. cf->can_id |= desc->data[3] << 13; /* 20-13 */
  661. cf->can_id |= desc->data[4] << 5; /* 12-5 */
  662. cf->can_id |= (desc->data[5] & 0xf8) >> 3;
  663. } else {
  664. cf->can_id |= desc->data[2] << 3; /* 10-3 */
  665. cf->can_id |= desc->data[3] >> 5; /* 2-0 */
  666. }
  667. memcpy(cf->data, &desc->data[6], sizeof(cf->data));
  668. }
  669. }
  670. static void can_frame_to_ican3(struct ican3_dev *mod,
  671. struct can_frame *cf,
  672. struct ican3_fast_desc *desc)
  673. {
  674. /* clear out any stale data in the descriptor */
  675. memset(desc->data, 0, sizeof(desc->data));
  676. /* we always use the extended format, with the ECHO flag set */
  677. desc->command = ICAN3_CAN_TYPE_EFF;
  678. desc->data[0] |= cf->can_dlc;
  679. desc->data[1] |= ICAN3_ECHO;
  680. if (cf->can_id & CAN_RTR_FLAG)
  681. desc->data[0] |= ICAN3_EFF_RTR;
  682. /* pack the id into the correct places */
  683. if (cf->can_id & CAN_EFF_FLAG) {
  684. desc->data[0] |= ICAN3_EFF;
  685. desc->data[2] = (cf->can_id & 0x1fe00000) >> 21; /* 28-21 */
  686. desc->data[3] = (cf->can_id & 0x001fe000) >> 13; /* 20-13 */
  687. desc->data[4] = (cf->can_id & 0x00001fe0) >> 5; /* 12-5 */
  688. desc->data[5] = (cf->can_id & 0x0000001f) << 3; /* 4-0 */
  689. } else {
  690. desc->data[2] = (cf->can_id & 0x7F8) >> 3; /* bits 10-3 */
  691. desc->data[3] = (cf->can_id & 0x007) << 5; /* bits 2-0 */
  692. }
  693. /* copy the data bits into the descriptor */
  694. memcpy(&desc->data[6], cf->data, sizeof(cf->data));
  695. }
  696. /*
  697. * Interrupt Handling
  698. */
  699. /*
  700. * Handle an ID + Version message response from the firmware. We never generate
  701. * this message in production code, but it is very useful when debugging to be
  702. * able to display this message.
  703. */
  704. static void ican3_handle_idvers(struct ican3_dev *mod, struct ican3_msg *msg)
  705. {
  706. dev_dbg(mod->dev, "IDVERS response: %s\n", msg->data);
  707. }
  708. static void ican3_handle_msglost(struct ican3_dev *mod, struct ican3_msg *msg)
  709. {
  710. struct net_device *dev = mod->ndev;
  711. struct net_device_stats *stats = &dev->stats;
  712. struct can_frame *cf;
  713. struct sk_buff *skb;
  714. /*
  715. * Report that communication messages with the microcontroller firmware
  716. * are being lost. These are never CAN frames, so we do not generate an
  717. * error frame for userspace
  718. */
  719. if (msg->spec == MSG_MSGLOST) {
  720. dev_err(mod->dev, "lost %d control messages\n", msg->data[0]);
  721. return;
  722. }
  723. /*
  724. * Oops, this indicates that we have lost messages in the fast queue,
  725. * which are exclusively CAN messages. Our driver isn't reading CAN
  726. * frames fast enough.
  727. *
  728. * We'll pretend that the SJA1000 told us that it ran out of buffer
  729. * space, because there is not a better message for this.
  730. */
  731. skb = alloc_can_err_skb(dev, &cf);
  732. if (skb) {
  733. cf->can_id |= CAN_ERR_CRTL;
  734. cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
  735. stats->rx_errors++;
  736. stats->rx_bytes += cf->can_dlc;
  737. netif_rx(skb);
  738. }
  739. }
  740. /*
  741. * Handle CAN Event Indication Messages from the firmware
  742. *
  743. * The ICAN3 firmware provides the values of some SJA1000 registers when it
  744. * generates this message. The code below is largely copied from the
  745. * drivers/net/can/sja1000/sja1000.c file, and adapted as necessary
  746. */
  747. static int ican3_handle_cevtind(struct ican3_dev *mod, struct ican3_msg *msg)
  748. {
  749. struct net_device *dev = mod->ndev;
  750. struct net_device_stats *stats = &dev->stats;
  751. enum can_state state = mod->can.state;
  752. u8 status, isrc, rxerr, txerr;
  753. struct can_frame *cf;
  754. struct sk_buff *skb;
  755. /* we can only handle the SJA1000 part */
  756. if (msg->data[1] != CEVTIND_CHIP_SJA1000) {
  757. dev_err(mod->dev, "unable to handle errors on non-SJA1000\n");
  758. return -ENODEV;
  759. }
  760. /* check the message length for sanity */
  761. if (le16_to_cpu(msg->len) < 6) {
  762. dev_err(mod->dev, "error message too short\n");
  763. return -EINVAL;
  764. }
  765. skb = alloc_can_err_skb(dev, &cf);
  766. if (skb == NULL)
  767. return -ENOMEM;
  768. isrc = msg->data[0];
  769. status = msg->data[3];
  770. rxerr = msg->data[4];
  771. txerr = msg->data[5];
  772. /* data overrun interrupt */
  773. if (isrc == CEVTIND_DOI || isrc == CEVTIND_LOST) {
  774. dev_dbg(mod->dev, "data overrun interrupt\n");
  775. cf->can_id |= CAN_ERR_CRTL;
  776. cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
  777. stats->rx_over_errors++;
  778. stats->rx_errors++;
  779. }
  780. /* error warning + passive interrupt */
  781. if (isrc == CEVTIND_EI) {
  782. dev_dbg(mod->dev, "error warning + passive interrupt\n");
  783. if (status & SR_BS) {
  784. state = CAN_STATE_BUS_OFF;
  785. cf->can_id |= CAN_ERR_BUSOFF;
  786. can_bus_off(dev);
  787. } else if (status & SR_ES) {
  788. if (rxerr >= 128 || txerr >= 128)
  789. state = CAN_STATE_ERROR_PASSIVE;
  790. else
  791. state = CAN_STATE_ERROR_WARNING;
  792. } else {
  793. state = CAN_STATE_ERROR_ACTIVE;
  794. }
  795. }
  796. /* bus error interrupt */
  797. if (isrc == CEVTIND_BEI) {
  798. u8 ecc = msg->data[2];
  799. dev_dbg(mod->dev, "bus error interrupt\n");
  800. mod->can.can_stats.bus_error++;
  801. stats->rx_errors++;
  802. cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
  803. switch (ecc & ECC_MASK) {
  804. case ECC_BIT:
  805. cf->data[2] |= CAN_ERR_PROT_BIT;
  806. break;
  807. case ECC_FORM:
  808. cf->data[2] |= CAN_ERR_PROT_FORM;
  809. break;
  810. case ECC_STUFF:
  811. cf->data[2] |= CAN_ERR_PROT_STUFF;
  812. break;
  813. default:
  814. cf->data[2] |= CAN_ERR_PROT_UNSPEC;
  815. cf->data[3] = ecc & ECC_SEG;
  816. break;
  817. }
  818. if ((ecc & ECC_DIR) == 0)
  819. cf->data[2] |= CAN_ERR_PROT_TX;
  820. cf->data[6] = txerr;
  821. cf->data[7] = rxerr;
  822. }
  823. if (state != mod->can.state && (state == CAN_STATE_ERROR_WARNING ||
  824. state == CAN_STATE_ERROR_PASSIVE)) {
  825. cf->can_id |= CAN_ERR_CRTL;
  826. if (state == CAN_STATE_ERROR_WARNING) {
  827. mod->can.can_stats.error_warning++;
  828. cf->data[1] = (txerr > rxerr) ?
  829. CAN_ERR_CRTL_TX_WARNING :
  830. CAN_ERR_CRTL_RX_WARNING;
  831. } else {
  832. mod->can.can_stats.error_passive++;
  833. cf->data[1] = (txerr > rxerr) ?
  834. CAN_ERR_CRTL_TX_PASSIVE :
  835. CAN_ERR_CRTL_RX_PASSIVE;
  836. }
  837. cf->data[6] = txerr;
  838. cf->data[7] = rxerr;
  839. }
  840. mod->can.state = state;
  841. stats->rx_errors++;
  842. stats->rx_bytes += cf->can_dlc;
  843. netif_rx(skb);
  844. return 0;
  845. }
  846. static void ican3_handle_inquiry(struct ican3_dev *mod, struct ican3_msg *msg)
  847. {
  848. switch (msg->data[0]) {
  849. case INQUIRY_STATUS:
  850. case INQUIRY_EXTENDED:
  851. mod->bec.rxerr = msg->data[5];
  852. mod->bec.txerr = msg->data[6];
  853. complete(&mod->buserror_comp);
  854. break;
  855. case INQUIRY_TERMINATION:
  856. mod->termination_enabled = msg->data[6] & HWCONF_TERMINATE_ON;
  857. complete(&mod->termination_comp);
  858. break;
  859. default:
  860. dev_err(mod->dev, "received an unknown inquiry response\n");
  861. break;
  862. }
  863. }
  864. static void ican3_handle_unknown_message(struct ican3_dev *mod,
  865. struct ican3_msg *msg)
  866. {
  867. dev_warn(mod->dev, "received unknown message: spec 0x%.2x length %d\n",
  868. msg->spec, le16_to_cpu(msg->len));
  869. }
  870. /*
  871. * Handle a control message from the firmware
  872. */
  873. static void ican3_handle_message(struct ican3_dev *mod, struct ican3_msg *msg)
  874. {
  875. dev_dbg(mod->dev, "%s: modno %d spec 0x%.2x len %d bytes\n", __func__,
  876. mod->num, msg->spec, le16_to_cpu(msg->len));
  877. switch (msg->spec) {
  878. case MSG_IDVERS:
  879. ican3_handle_idvers(mod, msg);
  880. break;
  881. case MSG_MSGLOST:
  882. case MSG_FMSGLOST:
  883. ican3_handle_msglost(mod, msg);
  884. break;
  885. case MSG_CEVTIND:
  886. ican3_handle_cevtind(mod, msg);
  887. break;
  888. case MSG_INQUIRY:
  889. ican3_handle_inquiry(mod, msg);
  890. break;
  891. default:
  892. ican3_handle_unknown_message(mod, msg);
  893. break;
  894. }
  895. }
  896. /*
  897. * Check that there is room in the TX ring to transmit another skb
  898. *
  899. * LOCKING: must hold mod->lock
  900. */
  901. static bool ican3_txok(struct ican3_dev *mod)
  902. {
  903. struct ican3_fast_desc __iomem *desc;
  904. u8 control;
  905. /* copy the control bits of the descriptor */
  906. ican3_set_page(mod, mod->fasttx_start + (mod->fasttx_num / 16));
  907. desc = mod->dpm + ((mod->fasttx_num % 16) * sizeof(*desc));
  908. control = ioread8(&desc->control);
  909. /* if the control bits are not valid, then we have no more space */
  910. if (!(control & DESC_VALID))
  911. return false;
  912. return true;
  913. }
  914. /*
  915. * Receive one CAN frame from the hardware
  916. *
  917. * CONTEXT: must be called from user context
  918. */
  919. static int ican3_recv_skb(struct ican3_dev *mod)
  920. {
  921. struct net_device *ndev = mod->ndev;
  922. struct net_device_stats *stats = &ndev->stats;
  923. struct ican3_fast_desc desc;
  924. void __iomem *desc_addr;
  925. struct can_frame *cf;
  926. struct sk_buff *skb;
  927. unsigned long flags;
  928. spin_lock_irqsave(&mod->lock, flags);
  929. /* copy the whole descriptor */
  930. ican3_set_page(mod, mod->fastrx_start + (mod->fastrx_num / 16));
  931. desc_addr = mod->dpm + ((mod->fastrx_num % 16) * sizeof(desc));
  932. memcpy_fromio(&desc, desc_addr, sizeof(desc));
  933. spin_unlock_irqrestore(&mod->lock, flags);
  934. /* check that we actually have a CAN frame */
  935. if (!(desc.control & DESC_VALID))
  936. return -ENOBUFS;
  937. /* allocate an skb */
  938. skb = alloc_can_skb(ndev, &cf);
  939. if (unlikely(skb == NULL)) {
  940. stats->rx_dropped++;
  941. goto err_noalloc;
  942. }
  943. /* convert the ICAN3 frame into Linux CAN format */
  944. ican3_to_can_frame(mod, &desc, cf);
  945. /* receive the skb, update statistics */
  946. netif_receive_skb(skb);
  947. stats->rx_packets++;
  948. stats->rx_bytes += cf->can_dlc;
  949. err_noalloc:
  950. /* toggle the valid bit and return the descriptor to the ring */
  951. desc.control ^= DESC_VALID;
  952. spin_lock_irqsave(&mod->lock, flags);
  953. ican3_set_page(mod, mod->fastrx_start + (mod->fastrx_num / 16));
  954. memcpy_toio(desc_addr, &desc, 1);
  955. /* update the next buffer pointer */
  956. mod->fastrx_num = (desc.control & DESC_WRAP) ? 0
  957. : (mod->fastrx_num + 1);
  958. /* there are still more buffers to process */
  959. spin_unlock_irqrestore(&mod->lock, flags);
  960. return 0;
  961. }
  962. static int ican3_napi(struct napi_struct *napi, int budget)
  963. {
  964. struct ican3_dev *mod = container_of(napi, struct ican3_dev, napi);
  965. struct ican3_msg msg;
  966. unsigned long flags;
  967. int received = 0;
  968. int ret;
  969. /* process all communication messages */
  970. while (true) {
  971. ret = ican3_recv_msg(mod, &msg);
  972. if (ret)
  973. break;
  974. ican3_handle_message(mod, &msg);
  975. }
  976. /* process all CAN frames from the fast interface */
  977. while (received < budget) {
  978. ret = ican3_recv_skb(mod);
  979. if (ret)
  980. break;
  981. received++;
  982. }
  983. /* We have processed all packets that the adapter had, but it
  984. * was less than our budget, stop polling */
  985. if (received < budget)
  986. napi_complete(napi);
  987. spin_lock_irqsave(&mod->lock, flags);
  988. /* Wake up the transmit queue if necessary */
  989. if (netif_queue_stopped(mod->ndev) && ican3_txok(mod))
  990. netif_wake_queue(mod->ndev);
  991. spin_unlock_irqrestore(&mod->lock, flags);
  992. /* re-enable interrupt generation */
  993. iowrite8(1 << mod->num, &mod->ctrl->int_enable);
  994. return received;
  995. }
  996. static irqreturn_t ican3_irq(int irq, void *dev_id)
  997. {
  998. struct ican3_dev *mod = dev_id;
  999. u8 stat;
  1000. /*
  1001. * The interrupt status register on this device reports interrupts
  1002. * as zeroes instead of using ones like most other devices
  1003. */
  1004. stat = ioread8(&mod->ctrl->int_disable) & (1 << mod->num);
  1005. if (stat == (1 << mod->num))
  1006. return IRQ_NONE;
  1007. /* clear the MODULbus interrupt from the microcontroller */
  1008. ioread8(&mod->dpmctrl->interrupt);
  1009. /* disable interrupt generation, schedule the NAPI poller */
  1010. iowrite8(1 << mod->num, &mod->ctrl->int_disable);
  1011. napi_schedule(&mod->napi);
  1012. return IRQ_HANDLED;
  1013. }
  1014. /*
  1015. * Firmware reset, startup, and shutdown
  1016. */
  1017. /*
  1018. * Reset an ICAN module to its power-on state
  1019. *
  1020. * CONTEXT: no network device registered
  1021. */
  1022. static int ican3_reset_module(struct ican3_dev *mod)
  1023. {
  1024. u8 val = 1 << mod->num;
  1025. unsigned long start;
  1026. u8 runold, runnew;
  1027. /* disable interrupts so no more work is scheduled */
  1028. iowrite8(1 << mod->num, &mod->ctrl->int_disable);
  1029. /* the first unallocated page in the DPM is #9 */
  1030. mod->free_page = DPM_FREE_START;
  1031. ican3_set_page(mod, QUEUE_OLD_CONTROL);
  1032. runold = ioread8(mod->dpm + TARGET_RUNNING);
  1033. /* reset the module */
  1034. iowrite8(val, &mod->ctrl->reset_assert);
  1035. iowrite8(val, &mod->ctrl->reset_deassert);
  1036. /* wait until the module has finished resetting and is running */
  1037. start = jiffies;
  1038. do {
  1039. ican3_set_page(mod, QUEUE_OLD_CONTROL);
  1040. runnew = ioread8(mod->dpm + TARGET_RUNNING);
  1041. if (runnew == (runold ^ 0xff))
  1042. return 0;
  1043. msleep(10);
  1044. } while (time_before(jiffies, start + HZ / 4));
  1045. dev_err(mod->dev, "failed to reset CAN module\n");
  1046. return -ETIMEDOUT;
  1047. }
  1048. static void __devexit ican3_shutdown_module(struct ican3_dev *mod)
  1049. {
  1050. ican3_msg_disconnect(mod);
  1051. ican3_reset_module(mod);
  1052. }
  1053. /*
  1054. * Startup an ICAN module, bringing it into fast mode
  1055. */
  1056. static int __devinit ican3_startup_module(struct ican3_dev *mod)
  1057. {
  1058. int ret;
  1059. ret = ican3_reset_module(mod);
  1060. if (ret) {
  1061. dev_err(mod->dev, "unable to reset module\n");
  1062. return ret;
  1063. }
  1064. /* re-enable interrupts so we can send messages */
  1065. iowrite8(1 << mod->num, &mod->ctrl->int_enable);
  1066. ret = ican3_msg_connect(mod);
  1067. if (ret) {
  1068. dev_err(mod->dev, "unable to connect to module\n");
  1069. return ret;
  1070. }
  1071. ican3_init_new_host_interface(mod);
  1072. ret = ican3_msg_newhostif(mod);
  1073. if (ret) {
  1074. dev_err(mod->dev, "unable to switch to new-style interface\n");
  1075. return ret;
  1076. }
  1077. /* default to "termination on" */
  1078. ret = ican3_set_termination(mod, true);
  1079. if (ret) {
  1080. dev_err(mod->dev, "unable to enable termination\n");
  1081. return ret;
  1082. }
  1083. /* default to "bus errors enabled" */
  1084. ret = ican3_set_buserror(mod, ICAN3_BUSERR_QUOTA_MAX);
  1085. if (ret) {
  1086. dev_err(mod->dev, "unable to set bus-error\n");
  1087. return ret;
  1088. }
  1089. ican3_init_fast_host_interface(mod);
  1090. ret = ican3_msg_fasthostif(mod);
  1091. if (ret) {
  1092. dev_err(mod->dev, "unable to switch to fast host interface\n");
  1093. return ret;
  1094. }
  1095. ret = ican3_set_id_filter(mod, true);
  1096. if (ret) {
  1097. dev_err(mod->dev, "unable to set acceptance filter\n");
  1098. return ret;
  1099. }
  1100. return 0;
  1101. }
  1102. /*
  1103. * CAN Network Device
  1104. */
  1105. static int ican3_open(struct net_device *ndev)
  1106. {
  1107. struct ican3_dev *mod = netdev_priv(ndev);
  1108. u8 quota;
  1109. int ret;
  1110. /* open the CAN layer */
  1111. ret = open_candev(ndev);
  1112. if (ret) {
  1113. dev_err(mod->dev, "unable to start CAN layer\n");
  1114. return ret;
  1115. }
  1116. /* set the bus error generation state appropriately */
  1117. if (mod->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
  1118. quota = ICAN3_BUSERR_QUOTA_MAX;
  1119. else
  1120. quota = 0;
  1121. ret = ican3_set_buserror(mod, quota);
  1122. if (ret) {
  1123. dev_err(mod->dev, "unable to set bus-error\n");
  1124. close_candev(ndev);
  1125. return ret;
  1126. }
  1127. /* bring the bus online */
  1128. ret = ican3_set_bus_state(mod, true);
  1129. if (ret) {
  1130. dev_err(mod->dev, "unable to set bus-on\n");
  1131. close_candev(ndev);
  1132. return ret;
  1133. }
  1134. /* start up the network device */
  1135. mod->can.state = CAN_STATE_ERROR_ACTIVE;
  1136. netif_start_queue(ndev);
  1137. return 0;
  1138. }
  1139. static int ican3_stop(struct net_device *ndev)
  1140. {
  1141. struct ican3_dev *mod = netdev_priv(ndev);
  1142. int ret;
  1143. /* stop the network device xmit routine */
  1144. netif_stop_queue(ndev);
  1145. mod->can.state = CAN_STATE_STOPPED;
  1146. /* bring the bus offline, stop receiving packets */
  1147. ret = ican3_set_bus_state(mod, false);
  1148. if (ret) {
  1149. dev_err(mod->dev, "unable to set bus-off\n");
  1150. return ret;
  1151. }
  1152. /* close the CAN layer */
  1153. close_candev(ndev);
  1154. return 0;
  1155. }
  1156. static int ican3_xmit(struct sk_buff *skb, struct net_device *ndev)
  1157. {
  1158. struct ican3_dev *mod = netdev_priv(ndev);
  1159. struct net_device_stats *stats = &ndev->stats;
  1160. struct can_frame *cf = (struct can_frame *)skb->data;
  1161. struct ican3_fast_desc desc;
  1162. void __iomem *desc_addr;
  1163. unsigned long flags;
  1164. spin_lock_irqsave(&mod->lock, flags);
  1165. /* check that we can actually transmit */
  1166. if (!ican3_txok(mod)) {
  1167. dev_err(mod->dev, "no free descriptors, stopping queue\n");
  1168. netif_stop_queue(ndev);
  1169. spin_unlock_irqrestore(&mod->lock, flags);
  1170. return NETDEV_TX_BUSY;
  1171. }
  1172. /* copy the control bits of the descriptor */
  1173. ican3_set_page(mod, mod->fasttx_start + (mod->fasttx_num / 16));
  1174. desc_addr = mod->dpm + ((mod->fasttx_num % 16) * sizeof(desc));
  1175. memset(&desc, 0, sizeof(desc));
  1176. memcpy_fromio(&desc, desc_addr, 1);
  1177. /* convert the Linux CAN frame into ICAN3 format */
  1178. can_frame_to_ican3(mod, cf, &desc);
  1179. /*
  1180. * the programming manual says that you must set the IVALID bit, then
  1181. * interrupt, then set the valid bit. Quite weird, but it seems to be
  1182. * required for this to work
  1183. */
  1184. desc.control |= DESC_IVALID;
  1185. memcpy_toio(desc_addr, &desc, sizeof(desc));
  1186. /* generate a MODULbus interrupt to the microcontroller */
  1187. iowrite8(0x01, &mod->dpmctrl->interrupt);
  1188. desc.control ^= DESC_VALID;
  1189. memcpy_toio(desc_addr, &desc, sizeof(desc));
  1190. /* update the next buffer pointer */
  1191. mod->fasttx_num = (desc.control & DESC_WRAP) ? 0
  1192. : (mod->fasttx_num + 1);
  1193. /* update statistics */
  1194. stats->tx_packets++;
  1195. stats->tx_bytes += cf->can_dlc;
  1196. kfree_skb(skb);
  1197. /*
  1198. * This hardware doesn't have TX-done notifications, so we'll try and
  1199. * emulate it the best we can using ECHO skbs. Get the next TX
  1200. * descriptor, and see if we have room to send. If not, stop the queue.
  1201. * It will be woken when the ECHO skb for the current packet is recv'd.
  1202. */
  1203. /* copy the control bits of the descriptor */
  1204. if (!ican3_txok(mod))
  1205. netif_stop_queue(ndev);
  1206. spin_unlock_irqrestore(&mod->lock, flags);
  1207. return NETDEV_TX_OK;
  1208. }
  1209. static const struct net_device_ops ican3_netdev_ops = {
  1210. .ndo_open = ican3_open,
  1211. .ndo_stop = ican3_stop,
  1212. .ndo_start_xmit = ican3_xmit,
  1213. };
  1214. /*
  1215. * Low-level CAN Device
  1216. */
  1217. /* This structure was stolen from drivers/net/can/sja1000/sja1000.c */
  1218. static struct can_bittiming_const ican3_bittiming_const = {
  1219. .name = DRV_NAME,
  1220. .tseg1_min = 1,
  1221. .tseg1_max = 16,
  1222. .tseg2_min = 1,
  1223. .tseg2_max = 8,
  1224. .sjw_max = 4,
  1225. .brp_min = 1,
  1226. .brp_max = 64,
  1227. .brp_inc = 1,
  1228. };
  1229. /*
  1230. * This routine was stolen from drivers/net/can/sja1000/sja1000.c
  1231. *
  1232. * The bittiming register command for the ICAN3 just sets the bit timing
  1233. * registers on the SJA1000 chip directly
  1234. */
  1235. static int ican3_set_bittiming(struct net_device *ndev)
  1236. {
  1237. struct ican3_dev *mod = netdev_priv(ndev);
  1238. struct can_bittiming *bt = &mod->can.bittiming;
  1239. struct ican3_msg msg;
  1240. u8 btr0, btr1;
  1241. btr0 = ((bt->brp - 1) & 0x3f) | (((bt->sjw - 1) & 0x3) << 6);
  1242. btr1 = ((bt->prop_seg + bt->phase_seg1 - 1) & 0xf) |
  1243. (((bt->phase_seg2 - 1) & 0x7) << 4);
  1244. if (mod->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
  1245. btr1 |= 0x80;
  1246. memset(&msg, 0, sizeof(msg));
  1247. msg.spec = MSG_CBTRREQ;
  1248. msg.len = cpu_to_le16(4);
  1249. msg.data[0] = 0x00;
  1250. msg.data[1] = 0x00;
  1251. msg.data[2] = btr0;
  1252. msg.data[3] = btr1;
  1253. return ican3_send_msg(mod, &msg);
  1254. }
  1255. static int ican3_set_mode(struct net_device *ndev, enum can_mode mode)
  1256. {
  1257. struct ican3_dev *mod = netdev_priv(ndev);
  1258. int ret;
  1259. if (mode != CAN_MODE_START)
  1260. return -ENOTSUPP;
  1261. /* bring the bus online */
  1262. ret = ican3_set_bus_state(mod, true);
  1263. if (ret) {
  1264. dev_err(mod->dev, "unable to set bus-on\n");
  1265. return ret;
  1266. }
  1267. /* start up the network device */
  1268. mod->can.state = CAN_STATE_ERROR_ACTIVE;
  1269. if (netif_queue_stopped(ndev))
  1270. netif_wake_queue(ndev);
  1271. return 0;
  1272. }
  1273. static int ican3_get_berr_counter(const struct net_device *ndev,
  1274. struct can_berr_counter *bec)
  1275. {
  1276. struct ican3_dev *mod = netdev_priv(ndev);
  1277. int ret;
  1278. ret = ican3_send_inquiry(mod, INQUIRY_STATUS);
  1279. if (ret)
  1280. return ret;
  1281. ret = wait_for_completion_timeout(&mod->buserror_comp, HZ);
  1282. if (ret <= 0) {
  1283. dev_info(mod->dev, "%s timed out\n", __func__);
  1284. return -ETIMEDOUT;
  1285. }
  1286. bec->rxerr = mod->bec.rxerr;
  1287. bec->txerr = mod->bec.txerr;
  1288. return 0;
  1289. }
  1290. /*
  1291. * Sysfs Attributes
  1292. */
  1293. static ssize_t ican3_sysfs_show_term(struct device *dev,
  1294. struct device_attribute *attr,
  1295. char *buf)
  1296. {
  1297. struct ican3_dev *mod = netdev_priv(to_net_dev(dev));
  1298. int ret;
  1299. ret = ican3_send_inquiry(mod, INQUIRY_TERMINATION);
  1300. if (ret)
  1301. return ret;
  1302. ret = wait_for_completion_timeout(&mod->termination_comp, HZ);
  1303. if (ret <= 0) {
  1304. dev_info(mod->dev, "%s timed out\n", __func__);
  1305. return -ETIMEDOUT;
  1306. }
  1307. return snprintf(buf, PAGE_SIZE, "%u\n", mod->termination_enabled);
  1308. }
  1309. static ssize_t ican3_sysfs_set_term(struct device *dev,
  1310. struct device_attribute *attr,
  1311. const char *buf, size_t count)
  1312. {
  1313. struct ican3_dev *mod = netdev_priv(to_net_dev(dev));
  1314. unsigned long enable;
  1315. int ret;
  1316. if (strict_strtoul(buf, 0, &enable))
  1317. return -EINVAL;
  1318. ret = ican3_set_termination(mod, enable);
  1319. if (ret)
  1320. return ret;
  1321. return count;
  1322. }
  1323. static DEVICE_ATTR(termination, S_IWUSR | S_IRUGO, ican3_sysfs_show_term,
  1324. ican3_sysfs_set_term);
  1325. static struct attribute *ican3_sysfs_attrs[] = {
  1326. &dev_attr_termination.attr,
  1327. NULL,
  1328. };
  1329. static struct attribute_group ican3_sysfs_attr_group = {
  1330. .attrs = ican3_sysfs_attrs,
  1331. };
  1332. /*
  1333. * PCI Subsystem
  1334. */
  1335. static int __devinit ican3_probe(struct platform_device *pdev)
  1336. {
  1337. struct janz_platform_data *pdata;
  1338. struct net_device *ndev;
  1339. struct ican3_dev *mod;
  1340. struct resource *res;
  1341. struct device *dev;
  1342. int ret;
  1343. pdata = pdev->dev.platform_data;
  1344. if (!pdata)
  1345. return -ENXIO;
  1346. dev_dbg(&pdev->dev, "probe: module number %d\n", pdata->modno);
  1347. /* save the struct device for printing */
  1348. dev = &pdev->dev;
  1349. /* allocate the CAN device and private data */
  1350. ndev = alloc_candev(sizeof(*mod), 0);
  1351. if (!ndev) {
  1352. dev_err(dev, "unable to allocate CANdev\n");
  1353. ret = -ENOMEM;
  1354. goto out_return;
  1355. }
  1356. platform_set_drvdata(pdev, ndev);
  1357. mod = netdev_priv(ndev);
  1358. mod->ndev = ndev;
  1359. mod->dev = &pdev->dev;
  1360. mod->num = pdata->modno;
  1361. netif_napi_add(ndev, &mod->napi, ican3_napi, ICAN3_RX_BUFFERS);
  1362. spin_lock_init(&mod->lock);
  1363. init_completion(&mod->termination_comp);
  1364. init_completion(&mod->buserror_comp);
  1365. /* setup device-specific sysfs attributes */
  1366. ndev->sysfs_groups[0] = &ican3_sysfs_attr_group;
  1367. /* the first unallocated page in the DPM is 9 */
  1368. mod->free_page = DPM_FREE_START;
  1369. ndev->netdev_ops = &ican3_netdev_ops;
  1370. ndev->flags |= IFF_ECHO;
  1371. SET_NETDEV_DEV(ndev, &pdev->dev);
  1372. mod->can.clock.freq = ICAN3_CAN_CLOCK;
  1373. mod->can.bittiming_const = &ican3_bittiming_const;
  1374. mod->can.do_set_bittiming = ican3_set_bittiming;
  1375. mod->can.do_set_mode = ican3_set_mode;
  1376. mod->can.do_get_berr_counter = ican3_get_berr_counter;
  1377. mod->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES
  1378. | CAN_CTRLMODE_BERR_REPORTING;
  1379. /* find our IRQ number */
  1380. mod->irq = platform_get_irq(pdev, 0);
  1381. if (mod->irq < 0) {
  1382. dev_err(dev, "IRQ line not found\n");
  1383. ret = -ENODEV;
  1384. goto out_free_ndev;
  1385. }
  1386. ndev->irq = mod->irq;
  1387. /* get access to the MODULbus registers for this module */
  1388. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1389. if (!res) {
  1390. dev_err(dev, "MODULbus registers not found\n");
  1391. ret = -ENODEV;
  1392. goto out_free_ndev;
  1393. }
  1394. mod->dpm = ioremap(res->start, resource_size(res));
  1395. if (!mod->dpm) {
  1396. dev_err(dev, "MODULbus registers not ioremap\n");
  1397. ret = -ENOMEM;
  1398. goto out_free_ndev;
  1399. }
  1400. mod->dpmctrl = mod->dpm + DPM_PAGE_SIZE;
  1401. /* get access to the control registers for this module */
  1402. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1403. if (!res) {
  1404. dev_err(dev, "CONTROL registers not found\n");
  1405. ret = -ENODEV;
  1406. goto out_iounmap_dpm;
  1407. }
  1408. mod->ctrl = ioremap(res->start, resource_size(res));
  1409. if (!mod->ctrl) {
  1410. dev_err(dev, "CONTROL registers not ioremap\n");
  1411. ret = -ENOMEM;
  1412. goto out_iounmap_dpm;
  1413. }
  1414. /* disable our IRQ, then hookup the IRQ handler */
  1415. iowrite8(1 << mod->num, &mod->ctrl->int_disable);
  1416. ret = request_irq(mod->irq, ican3_irq, IRQF_SHARED, DRV_NAME, mod);
  1417. if (ret) {
  1418. dev_err(dev, "unable to request IRQ\n");
  1419. goto out_iounmap_ctrl;
  1420. }
  1421. /* reset and initialize the CAN controller into fast mode */
  1422. napi_enable(&mod->napi);
  1423. ret = ican3_startup_module(mod);
  1424. if (ret) {
  1425. dev_err(dev, "%s: unable to start CANdev\n", __func__);
  1426. goto out_free_irq;
  1427. }
  1428. /* register with the Linux CAN layer */
  1429. ret = register_candev(ndev);
  1430. if (ret) {
  1431. dev_err(dev, "%s: unable to register CANdev\n", __func__);
  1432. goto out_free_irq;
  1433. }
  1434. dev_info(dev, "module %d: registered CAN device\n", pdata->modno);
  1435. return 0;
  1436. out_free_irq:
  1437. napi_disable(&mod->napi);
  1438. iowrite8(1 << mod->num, &mod->ctrl->int_disable);
  1439. free_irq(mod->irq, mod);
  1440. out_iounmap_ctrl:
  1441. iounmap(mod->ctrl);
  1442. out_iounmap_dpm:
  1443. iounmap(mod->dpm);
  1444. out_free_ndev:
  1445. free_candev(ndev);
  1446. out_return:
  1447. return ret;
  1448. }
  1449. static int __devexit ican3_remove(struct platform_device *pdev)
  1450. {
  1451. struct net_device *ndev = platform_get_drvdata(pdev);
  1452. struct ican3_dev *mod = netdev_priv(ndev);
  1453. /* unregister the netdevice, stop interrupts */
  1454. unregister_netdev(ndev);
  1455. napi_disable(&mod->napi);
  1456. iowrite8(1 << mod->num, &mod->ctrl->int_disable);
  1457. free_irq(mod->irq, mod);
  1458. /* put the module into reset */
  1459. ican3_shutdown_module(mod);
  1460. /* unmap all registers */
  1461. iounmap(mod->ctrl);
  1462. iounmap(mod->dpm);
  1463. free_candev(ndev);
  1464. return 0;
  1465. }
  1466. static struct platform_driver ican3_driver = {
  1467. .driver = {
  1468. .name = DRV_NAME,
  1469. .owner = THIS_MODULE,
  1470. },
  1471. .probe = ican3_probe,
  1472. .remove = __devexit_p(ican3_remove),
  1473. };
  1474. static int __init ican3_init(void)
  1475. {
  1476. return platform_driver_register(&ican3_driver);
  1477. }
  1478. static void __exit ican3_exit(void)
  1479. {
  1480. platform_driver_unregister(&ican3_driver);
  1481. }
  1482. MODULE_AUTHOR("Ira W. Snyder <iws@ovro.caltech.edu>");
  1483. MODULE_DESCRIPTION("Janz MODULbus VMOD-ICAN3 Driver");
  1484. MODULE_LICENSE("GPL");
  1485. MODULE_ALIAS("platform:janz-ican3");
  1486. module_init(ican3_init);
  1487. module_exit(ican3_exit);