am79c961a.c 18 KB

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  1. /*
  2. * linux/drivers/net/am79c961.c
  3. *
  4. * by Russell King <rmk@arm.linux.org.uk> 1995-2001.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Derived from various things including skeleton.c
  11. *
  12. * This is a special driver for the am79c961A Lance chip used in the
  13. * Intel (formally Digital Equipment Corp) EBSA110 platform. Please
  14. * note that this can not be built as a module (it doesn't make sense).
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/types.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/ioport.h>
  20. #include <linux/slab.h>
  21. #include <linux/string.h>
  22. #include <linux/errno.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/delay.h>
  26. #include <linux/init.h>
  27. #include <linux/crc32.h>
  28. #include <linux/bitops.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/io.h>
  31. #include <mach/hardware.h>
  32. #include <asm/system.h>
  33. #define TX_BUFFERS 15
  34. #define RX_BUFFERS 25
  35. #include "am79c961a.h"
  36. static irqreturn_t
  37. am79c961_interrupt (int irq, void *dev_id);
  38. static unsigned int net_debug = NET_DEBUG;
  39. static const char version[] =
  40. "am79c961 ethernet driver (C) 1995-2001 Russell King v0.04\n";
  41. /* --------------------------------------------------------------------------- */
  42. #ifdef __arm__
  43. static void write_rreg(u_long base, u_int reg, u_int val)
  44. {
  45. asm volatile(
  46. "str%?h %1, [%2] @ NET_RAP\n\t"
  47. "str%?h %0, [%2, #-4] @ NET_RDP"
  48. :
  49. : "r" (val), "r" (reg), "r" (ISAIO_BASE + 0x0464));
  50. }
  51. static inline unsigned short read_rreg(u_long base_addr, u_int reg)
  52. {
  53. unsigned short v;
  54. asm volatile(
  55. "str%?h %1, [%2] @ NET_RAP\n\t"
  56. "ldr%?h %0, [%2, #-4] @ NET_RDP"
  57. : "=r" (v)
  58. : "r" (reg), "r" (ISAIO_BASE + 0x0464));
  59. return v;
  60. }
  61. static inline void write_ireg(u_long base, u_int reg, u_int val)
  62. {
  63. asm volatile(
  64. "str%?h %1, [%2] @ NET_RAP\n\t"
  65. "str%?h %0, [%2, #8] @ NET_IDP"
  66. :
  67. : "r" (val), "r" (reg), "r" (ISAIO_BASE + 0x0464));
  68. }
  69. static inline unsigned short read_ireg(u_long base_addr, u_int reg)
  70. {
  71. u_short v;
  72. asm volatile(
  73. "str%?h %1, [%2] @ NAT_RAP\n\t"
  74. "ldr%?h %0, [%2, #8] @ NET_IDP\n\t"
  75. : "=r" (v)
  76. : "r" (reg), "r" (ISAIO_BASE + 0x0464));
  77. return v;
  78. }
  79. #define am_writeword(dev,off,val) __raw_writew(val, ISAMEM_BASE + ((off) << 1))
  80. #define am_readword(dev,off) __raw_readw(ISAMEM_BASE + ((off) << 1))
  81. static void
  82. am_writebuffer(struct net_device *dev, u_int offset, unsigned char *buf, unsigned int length)
  83. {
  84. offset = ISAMEM_BASE + (offset << 1);
  85. length = (length + 1) & ~1;
  86. if ((int)buf & 2) {
  87. asm volatile("str%?h %2, [%0], #4"
  88. : "=&r" (offset) : "0" (offset), "r" (buf[0] | (buf[1] << 8)));
  89. buf += 2;
  90. length -= 2;
  91. }
  92. while (length > 8) {
  93. register unsigned int tmp asm("r2"), tmp2 asm("r3");
  94. asm volatile(
  95. "ldm%?ia %0!, {%1, %2}"
  96. : "+r" (buf), "=&r" (tmp), "=&r" (tmp2));
  97. length -= 8;
  98. asm volatile(
  99. "str%?h %1, [%0], #4\n\t"
  100. "mov%? %1, %1, lsr #16\n\t"
  101. "str%?h %1, [%0], #4\n\t"
  102. "str%?h %2, [%0], #4\n\t"
  103. "mov%? %2, %2, lsr #16\n\t"
  104. "str%?h %2, [%0], #4"
  105. : "+r" (offset), "=&r" (tmp), "=&r" (tmp2));
  106. }
  107. while (length > 0) {
  108. asm volatile("str%?h %2, [%0], #4"
  109. : "=&r" (offset) : "0" (offset), "r" (buf[0] | (buf[1] << 8)));
  110. buf += 2;
  111. length -= 2;
  112. }
  113. }
  114. static void
  115. am_readbuffer(struct net_device *dev, u_int offset, unsigned char *buf, unsigned int length)
  116. {
  117. offset = ISAMEM_BASE + (offset << 1);
  118. length = (length + 1) & ~1;
  119. if ((int)buf & 2) {
  120. unsigned int tmp;
  121. asm volatile(
  122. "ldr%?h %2, [%0], #4\n\t"
  123. "str%?b %2, [%1], #1\n\t"
  124. "mov%? %2, %2, lsr #8\n\t"
  125. "str%?b %2, [%1], #1"
  126. : "=&r" (offset), "=&r" (buf), "=r" (tmp): "0" (offset), "1" (buf));
  127. length -= 2;
  128. }
  129. while (length > 8) {
  130. register unsigned int tmp asm("r2"), tmp2 asm("r3"), tmp3;
  131. asm volatile(
  132. "ldr%?h %2, [%0], #4\n\t"
  133. "ldr%?h %4, [%0], #4\n\t"
  134. "ldr%?h %3, [%0], #4\n\t"
  135. "orr%? %2, %2, %4, lsl #16\n\t"
  136. "ldr%?h %4, [%0], #4\n\t"
  137. "orr%? %3, %3, %4, lsl #16\n\t"
  138. "stm%?ia %1!, {%2, %3}"
  139. : "=&r" (offset), "=&r" (buf), "=r" (tmp), "=r" (tmp2), "=r" (tmp3)
  140. : "0" (offset), "1" (buf));
  141. length -= 8;
  142. }
  143. while (length > 0) {
  144. unsigned int tmp;
  145. asm volatile(
  146. "ldr%?h %2, [%0], #4\n\t"
  147. "str%?b %2, [%1], #1\n\t"
  148. "mov%? %2, %2, lsr #8\n\t"
  149. "str%?b %2, [%1], #1"
  150. : "=&r" (offset), "=&r" (buf), "=r" (tmp) : "0" (offset), "1" (buf));
  151. length -= 2;
  152. }
  153. }
  154. #else
  155. #error Not compatible
  156. #endif
  157. static int
  158. am79c961_ramtest(struct net_device *dev, unsigned int val)
  159. {
  160. unsigned char *buffer = kmalloc (65536, GFP_KERNEL);
  161. int i, error = 0, errorcount = 0;
  162. if (!buffer)
  163. return 0;
  164. memset (buffer, val, 65536);
  165. am_writebuffer(dev, 0, buffer, 65536);
  166. memset (buffer, val ^ 255, 65536);
  167. am_readbuffer(dev, 0, buffer, 65536);
  168. for (i = 0; i < 65536; i++) {
  169. if (buffer[i] != val && !error) {
  170. printk ("%s: buffer error (%02X %02X) %05X - ", dev->name, val, buffer[i], i);
  171. error = 1;
  172. errorcount ++;
  173. } else if (error && buffer[i] == val) {
  174. printk ("%05X\n", i);
  175. error = 0;
  176. }
  177. }
  178. if (error)
  179. printk ("10000\n");
  180. kfree (buffer);
  181. return errorcount;
  182. }
  183. static void am79c961_mc_hash(char *addr, u16 *hash)
  184. {
  185. if (addr[0] & 0x01) {
  186. int idx, bit;
  187. u32 crc;
  188. crc = ether_crc_le(ETH_ALEN, addr);
  189. idx = crc >> 30;
  190. bit = (crc >> 26) & 15;
  191. hash[idx] |= 1 << bit;
  192. }
  193. }
  194. static unsigned int am79c961_get_rx_mode(struct net_device *dev, u16 *hash)
  195. {
  196. unsigned int mode = MODE_PORT_10BT;
  197. if (dev->flags & IFF_PROMISC) {
  198. mode |= MODE_PROMISC;
  199. memset(hash, 0xff, 4 * sizeof(*hash));
  200. } else if (dev->flags & IFF_ALLMULTI) {
  201. memset(hash, 0xff, 4 * sizeof(*hash));
  202. } else {
  203. struct netdev_hw_addr *ha;
  204. memset(hash, 0, 4 * sizeof(*hash));
  205. netdev_for_each_mc_addr(ha, dev)
  206. am79c961_mc_hash(ha->addr, hash);
  207. }
  208. return mode;
  209. }
  210. static void
  211. am79c961_init_for_open(struct net_device *dev)
  212. {
  213. struct dev_priv *priv = netdev_priv(dev);
  214. unsigned long flags;
  215. unsigned char *p;
  216. u_int hdr_addr, first_free_addr;
  217. u16 multi_hash[4], mode = am79c961_get_rx_mode(dev, multi_hash);
  218. int i;
  219. /*
  220. * Stop the chip.
  221. */
  222. spin_lock_irqsave(&priv->chip_lock, flags);
  223. write_rreg (dev->base_addr, CSR0, CSR0_BABL|CSR0_CERR|CSR0_MISS|CSR0_MERR|CSR0_TINT|CSR0_RINT|CSR0_STOP);
  224. spin_unlock_irqrestore(&priv->chip_lock, flags);
  225. write_ireg (dev->base_addr, 5, 0x00a0); /* Receive address LED */
  226. write_ireg (dev->base_addr, 6, 0x0081); /* Collision LED */
  227. write_ireg (dev->base_addr, 7, 0x0090); /* XMIT LED */
  228. write_ireg (dev->base_addr, 2, 0x0000); /* MODE register selects media */
  229. for (i = LADRL; i <= LADRH; i++)
  230. write_rreg (dev->base_addr, i, multi_hash[i - LADRL]);
  231. for (i = PADRL, p = dev->dev_addr; i <= PADRH; i++, p += 2)
  232. write_rreg (dev->base_addr, i, p[0] | (p[1] << 8));
  233. write_rreg (dev->base_addr, MODE, mode);
  234. write_rreg (dev->base_addr, POLLINT, 0);
  235. write_rreg (dev->base_addr, SIZERXR, -RX_BUFFERS);
  236. write_rreg (dev->base_addr, SIZETXR, -TX_BUFFERS);
  237. first_free_addr = RX_BUFFERS * 8 + TX_BUFFERS * 8 + 16;
  238. hdr_addr = 0;
  239. priv->rxhead = 0;
  240. priv->rxtail = 0;
  241. priv->rxhdr = hdr_addr;
  242. for (i = 0; i < RX_BUFFERS; i++) {
  243. priv->rxbuffer[i] = first_free_addr;
  244. am_writeword (dev, hdr_addr, first_free_addr);
  245. am_writeword (dev, hdr_addr + 2, RMD_OWN);
  246. am_writeword (dev, hdr_addr + 4, (-1600));
  247. am_writeword (dev, hdr_addr + 6, 0);
  248. first_free_addr += 1600;
  249. hdr_addr += 8;
  250. }
  251. priv->txhead = 0;
  252. priv->txtail = 0;
  253. priv->txhdr = hdr_addr;
  254. for (i = 0; i < TX_BUFFERS; i++) {
  255. priv->txbuffer[i] = first_free_addr;
  256. am_writeword (dev, hdr_addr, first_free_addr);
  257. am_writeword (dev, hdr_addr + 2, TMD_STP|TMD_ENP);
  258. am_writeword (dev, hdr_addr + 4, 0xf000);
  259. am_writeword (dev, hdr_addr + 6, 0);
  260. first_free_addr += 1600;
  261. hdr_addr += 8;
  262. }
  263. write_rreg (dev->base_addr, BASERXL, priv->rxhdr);
  264. write_rreg (dev->base_addr, BASERXH, 0);
  265. write_rreg (dev->base_addr, BASETXL, priv->txhdr);
  266. write_rreg (dev->base_addr, BASERXH, 0);
  267. write_rreg (dev->base_addr, CSR0, CSR0_STOP);
  268. write_rreg (dev->base_addr, CSR3, CSR3_IDONM|CSR3_BABLM|CSR3_DXSUFLO);
  269. write_rreg (dev->base_addr, CSR4, CSR4_APAD_XMIT|CSR4_MFCOM|CSR4_RCVCCOM|CSR4_TXSTRTM|CSR4_JABM);
  270. write_rreg (dev->base_addr, CSR0, CSR0_IENA|CSR0_STRT);
  271. }
  272. static void am79c961_timer(unsigned long data)
  273. {
  274. struct net_device *dev = (struct net_device *)data;
  275. struct dev_priv *priv = netdev_priv(dev);
  276. unsigned int lnkstat, carrier;
  277. lnkstat = read_ireg(dev->base_addr, ISALED0) & ISALED0_LNKST;
  278. carrier = netif_carrier_ok(dev);
  279. if (lnkstat && !carrier) {
  280. netif_carrier_on(dev);
  281. printk("%s: link up\n", dev->name);
  282. } else if (!lnkstat && carrier) {
  283. netif_carrier_off(dev);
  284. printk("%s: link down\n", dev->name);
  285. }
  286. mod_timer(&priv->timer, jiffies + msecs_to_jiffies(500));
  287. }
  288. /*
  289. * Open/initialize the board.
  290. */
  291. static int
  292. am79c961_open(struct net_device *dev)
  293. {
  294. struct dev_priv *priv = netdev_priv(dev);
  295. int ret;
  296. ret = request_irq(dev->irq, am79c961_interrupt, 0, dev->name, dev);
  297. if (ret)
  298. return ret;
  299. am79c961_init_for_open(dev);
  300. netif_carrier_off(dev);
  301. priv->timer.expires = jiffies;
  302. add_timer(&priv->timer);
  303. netif_start_queue(dev);
  304. return 0;
  305. }
  306. /*
  307. * The inverse routine to am79c961_open().
  308. */
  309. static int
  310. am79c961_close(struct net_device *dev)
  311. {
  312. struct dev_priv *priv = netdev_priv(dev);
  313. unsigned long flags;
  314. del_timer_sync(&priv->timer);
  315. netif_stop_queue(dev);
  316. netif_carrier_off(dev);
  317. spin_lock_irqsave(&priv->chip_lock, flags);
  318. write_rreg (dev->base_addr, CSR0, CSR0_STOP);
  319. write_rreg (dev->base_addr, CSR3, CSR3_MASKALL);
  320. spin_unlock_irqrestore(&priv->chip_lock, flags);
  321. free_irq (dev->irq, dev);
  322. return 0;
  323. }
  324. /*
  325. * Set or clear promiscuous/multicast mode filter for this adapter.
  326. */
  327. static void am79c961_setmulticastlist (struct net_device *dev)
  328. {
  329. struct dev_priv *priv = netdev_priv(dev);
  330. unsigned long flags;
  331. u16 multi_hash[4], mode = am79c961_get_rx_mode(dev, multi_hash);
  332. int i, stopped;
  333. spin_lock_irqsave(&priv->chip_lock, flags);
  334. stopped = read_rreg(dev->base_addr, CSR0) & CSR0_STOP;
  335. if (!stopped) {
  336. /*
  337. * Put the chip into suspend mode
  338. */
  339. write_rreg(dev->base_addr, CTRL1, CTRL1_SPND);
  340. /*
  341. * Spin waiting for chip to report suspend mode
  342. */
  343. while ((read_rreg(dev->base_addr, CTRL1) & CTRL1_SPND) == 0) {
  344. spin_unlock_irqrestore(&priv->chip_lock, flags);
  345. nop();
  346. spin_lock_irqsave(&priv->chip_lock, flags);
  347. }
  348. }
  349. /*
  350. * Update the multicast hash table
  351. */
  352. for (i = 0; i < ARRAY_SIZE(multi_hash); i++)
  353. write_rreg(dev->base_addr, i + LADRL, multi_hash[i]);
  354. /*
  355. * Write the mode register
  356. */
  357. write_rreg(dev->base_addr, MODE, mode);
  358. if (!stopped) {
  359. /*
  360. * Put the chip back into running mode
  361. */
  362. write_rreg(dev->base_addr, CTRL1, 0);
  363. }
  364. spin_unlock_irqrestore(&priv->chip_lock, flags);
  365. }
  366. static void am79c961_timeout(struct net_device *dev)
  367. {
  368. printk(KERN_WARNING "%s: transmit timed out, network cable problem?\n",
  369. dev->name);
  370. /*
  371. * ought to do some setup of the tx side here
  372. */
  373. netif_wake_queue(dev);
  374. }
  375. /*
  376. * Transmit a packet
  377. */
  378. static int
  379. am79c961_sendpacket(struct sk_buff *skb, struct net_device *dev)
  380. {
  381. struct dev_priv *priv = netdev_priv(dev);
  382. unsigned int hdraddr, bufaddr;
  383. unsigned int head;
  384. unsigned long flags;
  385. head = priv->txhead;
  386. hdraddr = priv->txhdr + (head << 3);
  387. bufaddr = priv->txbuffer[head];
  388. head += 1;
  389. if (head >= TX_BUFFERS)
  390. head = 0;
  391. am_writebuffer (dev, bufaddr, skb->data, skb->len);
  392. am_writeword (dev, hdraddr + 4, -skb->len);
  393. am_writeword (dev, hdraddr + 2, TMD_OWN|TMD_STP|TMD_ENP);
  394. priv->txhead = head;
  395. spin_lock_irqsave(&priv->chip_lock, flags);
  396. write_rreg (dev->base_addr, CSR0, CSR0_TDMD|CSR0_IENA);
  397. spin_unlock_irqrestore(&priv->chip_lock, flags);
  398. /*
  399. * If the next packet is owned by the ethernet device,
  400. * then the tx ring is full and we can't add another
  401. * packet.
  402. */
  403. if (am_readword(dev, priv->txhdr + (priv->txhead << 3) + 2) & TMD_OWN)
  404. netif_stop_queue(dev);
  405. dev_kfree_skb(skb);
  406. return NETDEV_TX_OK;
  407. }
  408. /*
  409. * If we have a good packet(s), get it/them out of the buffers.
  410. */
  411. static void
  412. am79c961_rx(struct net_device *dev, struct dev_priv *priv)
  413. {
  414. do {
  415. struct sk_buff *skb;
  416. u_int hdraddr;
  417. u_int pktaddr;
  418. u_int status;
  419. int len;
  420. hdraddr = priv->rxhdr + (priv->rxtail << 3);
  421. pktaddr = priv->rxbuffer[priv->rxtail];
  422. status = am_readword (dev, hdraddr + 2);
  423. if (status & RMD_OWN) /* do we own it? */
  424. break;
  425. priv->rxtail ++;
  426. if (priv->rxtail >= RX_BUFFERS)
  427. priv->rxtail = 0;
  428. if ((status & (RMD_ERR|RMD_STP|RMD_ENP)) != (RMD_STP|RMD_ENP)) {
  429. am_writeword (dev, hdraddr + 2, RMD_OWN);
  430. dev->stats.rx_errors++;
  431. if (status & RMD_ERR) {
  432. if (status & RMD_FRAM)
  433. dev->stats.rx_frame_errors++;
  434. if (status & RMD_CRC)
  435. dev->stats.rx_crc_errors++;
  436. } else if (status & RMD_STP)
  437. dev->stats.rx_length_errors++;
  438. continue;
  439. }
  440. len = am_readword(dev, hdraddr + 6);
  441. skb = dev_alloc_skb(len + 2);
  442. if (skb) {
  443. skb_reserve(skb, 2);
  444. am_readbuffer(dev, pktaddr, skb_put(skb, len), len);
  445. am_writeword(dev, hdraddr + 2, RMD_OWN);
  446. skb->protocol = eth_type_trans(skb, dev);
  447. netif_rx(skb);
  448. dev->stats.rx_bytes += len;
  449. dev->stats.rx_packets++;
  450. } else {
  451. am_writeword (dev, hdraddr + 2, RMD_OWN);
  452. printk (KERN_WARNING "%s: memory squeeze, dropping packet.\n", dev->name);
  453. dev->stats.rx_dropped++;
  454. break;
  455. }
  456. } while (1);
  457. }
  458. /*
  459. * Update stats for the transmitted packet
  460. */
  461. static void
  462. am79c961_tx(struct net_device *dev, struct dev_priv *priv)
  463. {
  464. do {
  465. short len;
  466. u_int hdraddr;
  467. u_int status;
  468. hdraddr = priv->txhdr + (priv->txtail << 3);
  469. status = am_readword (dev, hdraddr + 2);
  470. if (status & TMD_OWN)
  471. break;
  472. priv->txtail ++;
  473. if (priv->txtail >= TX_BUFFERS)
  474. priv->txtail = 0;
  475. if (status & TMD_ERR) {
  476. u_int status2;
  477. dev->stats.tx_errors++;
  478. status2 = am_readword (dev, hdraddr + 6);
  479. /*
  480. * Clear the error byte
  481. */
  482. am_writeword (dev, hdraddr + 6, 0);
  483. if (status2 & TST_RTRY)
  484. dev->stats.collisions += 16;
  485. if (status2 & TST_LCOL)
  486. dev->stats.tx_window_errors++;
  487. if (status2 & TST_LCAR)
  488. dev->stats.tx_carrier_errors++;
  489. if (status2 & TST_UFLO)
  490. dev->stats.tx_fifo_errors++;
  491. continue;
  492. }
  493. dev->stats.tx_packets++;
  494. len = am_readword (dev, hdraddr + 4);
  495. dev->stats.tx_bytes += -len;
  496. } while (priv->txtail != priv->txhead);
  497. netif_wake_queue(dev);
  498. }
  499. static irqreturn_t
  500. am79c961_interrupt(int irq, void *dev_id)
  501. {
  502. struct net_device *dev = (struct net_device *)dev_id;
  503. struct dev_priv *priv = netdev_priv(dev);
  504. u_int status, n = 100;
  505. int handled = 0;
  506. do {
  507. status = read_rreg(dev->base_addr, CSR0);
  508. write_rreg(dev->base_addr, CSR0, status &
  509. (CSR0_IENA|CSR0_TINT|CSR0_RINT|
  510. CSR0_MERR|CSR0_MISS|CSR0_CERR|CSR0_BABL));
  511. if (status & CSR0_RINT) {
  512. handled = 1;
  513. am79c961_rx(dev, priv);
  514. }
  515. if (status & CSR0_TINT) {
  516. handled = 1;
  517. am79c961_tx(dev, priv);
  518. }
  519. if (status & CSR0_MISS) {
  520. handled = 1;
  521. dev->stats.rx_dropped++;
  522. }
  523. if (status & CSR0_CERR) {
  524. handled = 1;
  525. mod_timer(&priv->timer, jiffies);
  526. }
  527. } while (--n && status & (CSR0_RINT | CSR0_TINT));
  528. return IRQ_RETVAL(handled);
  529. }
  530. #ifdef CONFIG_NET_POLL_CONTROLLER
  531. static void am79c961_poll_controller(struct net_device *dev)
  532. {
  533. unsigned long flags;
  534. local_irq_save(flags);
  535. am79c961_interrupt(dev->irq, dev);
  536. local_irq_restore(flags);
  537. }
  538. #endif
  539. /*
  540. * Initialise the chip. Note that we always expect
  541. * to be entered with interrupts enabled.
  542. */
  543. static int
  544. am79c961_hw_init(struct net_device *dev)
  545. {
  546. struct dev_priv *priv = netdev_priv(dev);
  547. spin_lock_irq(&priv->chip_lock);
  548. write_rreg (dev->base_addr, CSR0, CSR0_STOP);
  549. write_rreg (dev->base_addr, CSR3, CSR3_MASKALL);
  550. spin_unlock_irq(&priv->chip_lock);
  551. am79c961_ramtest(dev, 0x66);
  552. am79c961_ramtest(dev, 0x99);
  553. return 0;
  554. }
  555. static void __init am79c961_banner(void)
  556. {
  557. static unsigned version_printed;
  558. if (net_debug && version_printed++ == 0)
  559. printk(KERN_INFO "%s", version);
  560. }
  561. static const struct net_device_ops am79c961_netdev_ops = {
  562. .ndo_open = am79c961_open,
  563. .ndo_stop = am79c961_close,
  564. .ndo_start_xmit = am79c961_sendpacket,
  565. .ndo_set_multicast_list = am79c961_setmulticastlist,
  566. .ndo_tx_timeout = am79c961_timeout,
  567. .ndo_validate_addr = eth_validate_addr,
  568. .ndo_change_mtu = eth_change_mtu,
  569. .ndo_set_mac_address = eth_mac_addr,
  570. #ifdef CONFIG_NET_POLL_CONTROLLER
  571. .ndo_poll_controller = am79c961_poll_controller,
  572. #endif
  573. };
  574. static int __devinit am79c961_probe(struct platform_device *pdev)
  575. {
  576. struct resource *res;
  577. struct net_device *dev;
  578. struct dev_priv *priv;
  579. int i, ret;
  580. res = platform_get_resource(pdev, IORESOURCE_IO, 0);
  581. if (!res)
  582. return -ENODEV;
  583. dev = alloc_etherdev(sizeof(struct dev_priv));
  584. ret = -ENOMEM;
  585. if (!dev)
  586. goto out;
  587. SET_NETDEV_DEV(dev, &pdev->dev);
  588. priv = netdev_priv(dev);
  589. /*
  590. * Fixed address and IRQ lines here.
  591. * The PNP initialisation should have been
  592. * done by the ether bootp loader.
  593. */
  594. dev->base_addr = res->start;
  595. ret = platform_get_irq(pdev, 0);
  596. if (ret < 0) {
  597. ret = -ENODEV;
  598. goto nodev;
  599. }
  600. dev->irq = ret;
  601. ret = -ENODEV;
  602. if (!request_region(dev->base_addr, 0x18, dev->name))
  603. goto nodev;
  604. /*
  605. * Reset the device.
  606. */
  607. inb(dev->base_addr + NET_RESET);
  608. udelay(5);
  609. /*
  610. * Check the manufacturer part of the
  611. * ether address.
  612. */
  613. if (inb(dev->base_addr) != 0x08 ||
  614. inb(dev->base_addr + 2) != 0x00 ||
  615. inb(dev->base_addr + 4) != 0x2b)
  616. goto release;
  617. for (i = 0; i < 6; i++)
  618. dev->dev_addr[i] = inb(dev->base_addr + i * 2) & 0xff;
  619. am79c961_banner();
  620. spin_lock_init(&priv->chip_lock);
  621. init_timer(&priv->timer);
  622. priv->timer.data = (unsigned long)dev;
  623. priv->timer.function = am79c961_timer;
  624. if (am79c961_hw_init(dev))
  625. goto release;
  626. dev->netdev_ops = &am79c961_netdev_ops;
  627. ret = register_netdev(dev);
  628. if (ret == 0) {
  629. printk(KERN_INFO "%s: ether address %pM\n",
  630. dev->name, dev->dev_addr);
  631. return 0;
  632. }
  633. release:
  634. release_region(dev->base_addr, 0x18);
  635. nodev:
  636. free_netdev(dev);
  637. out:
  638. return ret;
  639. }
  640. static struct platform_driver am79c961_driver = {
  641. .probe = am79c961_probe,
  642. .driver = {
  643. .name = "am79c961",
  644. },
  645. };
  646. static int __init am79c961_init(void)
  647. {
  648. return platform_driver_register(&am79c961_driver);
  649. }
  650. __initcall(am79c961_init);