7990.c 21 KB

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  1. /*
  2. * 7990.c -- LANCE ethernet IC generic routines.
  3. * This is an attempt to separate out the bits of various ethernet
  4. * drivers that are common because they all use the AMD 7990 LANCE
  5. * (Local Area Network Controller for Ethernet) chip.
  6. *
  7. * Copyright (C) 05/1998 Peter Maydell <pmaydell@chiark.greenend.org.uk>
  8. *
  9. * Most of this stuff was obtained by looking at other LANCE drivers,
  10. * in particular a2065.[ch]. The AMD C-LANCE datasheet was also helpful.
  11. * NB: this was made easy by the fact that Jes Sorensen had cleaned up
  12. * most of a2025 and sunlance with the aim of merging them, so the
  13. * common code was pretty obvious.
  14. */
  15. #include <linux/crc32.h>
  16. #include <linux/delay.h>
  17. #include <linux/errno.h>
  18. #include <linux/netdevice.h>
  19. #include <linux/etherdevice.h>
  20. #include <linux/init.h>
  21. #include <linux/module.h>
  22. #include <linux/kernel.h>
  23. #include <linux/types.h>
  24. #include <linux/fcntl.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/ioport.h>
  27. #include <linux/in.h>
  28. #include <linux/route.h>
  29. #include <linux/string.h>
  30. #include <linux/skbuff.h>
  31. #include <asm/irq.h>
  32. /* Used for the temporal inet entries and routing */
  33. #include <linux/socket.h>
  34. #include <linux/bitops.h>
  35. #include <asm/system.h>
  36. #include <asm/io.h>
  37. #include <asm/dma.h>
  38. #include <asm/pgtable.h>
  39. #ifdef CONFIG_HP300
  40. #include <asm/blinken.h>
  41. #endif
  42. #include "7990.h"
  43. #define WRITERAP(lp,x) out_be16(lp->base + LANCE_RAP, (x))
  44. #define WRITERDP(lp,x) out_be16(lp->base + LANCE_RDP, (x))
  45. #define READRDP(lp) in_be16(lp->base + LANCE_RDP)
  46. #if defined(CONFIG_HPLANCE) || defined(CONFIG_HPLANCE_MODULE)
  47. #include "hplance.h"
  48. #undef WRITERAP
  49. #undef WRITERDP
  50. #undef READRDP
  51. #if defined(CONFIG_MVME147_NET) || defined(CONFIG_MVME147_NET_MODULE)
  52. /* Lossage Factor Nine, Mr Sulu. */
  53. #define WRITERAP(lp,x) (lp->writerap(lp,x))
  54. #define WRITERDP(lp,x) (lp->writerdp(lp,x))
  55. #define READRDP(lp) (lp->readrdp(lp))
  56. #else
  57. /* These inlines can be used if only CONFIG_HPLANCE is defined */
  58. static inline void WRITERAP(struct lance_private *lp, __u16 value)
  59. {
  60. do {
  61. out_be16(lp->base + HPLANCE_REGOFF + LANCE_RAP, value);
  62. } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
  63. }
  64. static inline void WRITERDP(struct lance_private *lp, __u16 value)
  65. {
  66. do {
  67. out_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP, value);
  68. } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
  69. }
  70. static inline __u16 READRDP(struct lance_private *lp)
  71. {
  72. __u16 value;
  73. do {
  74. value = in_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP);
  75. } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
  76. return value;
  77. }
  78. #endif
  79. #endif /* CONFIG_HPLANCE || CONFIG_HPLANCE_MODULE */
  80. /* debugging output macros, various flavours */
  81. /* #define TEST_HITS */
  82. #ifdef UNDEF
  83. #define PRINT_RINGS() \
  84. do { \
  85. int t; \
  86. for (t=0; t < RX_RING_SIZE; t++) { \
  87. printk("R%d: @(%02X %04X) len %04X, mblen %04X, bits %02X\n",\
  88. t, ib->brx_ring[t].rmd1_hadr, ib->brx_ring[t].rmd0,\
  89. ib->brx_ring[t].length,\
  90. ib->brx_ring[t].mblength, ib->brx_ring[t].rmd1_bits);\
  91. }\
  92. for (t=0; t < TX_RING_SIZE; t++) { \
  93. printk("T%d: @(%02X %04X) len %04X, misc %04X, bits %02X\n",\
  94. t, ib->btx_ring[t].tmd1_hadr, ib->btx_ring[t].tmd0,\
  95. ib->btx_ring[t].length,\
  96. ib->btx_ring[t].misc, ib->btx_ring[t].tmd1_bits);\
  97. }\
  98. } while (0)
  99. #else
  100. #define PRINT_RINGS()
  101. #endif
  102. /* Load the CSR registers. The LANCE has to be STOPped when we do this! */
  103. static void load_csrs (struct lance_private *lp)
  104. {
  105. volatile struct lance_init_block *aib = lp->lance_init_block;
  106. int leptr;
  107. leptr = LANCE_ADDR (aib);
  108. WRITERAP(lp, LE_CSR1); /* load address of init block */
  109. WRITERDP(lp, leptr & 0xFFFF);
  110. WRITERAP(lp, LE_CSR2);
  111. WRITERDP(lp, leptr >> 16);
  112. WRITERAP(lp, LE_CSR3);
  113. WRITERDP(lp, lp->busmaster_regval); /* set byteswap/ALEctrl/byte ctrl */
  114. /* Point back to csr0 */
  115. WRITERAP(lp, LE_CSR0);
  116. }
  117. /* #define to 0 or 1 appropriately */
  118. #define DEBUG_IRING 0
  119. /* Set up the Lance Rx and Tx rings and the init block */
  120. static void lance_init_ring (struct net_device *dev)
  121. {
  122. struct lance_private *lp = netdev_priv(dev);
  123. volatile struct lance_init_block *ib = lp->init_block;
  124. volatile struct lance_init_block *aib; /* for LANCE_ADDR computations */
  125. int leptr;
  126. int i;
  127. aib = lp->lance_init_block;
  128. lp->rx_new = lp->tx_new = 0;
  129. lp->rx_old = lp->tx_old = 0;
  130. ib->mode = LE_MO_PROM; /* normal, enable Tx & Rx */
  131. /* Copy the ethernet address to the lance init block
  132. * Notice that we do a byteswap if we're big endian.
  133. * [I think this is the right criterion; at least, sunlance,
  134. * a2065 and atarilance do the byteswap and lance.c (PC) doesn't.
  135. * However, the datasheet says that the BSWAP bit doesn't affect
  136. * the init block, so surely it should be low byte first for
  137. * everybody? Um.]
  138. * We could define the ib->physaddr as three 16bit values and
  139. * use (addr[1] << 8) | addr[0] & co, but this is more efficient.
  140. */
  141. #ifdef __BIG_ENDIAN
  142. ib->phys_addr [0] = dev->dev_addr [1];
  143. ib->phys_addr [1] = dev->dev_addr [0];
  144. ib->phys_addr [2] = dev->dev_addr [3];
  145. ib->phys_addr [3] = dev->dev_addr [2];
  146. ib->phys_addr [4] = dev->dev_addr [5];
  147. ib->phys_addr [5] = dev->dev_addr [4];
  148. #else
  149. for (i=0; i<6; i++)
  150. ib->phys_addr[i] = dev->dev_addr[i];
  151. #endif
  152. if (DEBUG_IRING)
  153. printk ("TX rings:\n");
  154. lp->tx_full = 0;
  155. /* Setup the Tx ring entries */
  156. for (i = 0; i < (1<<lp->lance_log_tx_bufs); i++) {
  157. leptr = LANCE_ADDR(&aib->tx_buf[i][0]);
  158. ib->btx_ring [i].tmd0 = leptr;
  159. ib->btx_ring [i].tmd1_hadr = leptr >> 16;
  160. ib->btx_ring [i].tmd1_bits = 0;
  161. ib->btx_ring [i].length = 0xf000; /* The ones required by tmd2 */
  162. ib->btx_ring [i].misc = 0;
  163. if (DEBUG_IRING)
  164. printk ("%d: 0x%8.8x\n", i, leptr);
  165. }
  166. /* Setup the Rx ring entries */
  167. if (DEBUG_IRING)
  168. printk ("RX rings:\n");
  169. for (i = 0; i < (1<<lp->lance_log_rx_bufs); i++) {
  170. leptr = LANCE_ADDR(&aib->rx_buf[i][0]);
  171. ib->brx_ring [i].rmd0 = leptr;
  172. ib->brx_ring [i].rmd1_hadr = leptr >> 16;
  173. ib->brx_ring [i].rmd1_bits = LE_R1_OWN;
  174. /* 0xf000 == bits that must be one (reserved, presumably) */
  175. ib->brx_ring [i].length = -RX_BUFF_SIZE | 0xf000;
  176. ib->brx_ring [i].mblength = 0;
  177. if (DEBUG_IRING)
  178. printk ("%d: 0x%8.8x\n", i, leptr);
  179. }
  180. /* Setup the initialization block */
  181. /* Setup rx descriptor pointer */
  182. leptr = LANCE_ADDR(&aib->brx_ring);
  183. ib->rx_len = (lp->lance_log_rx_bufs << 13) | (leptr >> 16);
  184. ib->rx_ptr = leptr;
  185. if (DEBUG_IRING)
  186. printk ("RX ptr: %8.8x\n", leptr);
  187. /* Setup tx descriptor pointer */
  188. leptr = LANCE_ADDR(&aib->btx_ring);
  189. ib->tx_len = (lp->lance_log_tx_bufs << 13) | (leptr >> 16);
  190. ib->tx_ptr = leptr;
  191. if (DEBUG_IRING)
  192. printk ("TX ptr: %8.8x\n", leptr);
  193. /* Clear the multicast filter */
  194. ib->filter [0] = 0;
  195. ib->filter [1] = 0;
  196. PRINT_RINGS();
  197. }
  198. /* LANCE must be STOPped before we do this, too... */
  199. static int init_restart_lance (struct lance_private *lp)
  200. {
  201. int i;
  202. WRITERAP(lp, LE_CSR0);
  203. WRITERDP(lp, LE_C0_INIT);
  204. /* Need a hook here for sunlance ledma stuff */
  205. /* Wait for the lance to complete initialization */
  206. for (i = 0; (i < 100) && !(READRDP(lp) & (LE_C0_ERR | LE_C0_IDON)); i++)
  207. barrier();
  208. if ((i == 100) || (READRDP(lp) & LE_C0_ERR)) {
  209. printk ("LANCE unopened after %d ticks, csr0=%4.4x.\n", i, READRDP(lp));
  210. return -1;
  211. }
  212. /* Clear IDON by writing a "1", enable interrupts and start lance */
  213. WRITERDP(lp, LE_C0_IDON);
  214. WRITERDP(lp, LE_C0_INEA | LE_C0_STRT);
  215. return 0;
  216. }
  217. static int lance_reset (struct net_device *dev)
  218. {
  219. struct lance_private *lp = netdev_priv(dev);
  220. int status;
  221. /* Stop the lance */
  222. WRITERAP(lp, LE_CSR0);
  223. WRITERDP(lp, LE_C0_STOP);
  224. load_csrs (lp);
  225. lance_init_ring (dev);
  226. dev->trans_start = jiffies; /* prevent tx timeout */
  227. status = init_restart_lance (lp);
  228. #ifdef DEBUG_DRIVER
  229. printk ("Lance restart=%d\n", status);
  230. #endif
  231. return status;
  232. }
  233. static int lance_rx (struct net_device *dev)
  234. {
  235. struct lance_private *lp = netdev_priv(dev);
  236. volatile struct lance_init_block *ib = lp->init_block;
  237. volatile struct lance_rx_desc *rd;
  238. unsigned char bits;
  239. #ifdef TEST_HITS
  240. int i;
  241. #endif
  242. #ifdef TEST_HITS
  243. printk ("[");
  244. for (i = 0; i < RX_RING_SIZE; i++) {
  245. if (i == lp->rx_new)
  246. printk ("%s",
  247. ib->brx_ring [i].rmd1_bits & LE_R1_OWN ? "_" : "X");
  248. else
  249. printk ("%s",
  250. ib->brx_ring [i].rmd1_bits & LE_R1_OWN ? "." : "1");
  251. }
  252. printk ("]");
  253. #endif
  254. #ifdef CONFIG_HP300
  255. blinken_leds(0x40, 0);
  256. #endif
  257. WRITERDP(lp, LE_C0_RINT | LE_C0_INEA); /* ack Rx int, reenable ints */
  258. for (rd = &ib->brx_ring [lp->rx_new]; /* For each Rx ring we own... */
  259. !((bits = rd->rmd1_bits) & LE_R1_OWN);
  260. rd = &ib->brx_ring [lp->rx_new]) {
  261. /* We got an incomplete frame? */
  262. if ((bits & LE_R1_POK) != LE_R1_POK) {
  263. dev->stats.rx_over_errors++;
  264. dev->stats.rx_errors++;
  265. continue;
  266. } else if (bits & LE_R1_ERR) {
  267. /* Count only the end frame as a rx error,
  268. * not the beginning
  269. */
  270. if (bits & LE_R1_BUF) dev->stats.rx_fifo_errors++;
  271. if (bits & LE_R1_CRC) dev->stats.rx_crc_errors++;
  272. if (bits & LE_R1_OFL) dev->stats.rx_over_errors++;
  273. if (bits & LE_R1_FRA) dev->stats.rx_frame_errors++;
  274. if (bits & LE_R1_EOP) dev->stats.rx_errors++;
  275. } else {
  276. int len = (rd->mblength & 0xfff) - 4;
  277. struct sk_buff *skb = dev_alloc_skb (len+2);
  278. if (!skb) {
  279. printk ("%s: Memory squeeze, deferring packet.\n",
  280. dev->name);
  281. dev->stats.rx_dropped++;
  282. rd->mblength = 0;
  283. rd->rmd1_bits = LE_R1_OWN;
  284. lp->rx_new = (lp->rx_new + 1) & lp->rx_ring_mod_mask;
  285. return 0;
  286. }
  287. skb_reserve (skb, 2); /* 16 byte align */
  288. skb_put (skb, len); /* make room */
  289. skb_copy_to_linear_data(skb,
  290. (unsigned char *)&(ib->rx_buf [lp->rx_new][0]),
  291. len);
  292. skb->protocol = eth_type_trans (skb, dev);
  293. netif_rx (skb);
  294. dev->stats.rx_packets++;
  295. dev->stats.rx_bytes += len;
  296. }
  297. /* Return the packet to the pool */
  298. rd->mblength = 0;
  299. rd->rmd1_bits = LE_R1_OWN;
  300. lp->rx_new = (lp->rx_new + 1) & lp->rx_ring_mod_mask;
  301. }
  302. return 0;
  303. }
  304. static int lance_tx (struct net_device *dev)
  305. {
  306. struct lance_private *lp = netdev_priv(dev);
  307. volatile struct lance_init_block *ib = lp->init_block;
  308. volatile struct lance_tx_desc *td;
  309. int i, j;
  310. int status;
  311. #ifdef CONFIG_HP300
  312. blinken_leds(0x80, 0);
  313. #endif
  314. /* csr0 is 2f3 */
  315. WRITERDP(lp, LE_C0_TINT | LE_C0_INEA);
  316. /* csr0 is 73 */
  317. j = lp->tx_old;
  318. for (i = j; i != lp->tx_new; i = j) {
  319. td = &ib->btx_ring [i];
  320. /* If we hit a packet not owned by us, stop */
  321. if (td->tmd1_bits & LE_T1_OWN)
  322. break;
  323. if (td->tmd1_bits & LE_T1_ERR) {
  324. status = td->misc;
  325. dev->stats.tx_errors++;
  326. if (status & LE_T3_RTY) dev->stats.tx_aborted_errors++;
  327. if (status & LE_T3_LCOL) dev->stats.tx_window_errors++;
  328. if (status & LE_T3_CLOS) {
  329. dev->stats.tx_carrier_errors++;
  330. if (lp->auto_select) {
  331. lp->tpe = 1 - lp->tpe;
  332. printk("%s: Carrier Lost, trying %s\n",
  333. dev->name, lp->tpe?"TPE":"AUI");
  334. /* Stop the lance */
  335. WRITERAP(lp, LE_CSR0);
  336. WRITERDP(lp, LE_C0_STOP);
  337. lance_init_ring (dev);
  338. load_csrs (lp);
  339. init_restart_lance (lp);
  340. return 0;
  341. }
  342. }
  343. /* buffer errors and underflows turn off the transmitter */
  344. /* Restart the adapter */
  345. if (status & (LE_T3_BUF|LE_T3_UFL)) {
  346. dev->stats.tx_fifo_errors++;
  347. printk ("%s: Tx: ERR_BUF|ERR_UFL, restarting\n",
  348. dev->name);
  349. /* Stop the lance */
  350. WRITERAP(lp, LE_CSR0);
  351. WRITERDP(lp, LE_C0_STOP);
  352. lance_init_ring (dev);
  353. load_csrs (lp);
  354. init_restart_lance (lp);
  355. return 0;
  356. }
  357. } else if ((td->tmd1_bits & LE_T1_POK) == LE_T1_POK) {
  358. /*
  359. * So we don't count the packet more than once.
  360. */
  361. td->tmd1_bits &= ~(LE_T1_POK);
  362. /* One collision before packet was sent. */
  363. if (td->tmd1_bits & LE_T1_EONE)
  364. dev->stats.collisions++;
  365. /* More than one collision, be optimistic. */
  366. if (td->tmd1_bits & LE_T1_EMORE)
  367. dev->stats.collisions += 2;
  368. dev->stats.tx_packets++;
  369. }
  370. j = (j + 1) & lp->tx_ring_mod_mask;
  371. }
  372. lp->tx_old = j;
  373. WRITERDP(lp, LE_C0_TINT | LE_C0_INEA);
  374. return 0;
  375. }
  376. static irqreturn_t
  377. lance_interrupt (int irq, void *dev_id)
  378. {
  379. struct net_device *dev = (struct net_device *)dev_id;
  380. struct lance_private *lp = netdev_priv(dev);
  381. int csr0;
  382. spin_lock (&lp->devlock);
  383. WRITERAP(lp, LE_CSR0); /* LANCE Controller Status */
  384. csr0 = READRDP(lp);
  385. PRINT_RINGS();
  386. if (!(csr0 & LE_C0_INTR)) { /* Check if any interrupt has */
  387. spin_unlock (&lp->devlock);
  388. return IRQ_NONE; /* been generated by the Lance. */
  389. }
  390. /* Acknowledge all the interrupt sources ASAP */
  391. WRITERDP(lp, csr0 & ~(LE_C0_INEA|LE_C0_TDMD|LE_C0_STOP|LE_C0_STRT|LE_C0_INIT));
  392. if ((csr0 & LE_C0_ERR)) {
  393. /* Clear the error condition */
  394. WRITERDP(lp, LE_C0_BABL|LE_C0_ERR|LE_C0_MISS|LE_C0_INEA);
  395. }
  396. if (csr0 & LE_C0_RINT)
  397. lance_rx (dev);
  398. if (csr0 & LE_C0_TINT)
  399. lance_tx (dev);
  400. /* Log misc errors. */
  401. if (csr0 & LE_C0_BABL)
  402. dev->stats.tx_errors++; /* Tx babble. */
  403. if (csr0 & LE_C0_MISS)
  404. dev->stats.rx_errors++; /* Missed a Rx frame. */
  405. if (csr0 & LE_C0_MERR) {
  406. printk("%s: Bus master arbitration failure, status %4.4x.\n",
  407. dev->name, csr0);
  408. /* Restart the chip. */
  409. WRITERDP(lp, LE_C0_STRT);
  410. }
  411. if (lp->tx_full && netif_queue_stopped(dev) && (TX_BUFFS_AVAIL >= 0)) {
  412. lp->tx_full = 0;
  413. netif_wake_queue (dev);
  414. }
  415. WRITERAP(lp, LE_CSR0);
  416. WRITERDP(lp, LE_C0_BABL|LE_C0_CERR|LE_C0_MISS|LE_C0_MERR|LE_C0_IDON|LE_C0_INEA);
  417. spin_unlock (&lp->devlock);
  418. return IRQ_HANDLED;
  419. }
  420. int lance_open (struct net_device *dev)
  421. {
  422. struct lance_private *lp = netdev_priv(dev);
  423. int res;
  424. /* Install the Interrupt handler. Or we could shunt this out to specific drivers? */
  425. if (request_irq(lp->irq, lance_interrupt, IRQF_SHARED, lp->name, dev))
  426. return -EAGAIN;
  427. res = lance_reset(dev);
  428. spin_lock_init(&lp->devlock);
  429. netif_start_queue (dev);
  430. return res;
  431. }
  432. EXPORT_SYMBOL_GPL(lance_open);
  433. int lance_close (struct net_device *dev)
  434. {
  435. struct lance_private *lp = netdev_priv(dev);
  436. netif_stop_queue (dev);
  437. /* Stop the LANCE */
  438. WRITERAP(lp, LE_CSR0);
  439. WRITERDP(lp, LE_C0_STOP);
  440. free_irq(lp->irq, dev);
  441. return 0;
  442. }
  443. EXPORT_SYMBOL_GPL(lance_close);
  444. void lance_tx_timeout(struct net_device *dev)
  445. {
  446. printk("lance_tx_timeout\n");
  447. lance_reset(dev);
  448. dev->trans_start = jiffies; /* prevent tx timeout */
  449. netif_wake_queue (dev);
  450. }
  451. EXPORT_SYMBOL_GPL(lance_tx_timeout);
  452. int lance_start_xmit (struct sk_buff *skb, struct net_device *dev)
  453. {
  454. struct lance_private *lp = netdev_priv(dev);
  455. volatile struct lance_init_block *ib = lp->init_block;
  456. int entry, skblen, len;
  457. static int outs;
  458. unsigned long flags;
  459. if (!TX_BUFFS_AVAIL)
  460. return NETDEV_TX_LOCKED;
  461. netif_stop_queue (dev);
  462. skblen = skb->len;
  463. #ifdef DEBUG_DRIVER
  464. /* dump the packet */
  465. {
  466. int i;
  467. for (i = 0; i < 64; i++) {
  468. if ((i % 16) == 0)
  469. printk ("\n");
  470. printk ("%2.2x ", skb->data [i]);
  471. }
  472. }
  473. #endif
  474. len = (skblen <= ETH_ZLEN) ? ETH_ZLEN : skblen;
  475. entry = lp->tx_new & lp->tx_ring_mod_mask;
  476. ib->btx_ring [entry].length = (-len) | 0xf000;
  477. ib->btx_ring [entry].misc = 0;
  478. if (skb->len < ETH_ZLEN)
  479. memset((void *)&ib->tx_buf[entry][0], 0, ETH_ZLEN);
  480. skb_copy_from_linear_data(skb, (void *)&ib->tx_buf[entry][0], skblen);
  481. /* Now, give the packet to the lance */
  482. ib->btx_ring [entry].tmd1_bits = (LE_T1_POK|LE_T1_OWN);
  483. lp->tx_new = (lp->tx_new+1) & lp->tx_ring_mod_mask;
  484. outs++;
  485. /* Kick the lance: transmit now */
  486. WRITERDP(lp, LE_C0_INEA | LE_C0_TDMD);
  487. dev_kfree_skb (skb);
  488. spin_lock_irqsave (&lp->devlock, flags);
  489. if (TX_BUFFS_AVAIL)
  490. netif_start_queue (dev);
  491. else
  492. lp->tx_full = 1;
  493. spin_unlock_irqrestore (&lp->devlock, flags);
  494. return NETDEV_TX_OK;
  495. }
  496. EXPORT_SYMBOL_GPL(lance_start_xmit);
  497. /* taken from the depca driver via a2065.c */
  498. static void lance_load_multicast (struct net_device *dev)
  499. {
  500. struct lance_private *lp = netdev_priv(dev);
  501. volatile struct lance_init_block *ib = lp->init_block;
  502. volatile u16 *mcast_table = (u16 *)&ib->filter;
  503. struct netdev_hw_addr *ha;
  504. char *addrs;
  505. u32 crc;
  506. /* set all multicast bits */
  507. if (dev->flags & IFF_ALLMULTI){
  508. ib->filter [0] = 0xffffffff;
  509. ib->filter [1] = 0xffffffff;
  510. return;
  511. }
  512. /* clear the multicast filter */
  513. ib->filter [0] = 0;
  514. ib->filter [1] = 0;
  515. /* Add addresses */
  516. netdev_for_each_mc_addr(ha, dev) {
  517. addrs = ha->addr;
  518. /* multicast address? */
  519. if (!(*addrs & 1))
  520. continue;
  521. crc = ether_crc_le(6, addrs);
  522. crc = crc >> 26;
  523. mcast_table [crc >> 4] |= 1 << (crc & 0xf);
  524. }
  525. }
  526. void lance_set_multicast (struct net_device *dev)
  527. {
  528. struct lance_private *lp = netdev_priv(dev);
  529. volatile struct lance_init_block *ib = lp->init_block;
  530. int stopped;
  531. stopped = netif_queue_stopped(dev);
  532. if (!stopped)
  533. netif_stop_queue (dev);
  534. while (lp->tx_old != lp->tx_new)
  535. schedule();
  536. WRITERAP(lp, LE_CSR0);
  537. WRITERDP(lp, LE_C0_STOP);
  538. lance_init_ring (dev);
  539. if (dev->flags & IFF_PROMISC) {
  540. ib->mode |= LE_MO_PROM;
  541. } else {
  542. ib->mode &= ~LE_MO_PROM;
  543. lance_load_multicast (dev);
  544. }
  545. load_csrs (lp);
  546. init_restart_lance (lp);
  547. if (!stopped)
  548. netif_start_queue (dev);
  549. }
  550. EXPORT_SYMBOL_GPL(lance_set_multicast);
  551. #ifdef CONFIG_NET_POLL_CONTROLLER
  552. void lance_poll(struct net_device *dev)
  553. {
  554. struct lance_private *lp = netdev_priv(dev);
  555. spin_lock (&lp->devlock);
  556. WRITERAP(lp, LE_CSR0);
  557. WRITERDP(lp, LE_C0_STRT);
  558. spin_unlock (&lp->devlock);
  559. lance_interrupt(dev->irq, dev);
  560. }
  561. #endif
  562. MODULE_LICENSE("GPL");