ad525x_dpot.c 20 KB

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  1. /*
  2. * ad525x_dpot: Driver for the Analog Devices digital potentiometers
  3. * Copyright (c) 2009-2010 Analog Devices, Inc.
  4. * Author: Michael Hennerich <hennerich@blackfin.uclinux.org>
  5. *
  6. * DEVID #Wipers #Positions Resistor Options (kOhm)
  7. * AD5258 1 64 1, 10, 50, 100
  8. * AD5259 1 256 5, 10, 50, 100
  9. * AD5251 2 64 1, 10, 50, 100
  10. * AD5252 2 256 1, 10, 50, 100
  11. * AD5255 3 512 25, 250
  12. * AD5253 4 64 1, 10, 50, 100
  13. * AD5254 4 256 1, 10, 50, 100
  14. * AD5160 1 256 5, 10, 50, 100
  15. * AD5161 1 256 5, 10, 50, 100
  16. * AD5162 2 256 2.5, 10, 50, 100
  17. * AD5165 1 256 100
  18. * AD5200 1 256 10, 50
  19. * AD5201 1 33 10, 50
  20. * AD5203 4 64 10, 100
  21. * AD5204 4 256 10, 50, 100
  22. * AD5206 6 256 10, 50, 100
  23. * AD5207 2 256 10, 50, 100
  24. * AD5231 1 1024 10, 50, 100
  25. * AD5232 2 256 10, 50, 100
  26. * AD5233 4 64 10, 50, 100
  27. * AD5235 2 1024 25, 250
  28. * AD5260 1 256 20, 50, 200
  29. * AD5262 2 256 20, 50, 200
  30. * AD5263 4 256 20, 50, 200
  31. * AD5290 1 256 10, 50, 100
  32. * AD5291 1 256 20, 50, 100 (20-TP)
  33. * AD5292 1 1024 20, 50, 100 (20-TP)
  34. * AD5293 1 1024 20, 50, 100
  35. * AD7376 1 128 10, 50, 100, 1M
  36. * AD8400 1 256 1, 10, 50, 100
  37. * AD8402 2 256 1, 10, 50, 100
  38. * AD8403 4 256 1, 10, 50, 100
  39. * ADN2850 3 512 25, 250
  40. * AD5241 1 256 10, 100, 1M
  41. * AD5246 1 128 5, 10, 50, 100
  42. * AD5247 1 128 5, 10, 50, 100
  43. * AD5245 1 256 5, 10, 50, 100
  44. * AD5243 2 256 2.5, 10, 50, 100
  45. * AD5248 2 256 2.5, 10, 50, 100
  46. * AD5242 2 256 20, 50, 200
  47. * AD5280 1 256 20, 50, 200
  48. * AD5282 2 256 20, 50, 200
  49. * ADN2860 3 512 25, 250
  50. * AD5273 1 64 1, 10, 50, 100 (OTP)
  51. * AD5171 1 64 5, 10, 50, 100 (OTP)
  52. * AD5170 1 256 2.5, 10, 50, 100 (OTP)
  53. * AD5172 2 256 2.5, 10, 50, 100 (OTP)
  54. * AD5173 2 256 2.5, 10, 50, 100 (OTP)
  55. * AD5270 1 1024 20, 50, 100 (50-TP)
  56. * AD5271 1 256 20, 50, 100 (50-TP)
  57. * AD5272 1 1024 20, 50, 100 (50-TP)
  58. * AD5274 1 256 20, 50, 100 (50-TP)
  59. *
  60. * See Documentation/misc-devices/ad525x_dpot.txt for more info.
  61. *
  62. * derived from ad5258.c
  63. * Copyright (c) 2009 Cyber Switching, Inc.
  64. * Author: Chris Verges <chrisv@cyberswitching.com>
  65. *
  66. * derived from ad5252.c
  67. * Copyright (c) 2006 Michael Hennerich <hennerich@blackfin.uclinux.org>
  68. *
  69. * Licensed under the GPL-2 or later.
  70. */
  71. #include <linux/module.h>
  72. #include <linux/device.h>
  73. #include <linux/kernel.h>
  74. #include <linux/init.h>
  75. #include <linux/delay.h>
  76. #include <linux/slab.h>
  77. #define DRIVER_VERSION "0.2"
  78. #include "ad525x_dpot.h"
  79. /*
  80. * Client data (each client gets its own)
  81. */
  82. struct dpot_data {
  83. struct ad_dpot_bus_data bdata;
  84. struct mutex update_lock;
  85. unsigned rdac_mask;
  86. unsigned max_pos;
  87. unsigned long devid;
  88. unsigned uid;
  89. unsigned feat;
  90. unsigned wipers;
  91. u16 rdac_cache[MAX_RDACS];
  92. DECLARE_BITMAP(otp_en_mask, MAX_RDACS);
  93. };
  94. static inline int dpot_read_d8(struct dpot_data *dpot)
  95. {
  96. return dpot->bdata.bops->read_d8(dpot->bdata.client);
  97. }
  98. static inline int dpot_read_r8d8(struct dpot_data *dpot, u8 reg)
  99. {
  100. return dpot->bdata.bops->read_r8d8(dpot->bdata.client, reg);
  101. }
  102. static inline int dpot_read_r8d16(struct dpot_data *dpot, u8 reg)
  103. {
  104. return dpot->bdata.bops->read_r8d16(dpot->bdata.client, reg);
  105. }
  106. static inline int dpot_write_d8(struct dpot_data *dpot, u8 val)
  107. {
  108. return dpot->bdata.bops->write_d8(dpot->bdata.client, val);
  109. }
  110. static inline int dpot_write_r8d8(struct dpot_data *dpot, u8 reg, u16 val)
  111. {
  112. return dpot->bdata.bops->write_r8d8(dpot->bdata.client, reg, val);
  113. }
  114. static inline int dpot_write_r8d16(struct dpot_data *dpot, u8 reg, u16 val)
  115. {
  116. return dpot->bdata.bops->write_r8d16(dpot->bdata.client, reg, val);
  117. }
  118. static s32 dpot_read_spi(struct dpot_data *dpot, u8 reg)
  119. {
  120. unsigned ctrl = 0;
  121. int value;
  122. if (!(reg & (DPOT_ADDR_EEPROM | DPOT_ADDR_CMD))) {
  123. if (dpot->feat & F_RDACS_WONLY)
  124. return dpot->rdac_cache[reg & DPOT_RDAC_MASK];
  125. if (dpot->uid == DPOT_UID(AD5291_ID) ||
  126. dpot->uid == DPOT_UID(AD5292_ID) ||
  127. dpot->uid == DPOT_UID(AD5293_ID)) {
  128. value = dpot_read_r8d8(dpot,
  129. DPOT_AD5291_READ_RDAC << 2);
  130. if (dpot->uid == DPOT_UID(AD5291_ID))
  131. value = value >> 2;
  132. return value;
  133. } else if (dpot->uid == DPOT_UID(AD5270_ID) ||
  134. dpot->uid == DPOT_UID(AD5271_ID)) {
  135. value = dpot_read_r8d8(dpot,
  136. DPOT_AD5270_1_2_4_READ_RDAC << 2);
  137. if (value < 0)
  138. return value;
  139. if (dpot->uid == DPOT_UID(AD5271_ID))
  140. value = value >> 2;
  141. return value;
  142. }
  143. ctrl = DPOT_SPI_READ_RDAC;
  144. } else if (reg & DPOT_ADDR_EEPROM) {
  145. ctrl = DPOT_SPI_READ_EEPROM;
  146. }
  147. if (dpot->feat & F_SPI_16BIT)
  148. return dpot_read_r8d8(dpot, ctrl);
  149. else if (dpot->feat & F_SPI_24BIT)
  150. return dpot_read_r8d16(dpot, ctrl);
  151. return -EFAULT;
  152. }
  153. static s32 dpot_read_i2c(struct dpot_data *dpot, u8 reg)
  154. {
  155. int value;
  156. unsigned ctrl = 0;
  157. switch (dpot->uid) {
  158. case DPOT_UID(AD5246_ID):
  159. case DPOT_UID(AD5247_ID):
  160. return dpot_read_d8(dpot);
  161. case DPOT_UID(AD5245_ID):
  162. case DPOT_UID(AD5241_ID):
  163. case DPOT_UID(AD5242_ID):
  164. case DPOT_UID(AD5243_ID):
  165. case DPOT_UID(AD5248_ID):
  166. case DPOT_UID(AD5280_ID):
  167. case DPOT_UID(AD5282_ID):
  168. ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ?
  169. 0 : DPOT_AD5282_RDAC_AB;
  170. return dpot_read_r8d8(dpot, ctrl);
  171. case DPOT_UID(AD5170_ID):
  172. case DPOT_UID(AD5171_ID):
  173. case DPOT_UID(AD5273_ID):
  174. return dpot_read_d8(dpot);
  175. case DPOT_UID(AD5172_ID):
  176. case DPOT_UID(AD5173_ID):
  177. ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ?
  178. 0 : DPOT_AD5172_3_A0;
  179. return dpot_read_r8d8(dpot, ctrl);
  180. case DPOT_UID(AD5272_ID):
  181. case DPOT_UID(AD5274_ID):
  182. dpot_write_r8d8(dpot,
  183. (DPOT_AD5270_1_2_4_READ_RDAC << 2), 0);
  184. value = dpot_read_r8d16(dpot,
  185. DPOT_AD5270_1_2_4_RDAC << 2);
  186. if (value < 0)
  187. return value;
  188. /*
  189. * AD5272/AD5274 returns high byte first, however
  190. * underling smbus expects low byte first.
  191. */
  192. value = swab16(value);
  193. if (dpot->uid == DPOT_UID(AD5271_ID))
  194. value = value >> 2;
  195. return value;
  196. default:
  197. if ((reg & DPOT_REG_TOL) || (dpot->max_pos > 256))
  198. return dpot_read_r8d16(dpot, (reg & 0xF8) |
  199. ((reg & 0x7) << 1));
  200. else
  201. return dpot_read_r8d8(dpot, reg);
  202. }
  203. }
  204. static s32 dpot_read(struct dpot_data *dpot, u8 reg)
  205. {
  206. if (dpot->feat & F_SPI)
  207. return dpot_read_spi(dpot, reg);
  208. else
  209. return dpot_read_i2c(dpot, reg);
  210. }
  211. static s32 dpot_write_spi(struct dpot_data *dpot, u8 reg, u16 value)
  212. {
  213. unsigned val = 0;
  214. if (!(reg & (DPOT_ADDR_EEPROM | DPOT_ADDR_CMD | DPOT_ADDR_OTP))) {
  215. if (dpot->feat & F_RDACS_WONLY)
  216. dpot->rdac_cache[reg & DPOT_RDAC_MASK] = value;
  217. if (dpot->feat & F_AD_APPDATA) {
  218. if (dpot->feat & F_SPI_8BIT) {
  219. val = ((reg & DPOT_RDAC_MASK) <<
  220. DPOT_MAX_POS(dpot->devid)) |
  221. value;
  222. return dpot_write_d8(dpot, val);
  223. } else if (dpot->feat & F_SPI_16BIT) {
  224. val = ((reg & DPOT_RDAC_MASK) <<
  225. DPOT_MAX_POS(dpot->devid)) |
  226. value;
  227. return dpot_write_r8d8(dpot, val >> 8,
  228. val & 0xFF);
  229. } else
  230. BUG();
  231. } else {
  232. if (dpot->uid == DPOT_UID(AD5291_ID) ||
  233. dpot->uid == DPOT_UID(AD5292_ID) ||
  234. dpot->uid == DPOT_UID(AD5293_ID)) {
  235. dpot_write_r8d8(dpot, DPOT_AD5291_CTRLREG << 2,
  236. DPOT_AD5291_UNLOCK_CMD);
  237. if (dpot->uid == DPOT_UID(AD5291_ID))
  238. value = value << 2;
  239. return dpot_write_r8d8(dpot,
  240. (DPOT_AD5291_RDAC << 2) |
  241. (value >> 8), value & 0xFF);
  242. } else if (dpot->uid == DPOT_UID(AD5270_ID) ||
  243. dpot->uid == DPOT_UID(AD5271_ID)) {
  244. dpot_write_r8d8(dpot,
  245. DPOT_AD5270_1_2_4_CTRLREG << 2,
  246. DPOT_AD5270_1_2_4_UNLOCK_CMD);
  247. if (dpot->uid == DPOT_UID(AD5271_ID))
  248. value = value << 2;
  249. return dpot_write_r8d8(dpot,
  250. (DPOT_AD5270_1_2_4_RDAC << 2) |
  251. (value >> 8), value & 0xFF);
  252. }
  253. val = DPOT_SPI_RDAC | (reg & DPOT_RDAC_MASK);
  254. }
  255. } else if (reg & DPOT_ADDR_EEPROM) {
  256. val = DPOT_SPI_EEPROM | (reg & DPOT_RDAC_MASK);
  257. } else if (reg & DPOT_ADDR_CMD) {
  258. switch (reg) {
  259. case DPOT_DEC_ALL_6DB:
  260. val = DPOT_SPI_DEC_ALL_6DB;
  261. break;
  262. case DPOT_INC_ALL_6DB:
  263. val = DPOT_SPI_INC_ALL_6DB;
  264. break;
  265. case DPOT_DEC_ALL:
  266. val = DPOT_SPI_DEC_ALL;
  267. break;
  268. case DPOT_INC_ALL:
  269. val = DPOT_SPI_INC_ALL;
  270. break;
  271. }
  272. } else if (reg & DPOT_ADDR_OTP) {
  273. if (dpot->uid == DPOT_UID(AD5291_ID) ||
  274. dpot->uid == DPOT_UID(AD5292_ID)) {
  275. return dpot_write_r8d8(dpot,
  276. DPOT_AD5291_STORE_XTPM << 2, 0);
  277. } else if (dpot->uid == DPOT_UID(AD5270_ID) ||
  278. dpot->uid == DPOT_UID(AD5271_ID)) {
  279. return dpot_write_r8d8(dpot,
  280. DPOT_AD5270_1_2_4_STORE_XTPM << 2, 0);
  281. }
  282. } else
  283. BUG();
  284. if (dpot->feat & F_SPI_16BIT)
  285. return dpot_write_r8d8(dpot, val, value);
  286. else if (dpot->feat & F_SPI_24BIT)
  287. return dpot_write_r8d16(dpot, val, value);
  288. return -EFAULT;
  289. }
  290. static s32 dpot_write_i2c(struct dpot_data *dpot, u8 reg, u16 value)
  291. {
  292. /* Only write the instruction byte for certain commands */
  293. unsigned tmp = 0, ctrl = 0;
  294. switch (dpot->uid) {
  295. case DPOT_UID(AD5246_ID):
  296. case DPOT_UID(AD5247_ID):
  297. return dpot_write_d8(dpot, value);
  298. break;
  299. case DPOT_UID(AD5245_ID):
  300. case DPOT_UID(AD5241_ID):
  301. case DPOT_UID(AD5242_ID):
  302. case DPOT_UID(AD5243_ID):
  303. case DPOT_UID(AD5248_ID):
  304. case DPOT_UID(AD5280_ID):
  305. case DPOT_UID(AD5282_ID):
  306. ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ?
  307. 0 : DPOT_AD5282_RDAC_AB;
  308. return dpot_write_r8d8(dpot, ctrl, value);
  309. break;
  310. case DPOT_UID(AD5171_ID):
  311. case DPOT_UID(AD5273_ID):
  312. if (reg & DPOT_ADDR_OTP) {
  313. tmp = dpot_read_d8(dpot);
  314. if (tmp >> 6) /* Ready to Program? */
  315. return -EFAULT;
  316. ctrl = DPOT_AD5273_FUSE;
  317. }
  318. return dpot_write_r8d8(dpot, ctrl, value);
  319. break;
  320. case DPOT_UID(AD5172_ID):
  321. case DPOT_UID(AD5173_ID):
  322. ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ?
  323. 0 : DPOT_AD5172_3_A0;
  324. if (reg & DPOT_ADDR_OTP) {
  325. tmp = dpot_read_r8d16(dpot, ctrl);
  326. if (tmp >> 14) /* Ready to Program? */
  327. return -EFAULT;
  328. ctrl |= DPOT_AD5170_2_3_FUSE;
  329. }
  330. return dpot_write_r8d8(dpot, ctrl, value);
  331. break;
  332. case DPOT_UID(AD5170_ID):
  333. if (reg & DPOT_ADDR_OTP) {
  334. tmp = dpot_read_r8d16(dpot, tmp);
  335. if (tmp >> 14) /* Ready to Program? */
  336. return -EFAULT;
  337. ctrl = DPOT_AD5170_2_3_FUSE;
  338. }
  339. return dpot_write_r8d8(dpot, ctrl, value);
  340. break;
  341. case DPOT_UID(AD5272_ID):
  342. case DPOT_UID(AD5274_ID):
  343. dpot_write_r8d8(dpot, DPOT_AD5270_1_2_4_CTRLREG << 2,
  344. DPOT_AD5270_1_2_4_UNLOCK_CMD);
  345. if (reg & DPOT_ADDR_OTP)
  346. return dpot_write_r8d8(dpot,
  347. DPOT_AD5270_1_2_4_STORE_XTPM << 2, 0);
  348. if (dpot->uid == DPOT_UID(AD5274_ID))
  349. value = value << 2;
  350. return dpot_write_r8d8(dpot, (DPOT_AD5270_1_2_4_RDAC << 2) |
  351. (value >> 8), value & 0xFF);
  352. break;
  353. default:
  354. if (reg & DPOT_ADDR_CMD)
  355. return dpot_write_d8(dpot, reg);
  356. if (dpot->max_pos > 256)
  357. return dpot_write_r8d16(dpot, (reg & 0xF8) |
  358. ((reg & 0x7) << 1), value);
  359. else
  360. /* All other registers require instruction + data bytes */
  361. return dpot_write_r8d8(dpot, reg, value);
  362. }
  363. }
  364. static s32 dpot_write(struct dpot_data *dpot, u8 reg, u16 value)
  365. {
  366. if (dpot->feat & F_SPI)
  367. return dpot_write_spi(dpot, reg, value);
  368. else
  369. return dpot_write_i2c(dpot, reg, value);
  370. }
  371. /* sysfs functions */
  372. static ssize_t sysfs_show_reg(struct device *dev,
  373. struct device_attribute *attr,
  374. char *buf, u32 reg)
  375. {
  376. struct dpot_data *data = dev_get_drvdata(dev);
  377. s32 value;
  378. if (reg & DPOT_ADDR_OTP_EN)
  379. return sprintf(buf, "%s\n",
  380. test_bit(DPOT_RDAC_MASK & reg, data->otp_en_mask) ?
  381. "enabled" : "disabled");
  382. mutex_lock(&data->update_lock);
  383. value = dpot_read(data, reg);
  384. mutex_unlock(&data->update_lock);
  385. if (value < 0)
  386. return -EINVAL;
  387. /*
  388. * Let someone else deal with converting this ...
  389. * the tolerance is a two-byte value where the MSB
  390. * is a sign + integer value, and the LSB is a
  391. * decimal value. See page 18 of the AD5258
  392. * datasheet (Rev. A) for more details.
  393. */
  394. if (reg & DPOT_REG_TOL)
  395. return sprintf(buf, "0x%04x\n", value & 0xFFFF);
  396. else
  397. return sprintf(buf, "%u\n", value & data->rdac_mask);
  398. }
  399. static ssize_t sysfs_set_reg(struct device *dev,
  400. struct device_attribute *attr,
  401. const char *buf, size_t count, u32 reg)
  402. {
  403. struct dpot_data *data = dev_get_drvdata(dev);
  404. unsigned long value;
  405. int err;
  406. if (reg & DPOT_ADDR_OTP_EN) {
  407. if (!strncmp(buf, "enabled", sizeof("enabled")))
  408. set_bit(DPOT_RDAC_MASK & reg, data->otp_en_mask);
  409. else
  410. clear_bit(DPOT_RDAC_MASK & reg, data->otp_en_mask);
  411. return count;
  412. }
  413. if ((reg & DPOT_ADDR_OTP) &&
  414. !test_bit(DPOT_RDAC_MASK & reg, data->otp_en_mask))
  415. return -EPERM;
  416. err = strict_strtoul(buf, 10, &value);
  417. if (err)
  418. return err;
  419. if (value > data->rdac_mask)
  420. value = data->rdac_mask;
  421. mutex_lock(&data->update_lock);
  422. dpot_write(data, reg, value);
  423. if (reg & DPOT_ADDR_EEPROM)
  424. msleep(26); /* Sleep while the EEPROM updates */
  425. else if (reg & DPOT_ADDR_OTP)
  426. msleep(400); /* Sleep while the OTP updates */
  427. mutex_unlock(&data->update_lock);
  428. return count;
  429. }
  430. static ssize_t sysfs_do_cmd(struct device *dev,
  431. struct device_attribute *attr,
  432. const char *buf, size_t count, u32 reg)
  433. {
  434. struct dpot_data *data = dev_get_drvdata(dev);
  435. mutex_lock(&data->update_lock);
  436. dpot_write(data, reg, 0);
  437. mutex_unlock(&data->update_lock);
  438. return count;
  439. }
  440. /* ------------------------------------------------------------------------- */
  441. #define DPOT_DEVICE_SHOW(_name, _reg) static ssize_t \
  442. show_##_name(struct device *dev, \
  443. struct device_attribute *attr, char *buf) \
  444. { \
  445. return sysfs_show_reg(dev, attr, buf, _reg); \
  446. }
  447. #define DPOT_DEVICE_SET(_name, _reg) static ssize_t \
  448. set_##_name(struct device *dev, \
  449. struct device_attribute *attr, \
  450. const char *buf, size_t count) \
  451. { \
  452. return sysfs_set_reg(dev, attr, buf, count, _reg); \
  453. }
  454. #define DPOT_DEVICE_SHOW_SET(name, reg) \
  455. DPOT_DEVICE_SHOW(name, reg) \
  456. DPOT_DEVICE_SET(name, reg) \
  457. static DEVICE_ATTR(name, S_IWUSR | S_IRUGO, show_##name, set_##name);
  458. #define DPOT_DEVICE_SHOW_ONLY(name, reg) \
  459. DPOT_DEVICE_SHOW(name, reg) \
  460. static DEVICE_ATTR(name, S_IWUSR | S_IRUGO, show_##name, NULL);
  461. DPOT_DEVICE_SHOW_SET(rdac0, DPOT_ADDR_RDAC | DPOT_RDAC0);
  462. DPOT_DEVICE_SHOW_SET(eeprom0, DPOT_ADDR_EEPROM | DPOT_RDAC0);
  463. DPOT_DEVICE_SHOW_ONLY(tolerance0, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC0);
  464. DPOT_DEVICE_SHOW_SET(otp0, DPOT_ADDR_OTP | DPOT_RDAC0);
  465. DPOT_DEVICE_SHOW_SET(otp0en, DPOT_ADDR_OTP_EN | DPOT_RDAC0);
  466. DPOT_DEVICE_SHOW_SET(rdac1, DPOT_ADDR_RDAC | DPOT_RDAC1);
  467. DPOT_DEVICE_SHOW_SET(eeprom1, DPOT_ADDR_EEPROM | DPOT_RDAC1);
  468. DPOT_DEVICE_SHOW_ONLY(tolerance1, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC1);
  469. DPOT_DEVICE_SHOW_SET(otp1, DPOT_ADDR_OTP | DPOT_RDAC1);
  470. DPOT_DEVICE_SHOW_SET(otp1en, DPOT_ADDR_OTP_EN | DPOT_RDAC1);
  471. DPOT_DEVICE_SHOW_SET(rdac2, DPOT_ADDR_RDAC | DPOT_RDAC2);
  472. DPOT_DEVICE_SHOW_SET(eeprom2, DPOT_ADDR_EEPROM | DPOT_RDAC2);
  473. DPOT_DEVICE_SHOW_ONLY(tolerance2, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC2);
  474. DPOT_DEVICE_SHOW_SET(otp2, DPOT_ADDR_OTP | DPOT_RDAC2);
  475. DPOT_DEVICE_SHOW_SET(otp2en, DPOT_ADDR_OTP_EN | DPOT_RDAC2);
  476. DPOT_DEVICE_SHOW_SET(rdac3, DPOT_ADDR_RDAC | DPOT_RDAC3);
  477. DPOT_DEVICE_SHOW_SET(eeprom3, DPOT_ADDR_EEPROM | DPOT_RDAC3);
  478. DPOT_DEVICE_SHOW_ONLY(tolerance3, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC3);
  479. DPOT_DEVICE_SHOW_SET(otp3, DPOT_ADDR_OTP | DPOT_RDAC3);
  480. DPOT_DEVICE_SHOW_SET(otp3en, DPOT_ADDR_OTP_EN | DPOT_RDAC3);
  481. DPOT_DEVICE_SHOW_SET(rdac4, DPOT_ADDR_RDAC | DPOT_RDAC4);
  482. DPOT_DEVICE_SHOW_SET(eeprom4, DPOT_ADDR_EEPROM | DPOT_RDAC4);
  483. DPOT_DEVICE_SHOW_ONLY(tolerance4, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC4);
  484. DPOT_DEVICE_SHOW_SET(otp4, DPOT_ADDR_OTP | DPOT_RDAC4);
  485. DPOT_DEVICE_SHOW_SET(otp4en, DPOT_ADDR_OTP_EN | DPOT_RDAC4);
  486. DPOT_DEVICE_SHOW_SET(rdac5, DPOT_ADDR_RDAC | DPOT_RDAC5);
  487. DPOT_DEVICE_SHOW_SET(eeprom5, DPOT_ADDR_EEPROM | DPOT_RDAC5);
  488. DPOT_DEVICE_SHOW_ONLY(tolerance5, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC5);
  489. DPOT_DEVICE_SHOW_SET(otp5, DPOT_ADDR_OTP | DPOT_RDAC5);
  490. DPOT_DEVICE_SHOW_SET(otp5en, DPOT_ADDR_OTP_EN | DPOT_RDAC5);
  491. static const struct attribute *dpot_attrib_wipers[] = {
  492. &dev_attr_rdac0.attr,
  493. &dev_attr_rdac1.attr,
  494. &dev_attr_rdac2.attr,
  495. &dev_attr_rdac3.attr,
  496. &dev_attr_rdac4.attr,
  497. &dev_attr_rdac5.attr,
  498. NULL
  499. };
  500. static const struct attribute *dpot_attrib_eeprom[] = {
  501. &dev_attr_eeprom0.attr,
  502. &dev_attr_eeprom1.attr,
  503. &dev_attr_eeprom2.attr,
  504. &dev_attr_eeprom3.attr,
  505. &dev_attr_eeprom4.attr,
  506. &dev_attr_eeprom5.attr,
  507. NULL
  508. };
  509. static const struct attribute *dpot_attrib_otp[] = {
  510. &dev_attr_otp0.attr,
  511. &dev_attr_otp1.attr,
  512. &dev_attr_otp2.attr,
  513. &dev_attr_otp3.attr,
  514. &dev_attr_otp4.attr,
  515. &dev_attr_otp5.attr,
  516. NULL
  517. };
  518. static const struct attribute *dpot_attrib_otp_en[] = {
  519. &dev_attr_otp0en.attr,
  520. &dev_attr_otp1en.attr,
  521. &dev_attr_otp2en.attr,
  522. &dev_attr_otp3en.attr,
  523. &dev_attr_otp4en.attr,
  524. &dev_attr_otp5en.attr,
  525. NULL
  526. };
  527. static const struct attribute *dpot_attrib_tolerance[] = {
  528. &dev_attr_tolerance0.attr,
  529. &dev_attr_tolerance1.attr,
  530. &dev_attr_tolerance2.attr,
  531. &dev_attr_tolerance3.attr,
  532. &dev_attr_tolerance4.attr,
  533. &dev_attr_tolerance5.attr,
  534. NULL
  535. };
  536. /* ------------------------------------------------------------------------- */
  537. #define DPOT_DEVICE_DO_CMD(_name, _cmd) static ssize_t \
  538. set_##_name(struct device *dev, \
  539. struct device_attribute *attr, \
  540. const char *buf, size_t count) \
  541. { \
  542. return sysfs_do_cmd(dev, attr, buf, count, _cmd); \
  543. } \
  544. static DEVICE_ATTR(_name, S_IWUSR | S_IRUGO, NULL, set_##_name);
  545. DPOT_DEVICE_DO_CMD(inc_all, DPOT_INC_ALL);
  546. DPOT_DEVICE_DO_CMD(dec_all, DPOT_DEC_ALL);
  547. DPOT_DEVICE_DO_CMD(inc_all_6db, DPOT_INC_ALL_6DB);
  548. DPOT_DEVICE_DO_CMD(dec_all_6db, DPOT_DEC_ALL_6DB);
  549. static struct attribute *ad525x_attributes_commands[] = {
  550. &dev_attr_inc_all.attr,
  551. &dev_attr_dec_all.attr,
  552. &dev_attr_inc_all_6db.attr,
  553. &dev_attr_dec_all_6db.attr,
  554. NULL
  555. };
  556. static const struct attribute_group ad525x_group_commands = {
  557. .attrs = ad525x_attributes_commands,
  558. };
  559. __devinit int ad_dpot_add_files(struct device *dev,
  560. unsigned features, unsigned rdac)
  561. {
  562. int err = sysfs_create_file(&dev->kobj,
  563. dpot_attrib_wipers[rdac]);
  564. if (features & F_CMD_EEP)
  565. err |= sysfs_create_file(&dev->kobj,
  566. dpot_attrib_eeprom[rdac]);
  567. if (features & F_CMD_TOL)
  568. err |= sysfs_create_file(&dev->kobj,
  569. dpot_attrib_tolerance[rdac]);
  570. if (features & F_CMD_OTP) {
  571. err |= sysfs_create_file(&dev->kobj,
  572. dpot_attrib_otp_en[rdac]);
  573. err |= sysfs_create_file(&dev->kobj,
  574. dpot_attrib_otp[rdac]);
  575. }
  576. if (err)
  577. dev_err(dev, "failed to register sysfs hooks for RDAC%d\n",
  578. rdac);
  579. return err;
  580. }
  581. inline void ad_dpot_remove_files(struct device *dev,
  582. unsigned features, unsigned rdac)
  583. {
  584. sysfs_remove_file(&dev->kobj,
  585. dpot_attrib_wipers[rdac]);
  586. if (features & F_CMD_EEP)
  587. sysfs_remove_file(&dev->kobj,
  588. dpot_attrib_eeprom[rdac]);
  589. if (features & F_CMD_TOL)
  590. sysfs_remove_file(&dev->kobj,
  591. dpot_attrib_tolerance[rdac]);
  592. if (features & F_CMD_OTP) {
  593. sysfs_remove_file(&dev->kobj,
  594. dpot_attrib_otp_en[rdac]);
  595. sysfs_remove_file(&dev->kobj,
  596. dpot_attrib_otp[rdac]);
  597. }
  598. }
  599. __devinit int ad_dpot_probe(struct device *dev,
  600. struct ad_dpot_bus_data *bdata, const struct ad_dpot_id *id)
  601. {
  602. struct dpot_data *data;
  603. int i, err = 0;
  604. data = kzalloc(sizeof(struct dpot_data), GFP_KERNEL);
  605. if (!data) {
  606. err = -ENOMEM;
  607. goto exit;
  608. }
  609. dev_set_drvdata(dev, data);
  610. mutex_init(&data->update_lock);
  611. data->bdata = *bdata;
  612. data->devid = id->devid;
  613. data->max_pos = 1 << DPOT_MAX_POS(data->devid);
  614. data->rdac_mask = data->max_pos - 1;
  615. data->feat = DPOT_FEAT(data->devid);
  616. data->uid = DPOT_UID(data->devid);
  617. data->wipers = DPOT_WIPERS(data->devid);
  618. for (i = DPOT_RDAC0; i < MAX_RDACS; i++)
  619. if (data->wipers & (1 << i)) {
  620. err = ad_dpot_add_files(dev, data->feat, i);
  621. if (err)
  622. goto exit_remove_files;
  623. /* power-up midscale */
  624. if (data->feat & F_RDACS_WONLY)
  625. data->rdac_cache[i] = data->max_pos / 2;
  626. }
  627. if (data->feat & F_CMD_INC)
  628. err = sysfs_create_group(&dev->kobj, &ad525x_group_commands);
  629. if (err) {
  630. dev_err(dev, "failed to register sysfs hooks\n");
  631. goto exit_free;
  632. }
  633. dev_info(dev, "%s %d-Position Digital Potentiometer registered\n",
  634. id->name, data->max_pos);
  635. return 0;
  636. exit_remove_files:
  637. for (i = DPOT_RDAC0; i < MAX_RDACS; i++)
  638. if (data->wipers & (1 << i))
  639. ad_dpot_remove_files(dev, data->feat, i);
  640. exit_free:
  641. kfree(data);
  642. dev_set_drvdata(dev, NULL);
  643. exit:
  644. dev_err(dev, "failed to create client for %s ID 0x%lX\n",
  645. id->name, id->devid);
  646. return err;
  647. }
  648. EXPORT_SYMBOL(ad_dpot_probe);
  649. __devexit int ad_dpot_remove(struct device *dev)
  650. {
  651. struct dpot_data *data = dev_get_drvdata(dev);
  652. int i;
  653. for (i = DPOT_RDAC0; i < MAX_RDACS; i++)
  654. if (data->wipers & (1 << i))
  655. ad_dpot_remove_files(dev, data->feat, i);
  656. kfree(data);
  657. return 0;
  658. }
  659. EXPORT_SYMBOL(ad_dpot_remove);
  660. MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>, "
  661. "Michael Hennerich <hennerich@blackfin.uclinux.org>");
  662. MODULE_DESCRIPTION("Digital potentiometer driver");
  663. MODULE_LICENSE("GPL");
  664. MODULE_VERSION(DRIVER_VERSION);