wm8400-core.c 13 KB

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  1. /*
  2. * Core driver for WM8400.
  3. *
  4. * Copyright 2008 Wolfson Microelectronics PLC.
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of the
  11. * License, or (at your option) any later version.
  12. *
  13. */
  14. #include <linux/bug.h>
  15. #include <linux/i2c.h>
  16. #include <linux/kernel.h>
  17. #include <linux/mfd/core.h>
  18. #include <linux/mfd/wm8400-private.h>
  19. #include <linux/mfd/wm8400-audio.h>
  20. #include <linux/slab.h>
  21. static struct {
  22. u16 readable; /* Mask of readable bits */
  23. u16 writable; /* Mask of writable bits */
  24. u16 vol; /* Mask of volatile bits */
  25. int is_codec; /* Register controlled by codec reset */
  26. u16 default_val; /* Value on reset */
  27. } reg_data[] = {
  28. { 0xFFFF, 0xFFFF, 0x0000, 0, 0x6172 }, /* R0 */
  29. { 0x7000, 0x0000, 0x8000, 0, 0x0000 }, /* R1 */
  30. { 0xFF17, 0xFF17, 0x0000, 0, 0x0000 }, /* R2 */
  31. { 0xEBF3, 0xEBF3, 0x0000, 1, 0x6000 }, /* R3 */
  32. { 0x3CF3, 0x3CF3, 0x0000, 1, 0x0000 }, /* R4 */
  33. { 0xF1F8, 0xF1F8, 0x0000, 1, 0x4050 }, /* R5 */
  34. { 0xFC1F, 0xFC1F, 0x0000, 1, 0x4000 }, /* R6 */
  35. { 0xDFDE, 0xDFDE, 0x0000, 1, 0x01C8 }, /* R7 */
  36. { 0xFCFC, 0xFCFC, 0x0000, 1, 0x0000 }, /* R8 */
  37. { 0xEFFF, 0xEFFF, 0x0000, 1, 0x0040 }, /* R9 */
  38. { 0xEFFF, 0xEFFF, 0x0000, 1, 0x0040 }, /* R10 */
  39. { 0x27F7, 0x27F7, 0x0000, 1, 0x0004 }, /* R11 */
  40. { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R12 */
  41. { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R13 */
  42. { 0x1FEF, 0x1FEF, 0x0000, 1, 0x0000 }, /* R14 */
  43. { 0x0163, 0x0163, 0x0000, 1, 0x0100 }, /* R15 */
  44. { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R16 */
  45. { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R17 */
  46. { 0x1FFF, 0x0FFF, 0x0000, 1, 0x0000 }, /* R18 */
  47. { 0xFFFF, 0xFFFF, 0x0000, 1, 0x1000 }, /* R19 */
  48. { 0xFFFF, 0xFFFF, 0x0000, 1, 0x1010 }, /* R20 */
  49. { 0xFFFF, 0xFFFF, 0x0000, 1, 0x1010 }, /* R21 */
  50. { 0x0FDD, 0x0FDD, 0x0000, 1, 0x8000 }, /* R22 */
  51. { 0x1FFF, 0x1FFF, 0x0000, 1, 0x0800 }, /* R23 */
  52. { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R24 */
  53. { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R25 */
  54. { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R26 */
  55. { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R27 */
  56. { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R28 */
  57. { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R29 */
  58. { 0x0000, 0x0077, 0x0000, 1, 0x0066 }, /* R30 */
  59. { 0x0000, 0x0033, 0x0000, 1, 0x0022 }, /* R31 */
  60. { 0x0000, 0x01FF, 0x0000, 1, 0x0079 }, /* R32 */
  61. { 0x0000, 0x01FF, 0x0000, 1, 0x0079 }, /* R33 */
  62. { 0x0000, 0x0003, 0x0000, 1, 0x0003 }, /* R34 */
  63. { 0x0000, 0x01FF, 0x0000, 1, 0x0003 }, /* R35 */
  64. { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R36 */
  65. { 0x0000, 0x003F, 0x0000, 1, 0x0100 }, /* R37 */
  66. { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R38 */
  67. { 0x0000, 0x000F, 0x0000, 0, 0x0000 }, /* R39 */
  68. { 0x0000, 0x00FF, 0x0000, 1, 0x0000 }, /* R40 */
  69. { 0x0000, 0x01B7, 0x0000, 1, 0x0000 }, /* R41 */
  70. { 0x0000, 0x01B7, 0x0000, 1, 0x0000 }, /* R42 */
  71. { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R43 */
  72. { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R44 */
  73. { 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R45 */
  74. { 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R46 */
  75. { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R47 */
  76. { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R48 */
  77. { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R49 */
  78. { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R50 */
  79. { 0x0000, 0x01B3, 0x0000, 1, 0x0180 }, /* R51 */
  80. { 0x0000, 0x0077, 0x0000, 1, 0x0000 }, /* R52 */
  81. { 0x0000, 0x0077, 0x0000, 1, 0x0000 }, /* R53 */
  82. { 0x0000, 0x00FF, 0x0000, 1, 0x0000 }, /* R54 */
  83. { 0x0000, 0x0001, 0x0000, 1, 0x0000 }, /* R55 */
  84. { 0x0000, 0x003F, 0x0000, 1, 0x0000 }, /* R56 */
  85. { 0x0000, 0x004F, 0x0000, 1, 0x0000 }, /* R57 */
  86. { 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R58 */
  87. { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R59 */
  88. { 0x1FFF, 0x1FFF, 0x0000, 1, 0x0000 }, /* R60 */
  89. { 0xFFFF, 0xFFFF, 0x0000, 1, 0x0000 }, /* R61 */
  90. { 0x03FF, 0x03FF, 0x0000, 1, 0x0000 }, /* R62 */
  91. { 0x007F, 0x007F, 0x0000, 1, 0x0000 }, /* R63 */
  92. { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R64 */
  93. { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R65 */
  94. { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R66 */
  95. { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R67 */
  96. { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R68 */
  97. { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R69 */
  98. { 0xFFFF, 0xFFFF, 0x0000, 0, 0x4400 }, /* R70 */
  99. { 0x23FF, 0x23FF, 0x0000, 0, 0x0000 }, /* R71 */
  100. { 0xFFFF, 0xFFFF, 0x0000, 0, 0x4400 }, /* R72 */
  101. { 0x23FF, 0x23FF, 0x0000, 0, 0x0000 }, /* R73 */
  102. { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R74 */
  103. { 0x000E, 0x000E, 0x0000, 0, 0x0008 }, /* R75 */
  104. { 0xE00F, 0xE00F, 0x0000, 0, 0x0000 }, /* R76 */
  105. { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R77 */
  106. { 0x03C0, 0x03C0, 0x0000, 0, 0x02C0 }, /* R78 */
  107. { 0xFFFF, 0x0000, 0xffff, 0, 0x0000 }, /* R79 */
  108. { 0xFFFF, 0xFFFF, 0x0000, 0, 0x0000 }, /* R80 */
  109. { 0xFFFF, 0x0000, 0xffff, 0, 0x0000 }, /* R81 */
  110. { 0x2BFF, 0x0000, 0xffff, 0, 0x0000 }, /* R82 */
  111. { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R83 */
  112. { 0x80FF, 0x80FF, 0x0000, 0, 0x00ff }, /* R84 */
  113. };
  114. static int wm8400_read(struct wm8400 *wm8400, u8 reg, int num_regs, u16 *dest)
  115. {
  116. int i, ret = 0;
  117. BUG_ON(reg + num_regs > ARRAY_SIZE(wm8400->reg_cache));
  118. /* If there are any volatile reads then read back the entire block */
  119. for (i = reg; i < reg + num_regs; i++)
  120. if (reg_data[i].vol) {
  121. ret = wm8400->read_dev(wm8400->io_data, reg,
  122. num_regs, dest);
  123. if (ret != 0)
  124. return ret;
  125. for (i = 0; i < num_regs; i++)
  126. dest[i] = be16_to_cpu(dest[i]);
  127. return 0;
  128. }
  129. /* Otherwise use the cache */
  130. memcpy(dest, &wm8400->reg_cache[reg], num_regs * sizeof(u16));
  131. return 0;
  132. }
  133. static int wm8400_write(struct wm8400 *wm8400, u8 reg, int num_regs,
  134. u16 *src)
  135. {
  136. int ret, i;
  137. BUG_ON(reg + num_regs > ARRAY_SIZE(wm8400->reg_cache));
  138. for (i = 0; i < num_regs; i++) {
  139. BUG_ON(!reg_data[reg + i].writable);
  140. wm8400->reg_cache[reg + i] = src[i];
  141. src[i] = cpu_to_be16(src[i]);
  142. }
  143. /* Do the actual I/O */
  144. ret = wm8400->write_dev(wm8400->io_data, reg, num_regs, src);
  145. if (ret != 0)
  146. return -EIO;
  147. return 0;
  148. }
  149. /**
  150. * wm8400_reg_read - Single register read
  151. *
  152. * @wm8400: Pointer to wm8400 control structure
  153. * @reg: Register to read
  154. *
  155. * @return Read value
  156. */
  157. u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg)
  158. {
  159. u16 val;
  160. mutex_lock(&wm8400->io_lock);
  161. wm8400_read(wm8400, reg, 1, &val);
  162. mutex_unlock(&wm8400->io_lock);
  163. return val;
  164. }
  165. EXPORT_SYMBOL_GPL(wm8400_reg_read);
  166. int wm8400_block_read(struct wm8400 *wm8400, u8 reg, int count, u16 *data)
  167. {
  168. int ret;
  169. mutex_lock(&wm8400->io_lock);
  170. ret = wm8400_read(wm8400, reg, count, data);
  171. mutex_unlock(&wm8400->io_lock);
  172. return ret;
  173. }
  174. EXPORT_SYMBOL_GPL(wm8400_block_read);
  175. /**
  176. * wm8400_set_bits - Bitmask write
  177. *
  178. * @wm8400: Pointer to wm8400 control structure
  179. * @reg: Register to access
  180. * @mask: Mask of bits to change
  181. * @val: Value to set for masked bits
  182. */
  183. int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, u16 mask, u16 val)
  184. {
  185. u16 tmp;
  186. int ret;
  187. mutex_lock(&wm8400->io_lock);
  188. ret = wm8400_read(wm8400, reg, 1, &tmp);
  189. tmp = (tmp & ~mask) | val;
  190. if (ret == 0)
  191. ret = wm8400_write(wm8400, reg, 1, &tmp);
  192. mutex_unlock(&wm8400->io_lock);
  193. return ret;
  194. }
  195. EXPORT_SYMBOL_GPL(wm8400_set_bits);
  196. /**
  197. * wm8400_reset_codec_reg_cache - Reset cached codec registers to
  198. * their default values.
  199. */
  200. void wm8400_reset_codec_reg_cache(struct wm8400 *wm8400)
  201. {
  202. int i;
  203. mutex_lock(&wm8400->io_lock);
  204. /* Reset all codec registers to their initial value */
  205. for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
  206. if (reg_data[i].is_codec)
  207. wm8400->reg_cache[i] = reg_data[i].default_val;
  208. mutex_unlock(&wm8400->io_lock);
  209. }
  210. EXPORT_SYMBOL_GPL(wm8400_reset_codec_reg_cache);
  211. static int wm8400_register_codec(struct wm8400 *wm8400)
  212. {
  213. struct mfd_cell cell = {
  214. .name = "wm8400-codec",
  215. .platform_data = wm8400,
  216. .pdata_size = sizeof(*wm8400),
  217. };
  218. return mfd_add_devices(wm8400->dev, -1, &cell, 1, NULL, 0);
  219. }
  220. /*
  221. * wm8400_init - Generic initialisation
  222. *
  223. * The WM8400 can be configured as either an I2C or SPI device. Probe
  224. * functions for each bus set up the accessors then call into this to
  225. * set up the device itself.
  226. */
  227. static int wm8400_init(struct wm8400 *wm8400,
  228. struct wm8400_platform_data *pdata)
  229. {
  230. u16 reg;
  231. int ret, i;
  232. mutex_init(&wm8400->io_lock);
  233. dev_set_drvdata(wm8400->dev, wm8400);
  234. /* Check that this is actually a WM8400 */
  235. ret = wm8400->read_dev(wm8400->io_data, WM8400_RESET_ID, 1, &reg);
  236. if (ret != 0) {
  237. dev_err(wm8400->dev, "Chip ID register read failed\n");
  238. return -EIO;
  239. }
  240. if (be16_to_cpu(reg) != reg_data[WM8400_RESET_ID].default_val) {
  241. dev_err(wm8400->dev, "Device is not a WM8400, ID is %x\n",
  242. be16_to_cpu(reg));
  243. return -ENODEV;
  244. }
  245. /* We don't know what state the hardware is in and since this
  246. * is a PMIC we can't reset it safely so initialise the register
  247. * cache from the hardware.
  248. */
  249. ret = wm8400->read_dev(wm8400->io_data, 0,
  250. ARRAY_SIZE(wm8400->reg_cache),
  251. wm8400->reg_cache);
  252. if (ret != 0) {
  253. dev_err(wm8400->dev, "Register cache read failed\n");
  254. return -EIO;
  255. }
  256. for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
  257. wm8400->reg_cache[i] = be16_to_cpu(wm8400->reg_cache[i]);
  258. /* If the codec is in reset use hard coded values */
  259. if (!(wm8400->reg_cache[WM8400_POWER_MANAGEMENT_1] & WM8400_CODEC_ENA))
  260. for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
  261. if (reg_data[i].is_codec)
  262. wm8400->reg_cache[i] = reg_data[i].default_val;
  263. ret = wm8400_read(wm8400, WM8400_ID, 1, &reg);
  264. if (ret != 0) {
  265. dev_err(wm8400->dev, "ID register read failed: %d\n", ret);
  266. return ret;
  267. }
  268. reg = (reg & WM8400_CHIP_REV_MASK) >> WM8400_CHIP_REV_SHIFT;
  269. dev_info(wm8400->dev, "WM8400 revision %x\n", reg);
  270. ret = wm8400_register_codec(wm8400);
  271. if (ret != 0) {
  272. dev_err(wm8400->dev, "Failed to register codec\n");
  273. goto err_children;
  274. }
  275. if (pdata && pdata->platform_init) {
  276. ret = pdata->platform_init(wm8400->dev);
  277. if (ret != 0) {
  278. dev_err(wm8400->dev, "Platform init failed: %d\n",
  279. ret);
  280. goto err_children;
  281. }
  282. } else
  283. dev_warn(wm8400->dev, "No platform initialisation supplied\n");
  284. return 0;
  285. err_children:
  286. mfd_remove_devices(wm8400->dev);
  287. return ret;
  288. }
  289. static void wm8400_release(struct wm8400 *wm8400)
  290. {
  291. mfd_remove_devices(wm8400->dev);
  292. }
  293. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  294. static int wm8400_i2c_read(void *io_data, char reg, int count, u16 *dest)
  295. {
  296. struct i2c_client *i2c = io_data;
  297. struct i2c_msg xfer[2];
  298. int ret;
  299. /* Write register */
  300. xfer[0].addr = i2c->addr;
  301. xfer[0].flags = 0;
  302. xfer[0].len = 1;
  303. xfer[0].buf = &reg;
  304. /* Read data */
  305. xfer[1].addr = i2c->addr;
  306. xfer[1].flags = I2C_M_RD;
  307. xfer[1].len = count * sizeof(u16);
  308. xfer[1].buf = (u8 *)dest;
  309. ret = i2c_transfer(i2c->adapter, xfer, 2);
  310. if (ret == 2)
  311. ret = 0;
  312. else if (ret >= 0)
  313. ret = -EIO;
  314. return ret;
  315. }
  316. static int wm8400_i2c_write(void *io_data, char reg, int count, const u16 *src)
  317. {
  318. struct i2c_client *i2c = io_data;
  319. u8 *msg;
  320. int ret;
  321. /* We add 1 byte for device register - ideally I2C would gather. */
  322. msg = kmalloc((count * sizeof(u16)) + 1, GFP_KERNEL);
  323. if (msg == NULL)
  324. return -ENOMEM;
  325. msg[0] = reg;
  326. memcpy(&msg[1], src, count * sizeof(u16));
  327. ret = i2c_master_send(i2c, msg, (count * sizeof(u16)) + 1);
  328. if (ret == (count * 2) + 1)
  329. ret = 0;
  330. else if (ret >= 0)
  331. ret = -EIO;
  332. kfree(msg);
  333. return ret;
  334. }
  335. static int wm8400_i2c_probe(struct i2c_client *i2c,
  336. const struct i2c_device_id *id)
  337. {
  338. struct wm8400 *wm8400;
  339. int ret;
  340. wm8400 = kzalloc(sizeof(struct wm8400), GFP_KERNEL);
  341. if (wm8400 == NULL) {
  342. ret = -ENOMEM;
  343. goto err;
  344. }
  345. wm8400->io_data = i2c;
  346. wm8400->read_dev = wm8400_i2c_read;
  347. wm8400->write_dev = wm8400_i2c_write;
  348. wm8400->dev = &i2c->dev;
  349. i2c_set_clientdata(i2c, wm8400);
  350. ret = wm8400_init(wm8400, i2c->dev.platform_data);
  351. if (ret != 0)
  352. goto struct_err;
  353. return 0;
  354. struct_err:
  355. kfree(wm8400);
  356. err:
  357. return ret;
  358. }
  359. static int wm8400_i2c_remove(struct i2c_client *i2c)
  360. {
  361. struct wm8400 *wm8400 = i2c_get_clientdata(i2c);
  362. wm8400_release(wm8400);
  363. kfree(wm8400);
  364. return 0;
  365. }
  366. static const struct i2c_device_id wm8400_i2c_id[] = {
  367. { "wm8400", 0 },
  368. { }
  369. };
  370. MODULE_DEVICE_TABLE(i2c, wm8400_i2c_id);
  371. static struct i2c_driver wm8400_i2c_driver = {
  372. .driver = {
  373. .name = "WM8400",
  374. .owner = THIS_MODULE,
  375. },
  376. .probe = wm8400_i2c_probe,
  377. .remove = wm8400_i2c_remove,
  378. .id_table = wm8400_i2c_id,
  379. };
  380. #endif
  381. static int __init wm8400_module_init(void)
  382. {
  383. int ret = -ENODEV;
  384. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  385. ret = i2c_add_driver(&wm8400_i2c_driver);
  386. if (ret != 0)
  387. pr_err("Failed to register I2C driver: %d\n", ret);
  388. #endif
  389. return ret;
  390. }
  391. subsys_initcall(wm8400_module_init);
  392. static void __exit wm8400_module_exit(void)
  393. {
  394. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  395. i2c_del_driver(&wm8400_i2c_driver);
  396. #endif
  397. }
  398. module_exit(wm8400_module_exit);
  399. MODULE_LICENSE("GPL");
  400. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");