twl6030-irq.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376
  1. /*
  2. * twl6030-irq.c - TWL6030 irq support
  3. *
  4. * Copyright (C) 2005-2009 Texas Instruments, Inc.
  5. *
  6. * Modifications to defer interrupt handling to a kernel thread:
  7. * Copyright (C) 2006 MontaVista Software, Inc.
  8. *
  9. * Based on tlv320aic23.c:
  10. * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
  11. *
  12. * Code cleanup and modifications to IRQ handler.
  13. * by syed khasim <x0khasim@ti.com>
  14. *
  15. * TWL6030 specific code and IRQ handling changes by
  16. * Jagadeesh Bhaskar Pakaravoor <j-pakaravoor@ti.com>
  17. * Balaji T K <balajitk@ti.com>
  18. *
  19. * This program is free software; you can redistribute it and/or modify
  20. * it under the terms of the GNU General Public License as published by
  21. * the Free Software Foundation; either version 2 of the License, or
  22. * (at your option) any later version.
  23. *
  24. * This program is distributed in the hope that it will be useful,
  25. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  27. * GNU General Public License for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License
  30. * along with this program; if not, write to the Free Software
  31. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  32. */
  33. #include <linux/init.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/irq.h>
  36. #include <linux/kthread.h>
  37. #include <linux/i2c/twl.h>
  38. #include <linux/platform_device.h>
  39. #include "twl-core.h"
  40. /*
  41. * TWL6030 (unlike its predecessors, which had two level interrupt handling)
  42. * three interrupt registers INT_STS_A, INT_STS_B and INT_STS_C.
  43. * It exposes status bits saying who has raised an interrupt. There are
  44. * three mask registers that corresponds to these status registers, that
  45. * enables/disables these interrupts.
  46. *
  47. * We set up IRQs starting at a platform-specified base. An interrupt map table,
  48. * specifies mapping between interrupt number and the associated module.
  49. *
  50. */
  51. static int twl6030_interrupt_mapping[24] = {
  52. PWR_INTR_OFFSET, /* Bit 0 PWRON */
  53. PWR_INTR_OFFSET, /* Bit 1 RPWRON */
  54. PWR_INTR_OFFSET, /* Bit 2 BAT_VLOW */
  55. RTC_INTR_OFFSET, /* Bit 3 RTC_ALARM */
  56. RTC_INTR_OFFSET, /* Bit 4 RTC_PERIOD */
  57. HOTDIE_INTR_OFFSET, /* Bit 5 HOT_DIE */
  58. SMPSLDO_INTR_OFFSET, /* Bit 6 VXXX_SHORT */
  59. SMPSLDO_INTR_OFFSET, /* Bit 7 VMMC_SHORT */
  60. SMPSLDO_INTR_OFFSET, /* Bit 8 VUSIM_SHORT */
  61. BATDETECT_INTR_OFFSET, /* Bit 9 BAT */
  62. SIMDETECT_INTR_OFFSET, /* Bit 10 SIM */
  63. MMCDETECT_INTR_OFFSET, /* Bit 11 MMC */
  64. RSV_INTR_OFFSET, /* Bit 12 Reserved */
  65. MADC_INTR_OFFSET, /* Bit 13 GPADC_RT_EOC */
  66. MADC_INTR_OFFSET, /* Bit 14 GPADC_SW_EOC */
  67. GASGAUGE_INTR_OFFSET, /* Bit 15 CC_AUTOCAL */
  68. USBOTG_INTR_OFFSET, /* Bit 16 ID_WKUP */
  69. USBOTG_INTR_OFFSET, /* Bit 17 VBUS_WKUP */
  70. USBOTG_INTR_OFFSET, /* Bit 18 ID */
  71. USB_PRES_INTR_OFFSET, /* Bit 19 VBUS */
  72. CHARGER_INTR_OFFSET, /* Bit 20 CHRG_CTRL */
  73. CHARGERFAULT_INTR_OFFSET, /* Bit 21 EXT_CHRG */
  74. CHARGERFAULT_INTR_OFFSET, /* Bit 22 INT_CHRG */
  75. RSV_INTR_OFFSET, /* Bit 23 Reserved */
  76. };
  77. /*----------------------------------------------------------------------*/
  78. static unsigned twl6030_irq_base;
  79. static struct completion irq_event;
  80. /*
  81. * This thread processes interrupts reported by the Primary Interrupt Handler.
  82. */
  83. static int twl6030_irq_thread(void *data)
  84. {
  85. long irq = (long)data;
  86. static unsigned i2c_errors;
  87. static const unsigned max_i2c_errors = 100;
  88. int ret;
  89. current->flags |= PF_NOFREEZE;
  90. while (!kthread_should_stop()) {
  91. int i;
  92. union {
  93. u8 bytes[4];
  94. u32 int_sts;
  95. } sts;
  96. /* Wait for IRQ, then read PIH irq status (also blocking) */
  97. wait_for_completion_interruptible(&irq_event);
  98. /* read INT_STS_A, B and C in one shot using a burst read */
  99. ret = twl_i2c_read(TWL_MODULE_PIH, sts.bytes,
  100. REG_INT_STS_A, 3);
  101. if (ret) {
  102. pr_warning("twl6030: I2C error %d reading PIH ISR\n",
  103. ret);
  104. if (++i2c_errors >= max_i2c_errors) {
  105. printk(KERN_ERR "Maximum I2C error count"
  106. " exceeded. Terminating %s.\n",
  107. __func__);
  108. break;
  109. }
  110. complete(&irq_event);
  111. continue;
  112. }
  113. sts.bytes[3] = 0; /* Only 24 bits are valid*/
  114. /*
  115. * Since VBUS status bit is not reliable for VBUS disconnect
  116. * use CHARGER VBUS detection status bit instead.
  117. */
  118. if (sts.bytes[2] & 0x10)
  119. sts.bytes[2] |= 0x08;
  120. for (i = 0; sts.int_sts; sts.int_sts >>= 1, i++) {
  121. local_irq_disable();
  122. if (sts.int_sts & 0x1) {
  123. int module_irq = twl6030_irq_base +
  124. twl6030_interrupt_mapping[i];
  125. generic_handle_irq(module_irq);
  126. }
  127. local_irq_enable();
  128. }
  129. /*
  130. * NOTE:
  131. * Simulation confirms that documentation is wrong w.r.t the
  132. * interrupt status clear operation. A single *byte* write to
  133. * any one of STS_A to STS_C register results in all three
  134. * STS registers being reset. Since it does not matter which
  135. * value is written, all three registers are cleared on a
  136. * single byte write, so we just use 0x0 to clear.
  137. */
  138. ret = twl_i2c_write_u8(TWL_MODULE_PIH, 0x00, REG_INT_STS_A);
  139. if (ret)
  140. pr_warning("twl6030: I2C error in clearing PIH ISR\n");
  141. enable_irq(irq);
  142. }
  143. return 0;
  144. }
  145. /*
  146. * handle_twl6030_int() is the desc->handle method for the twl6030 interrupt.
  147. * This is a chained interrupt, so there is no desc->action method for it.
  148. * Now we need to query the interrupt controller in the twl6030 to determine
  149. * which module is generating the interrupt request. However, we can't do i2c
  150. * transactions in interrupt context, so we must defer that work to a kernel
  151. * thread. All we do here is acknowledge and mask the interrupt and wakeup
  152. * the kernel thread.
  153. */
  154. static irqreturn_t handle_twl6030_pih(int irq, void *devid)
  155. {
  156. disable_irq_nosync(irq);
  157. complete(devid);
  158. return IRQ_HANDLED;
  159. }
  160. /*----------------------------------------------------------------------*/
  161. static inline void activate_irq(int irq)
  162. {
  163. #ifdef CONFIG_ARM
  164. /* ARM requires an extra step to clear IRQ_NOREQUEST, which it
  165. * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
  166. */
  167. set_irq_flags(irq, IRQF_VALID);
  168. #else
  169. /* same effect on other architectures */
  170. irq_set_noprobe(irq);
  171. #endif
  172. }
  173. /*----------------------------------------------------------------------*/
  174. static unsigned twl6030_irq_next;
  175. /*----------------------------------------------------------------------*/
  176. int twl6030_interrupt_unmask(u8 bit_mask, u8 offset)
  177. {
  178. int ret;
  179. u8 unmask_value;
  180. ret = twl_i2c_read_u8(TWL_MODULE_PIH, &unmask_value,
  181. REG_INT_STS_A + offset);
  182. unmask_value &= (~(bit_mask));
  183. ret |= twl_i2c_write_u8(TWL_MODULE_PIH, unmask_value,
  184. REG_INT_STS_A + offset); /* unmask INT_MSK_A/B/C */
  185. return ret;
  186. }
  187. EXPORT_SYMBOL(twl6030_interrupt_unmask);
  188. int twl6030_interrupt_mask(u8 bit_mask, u8 offset)
  189. {
  190. int ret;
  191. u8 mask_value;
  192. ret = twl_i2c_read_u8(TWL_MODULE_PIH, &mask_value,
  193. REG_INT_STS_A + offset);
  194. mask_value |= (bit_mask);
  195. ret |= twl_i2c_write_u8(TWL_MODULE_PIH, mask_value,
  196. REG_INT_STS_A + offset); /* mask INT_MSK_A/B/C */
  197. return ret;
  198. }
  199. EXPORT_SYMBOL(twl6030_interrupt_mask);
  200. int twl6030_mmc_card_detect_config(void)
  201. {
  202. int ret;
  203. u8 reg_val = 0;
  204. /* Unmasking the Card detect Interrupt line for MMC1 from Phoenix */
  205. twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
  206. REG_INT_MSK_LINE_B);
  207. twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
  208. REG_INT_MSK_STS_B);
  209. /*
  210. * Initially Configuring MMC_CTRL for receiving interrupts &
  211. * Card status on TWL6030 for MMC1
  212. */
  213. ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val, TWL6030_MMCCTRL);
  214. if (ret < 0) {
  215. pr_err("twl6030: Failed to read MMCCTRL, error %d\n", ret);
  216. return ret;
  217. }
  218. reg_val &= ~VMMC_AUTO_OFF;
  219. reg_val |= SW_FC;
  220. ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL);
  221. if (ret < 0) {
  222. pr_err("twl6030: Failed to write MMCCTRL, error %d\n", ret);
  223. return ret;
  224. }
  225. /* Configuring PullUp-PullDown register */
  226. ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val,
  227. TWL6030_CFG_INPUT_PUPD3);
  228. if (ret < 0) {
  229. pr_err("twl6030: Failed to read CFG_INPUT_PUPD3, error %d\n",
  230. ret);
  231. return ret;
  232. }
  233. reg_val &= ~(MMC_PU | MMC_PD);
  234. ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val,
  235. TWL6030_CFG_INPUT_PUPD3);
  236. if (ret < 0) {
  237. pr_err("twl6030: Failed to write CFG_INPUT_PUPD3, error %d\n",
  238. ret);
  239. return ret;
  240. }
  241. return 0;
  242. }
  243. EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
  244. int twl6030_mmc_card_detect(struct device *dev, int slot)
  245. {
  246. int ret = -EIO;
  247. u8 read_reg = 0;
  248. struct platform_device *pdev = to_platform_device(dev);
  249. if (pdev->id) {
  250. /* TWL6030 provide's Card detect support for
  251. * only MMC1 controller.
  252. */
  253. pr_err("Unknown MMC controller %d in %s\n", pdev->id, __func__);
  254. return ret;
  255. }
  256. /*
  257. * BIT0 of MMC_CTRL on TWL6030 provides card status for MMC1
  258. * 0 - Card not present ,1 - Card present
  259. */
  260. ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &read_reg,
  261. TWL6030_MMCCTRL);
  262. if (ret >= 0)
  263. ret = read_reg & STS_MMC;
  264. return ret;
  265. }
  266. EXPORT_SYMBOL(twl6030_mmc_card_detect);
  267. int twl6030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end)
  268. {
  269. int status = 0;
  270. int i;
  271. struct task_struct *task;
  272. int ret;
  273. u8 mask[4];
  274. static struct irq_chip twl6030_irq_chip;
  275. mask[1] = 0xFF;
  276. mask[2] = 0xFF;
  277. mask[3] = 0xFF;
  278. ret = twl_i2c_write(TWL_MODULE_PIH, &mask[0],
  279. REG_INT_MSK_LINE_A, 3); /* MASK ALL INT LINES */
  280. ret = twl_i2c_write(TWL_MODULE_PIH, &mask[0],
  281. REG_INT_MSK_STS_A, 3); /* MASK ALL INT STS */
  282. ret = twl_i2c_write(TWL_MODULE_PIH, &mask[0],
  283. REG_INT_STS_A, 3); /* clear INT_STS_A,B,C */
  284. twl6030_irq_base = irq_base;
  285. /* install an irq handler for each of the modules;
  286. * clone dummy irq_chip since PIH can't *do* anything
  287. */
  288. twl6030_irq_chip = dummy_irq_chip;
  289. twl6030_irq_chip.name = "twl6030";
  290. twl6030_irq_chip.irq_set_type = NULL;
  291. for (i = irq_base; i < irq_end; i++) {
  292. irq_set_chip_and_handler(i, &twl6030_irq_chip,
  293. handle_simple_irq);
  294. activate_irq(i);
  295. }
  296. twl6030_irq_next = i;
  297. pr_info("twl6030: %s (irq %d) chaining IRQs %d..%d\n", "PIH",
  298. irq_num, irq_base, twl6030_irq_next - 1);
  299. /* install an irq handler to demultiplex the TWL6030 interrupt */
  300. init_completion(&irq_event);
  301. task = kthread_run(twl6030_irq_thread, (void *)irq_num, "twl6030-irq");
  302. if (IS_ERR(task)) {
  303. pr_err("twl6030: could not create irq %d thread!\n", irq_num);
  304. status = PTR_ERR(task);
  305. goto fail_kthread;
  306. }
  307. status = request_irq(irq_num, handle_twl6030_pih, IRQF_DISABLED,
  308. "TWL6030-PIH", &irq_event);
  309. if (status < 0) {
  310. pr_err("twl6030: could not claim irq%d: %d\n", irq_num, status);
  311. goto fail_irq;
  312. }
  313. return status;
  314. fail_irq:
  315. free_irq(irq_num, &irq_event);
  316. fail_kthread:
  317. for (i = irq_base; i < irq_end; i++)
  318. irq_set_chip_and_handler(i, NULL, NULL);
  319. return status;
  320. }
  321. int twl6030_exit_irq(void)
  322. {
  323. if (twl6030_irq_base) {
  324. pr_err("twl6030: can't yet clean up IRQs?\n");
  325. return -ENOSYS;
  326. }
  327. return 0;
  328. }