twl4030-power.c 13 KB

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  1. /*
  2. * linux/drivers/i2c/chips/twl4030-power.c
  3. *
  4. * Handle TWL4030 Power initialization
  5. *
  6. * Copyright (C) 2008 Nokia Corporation
  7. * Copyright (C) 2006 Texas Instruments, Inc
  8. *
  9. * Written by Kalle Jokiniemi
  10. * Peter De Schrijver <peter.de-schrijver@nokia.com>
  11. * Several fixes by Amit Kucheria <amit.kucheria@verdurent.com>
  12. *
  13. * This file is subject to the terms and conditions of the GNU General
  14. * Public License. See the file "COPYING" in the main directory of this
  15. * archive for more details.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  25. */
  26. #include <linux/module.h>
  27. #include <linux/pm.h>
  28. #include <linux/i2c/twl.h>
  29. #include <linux/platform_device.h>
  30. #include <asm/mach-types.h>
  31. static u8 twl4030_start_script_address = 0x2b;
  32. #define PWR_P1_SW_EVENTS 0x10
  33. #define PWR_DEVOFF (1<<0)
  34. #define PHY_TO_OFF_PM_MASTER(p) (p - 0x36)
  35. #define PHY_TO_OFF_PM_RECEIVER(p) (p - 0x5b)
  36. /* resource - hfclk */
  37. #define R_HFCLKOUT_DEV_GRP PHY_TO_OFF_PM_RECEIVER(0xe6)
  38. /* PM events */
  39. #define R_P1_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x46)
  40. #define R_P2_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x47)
  41. #define R_P3_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x48)
  42. #define R_CFG_P1_TRANSITION PHY_TO_OFF_PM_MASTER(0x36)
  43. #define R_CFG_P2_TRANSITION PHY_TO_OFF_PM_MASTER(0x37)
  44. #define R_CFG_P3_TRANSITION PHY_TO_OFF_PM_MASTER(0x38)
  45. #define LVL_WAKEUP 0x08
  46. #define ENABLE_WARMRESET (1<<4)
  47. #define END_OF_SCRIPT 0x3f
  48. #define R_SEQ_ADD_A2S PHY_TO_OFF_PM_MASTER(0x55)
  49. #define R_SEQ_ADD_S2A12 PHY_TO_OFF_PM_MASTER(0x56)
  50. #define R_SEQ_ADD_S2A3 PHY_TO_OFF_PM_MASTER(0x57)
  51. #define R_SEQ_ADD_WARM PHY_TO_OFF_PM_MASTER(0x58)
  52. #define R_MEMORY_ADDRESS PHY_TO_OFF_PM_MASTER(0x59)
  53. #define R_MEMORY_DATA PHY_TO_OFF_PM_MASTER(0x5a)
  54. /* resource configuration registers
  55. <RESOURCE>_DEV_GRP at address 'n+0'
  56. <RESOURCE>_TYPE at address 'n+1'
  57. <RESOURCE>_REMAP at address 'n+2'
  58. <RESOURCE>_DEDICATED at address 'n+3'
  59. */
  60. #define DEV_GRP_OFFSET 0
  61. #define TYPE_OFFSET 1
  62. #define REMAP_OFFSET 2
  63. #define DEDICATED_OFFSET 3
  64. /* Bit positions in the registers */
  65. /* <RESOURCE>_DEV_GRP */
  66. #define DEV_GRP_SHIFT 5
  67. #define DEV_GRP_MASK (7 << DEV_GRP_SHIFT)
  68. /* <RESOURCE>_TYPE */
  69. #define TYPE_SHIFT 0
  70. #define TYPE_MASK (7 << TYPE_SHIFT)
  71. #define TYPE2_SHIFT 3
  72. #define TYPE2_MASK (3 << TYPE2_SHIFT)
  73. /* <RESOURCE>_REMAP */
  74. #define SLEEP_STATE_SHIFT 0
  75. #define SLEEP_STATE_MASK (0xf << SLEEP_STATE_SHIFT)
  76. #define OFF_STATE_SHIFT 4
  77. #define OFF_STATE_MASK (0xf << OFF_STATE_SHIFT)
  78. static u8 res_config_addrs[] = {
  79. [RES_VAUX1] = 0x17,
  80. [RES_VAUX2] = 0x1b,
  81. [RES_VAUX3] = 0x1f,
  82. [RES_VAUX4] = 0x23,
  83. [RES_VMMC1] = 0x27,
  84. [RES_VMMC2] = 0x2b,
  85. [RES_VPLL1] = 0x2f,
  86. [RES_VPLL2] = 0x33,
  87. [RES_VSIM] = 0x37,
  88. [RES_VDAC] = 0x3b,
  89. [RES_VINTANA1] = 0x3f,
  90. [RES_VINTANA2] = 0x43,
  91. [RES_VINTDIG] = 0x47,
  92. [RES_VIO] = 0x4b,
  93. [RES_VDD1] = 0x55,
  94. [RES_VDD2] = 0x63,
  95. [RES_VUSB_1V5] = 0x71,
  96. [RES_VUSB_1V8] = 0x74,
  97. [RES_VUSB_3V1] = 0x77,
  98. [RES_VUSBCP] = 0x7a,
  99. [RES_REGEN] = 0x7f,
  100. [RES_NRES_PWRON] = 0x82,
  101. [RES_CLKEN] = 0x85,
  102. [RES_SYSEN] = 0x88,
  103. [RES_HFCLKOUT] = 0x8b,
  104. [RES_32KCLKOUT] = 0x8e,
  105. [RES_RESET] = 0x91,
  106. [RES_MAIN_REF] = 0x94,
  107. };
  108. static int __init twl4030_write_script_byte(u8 address, u8 byte)
  109. {
  110. int err;
  111. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
  112. R_MEMORY_ADDRESS);
  113. if (err)
  114. goto out;
  115. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, byte,
  116. R_MEMORY_DATA);
  117. out:
  118. return err;
  119. }
  120. static int __init twl4030_write_script_ins(u8 address, u16 pmb_message,
  121. u8 delay, u8 next)
  122. {
  123. int err;
  124. address *= 4;
  125. err = twl4030_write_script_byte(address++, pmb_message >> 8);
  126. if (err)
  127. goto out;
  128. err = twl4030_write_script_byte(address++, pmb_message & 0xff);
  129. if (err)
  130. goto out;
  131. err = twl4030_write_script_byte(address++, delay);
  132. if (err)
  133. goto out;
  134. err = twl4030_write_script_byte(address++, next);
  135. out:
  136. return err;
  137. }
  138. static int __init twl4030_write_script(u8 address, struct twl4030_ins *script,
  139. int len)
  140. {
  141. int err;
  142. for (; len; len--, address++, script++) {
  143. if (len == 1) {
  144. err = twl4030_write_script_ins(address,
  145. script->pmb_message,
  146. script->delay,
  147. END_OF_SCRIPT);
  148. if (err)
  149. break;
  150. } else {
  151. err = twl4030_write_script_ins(address,
  152. script->pmb_message,
  153. script->delay,
  154. address + 1);
  155. if (err)
  156. break;
  157. }
  158. }
  159. return err;
  160. }
  161. static int __init twl4030_config_wakeup3_sequence(u8 address)
  162. {
  163. int err;
  164. u8 data;
  165. /* Set SLEEP to ACTIVE SEQ address for P3 */
  166. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
  167. R_SEQ_ADD_S2A3);
  168. if (err)
  169. goto out;
  170. /* P3 LVL_WAKEUP should be on LEVEL */
  171. err = twl_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
  172. R_P3_SW_EVENTS);
  173. if (err)
  174. goto out;
  175. data |= LVL_WAKEUP;
  176. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data,
  177. R_P3_SW_EVENTS);
  178. out:
  179. if (err)
  180. pr_err("TWL4030 wakeup sequence for P3 config error\n");
  181. return err;
  182. }
  183. static int __init twl4030_config_wakeup12_sequence(u8 address)
  184. {
  185. int err = 0;
  186. u8 data;
  187. /* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
  188. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
  189. R_SEQ_ADD_S2A12);
  190. if (err)
  191. goto out;
  192. /* P1/P2 LVL_WAKEUP should be on LEVEL */
  193. err = twl_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
  194. R_P1_SW_EVENTS);
  195. if (err)
  196. goto out;
  197. data |= LVL_WAKEUP;
  198. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data,
  199. R_P1_SW_EVENTS);
  200. if (err)
  201. goto out;
  202. err = twl_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
  203. R_P2_SW_EVENTS);
  204. if (err)
  205. goto out;
  206. data |= LVL_WAKEUP;
  207. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data,
  208. R_P2_SW_EVENTS);
  209. if (err)
  210. goto out;
  211. if (machine_is_omap_3430sdp() || machine_is_omap_ldp()) {
  212. /* Disabling AC charger effect on sleep-active transitions */
  213. err = twl_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &data,
  214. R_CFG_P1_TRANSITION);
  215. if (err)
  216. goto out;
  217. data &= ~(1<<1);
  218. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, data ,
  219. R_CFG_P1_TRANSITION);
  220. if (err)
  221. goto out;
  222. }
  223. out:
  224. if (err)
  225. pr_err("TWL4030 wakeup sequence for P1 and P2" \
  226. "config error\n");
  227. return err;
  228. }
  229. static int __init twl4030_config_sleep_sequence(u8 address)
  230. {
  231. int err;
  232. /* Set ACTIVE to SLEEP SEQ address in T2 memory*/
  233. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
  234. R_SEQ_ADD_A2S);
  235. if (err)
  236. pr_err("TWL4030 sleep sequence config error\n");
  237. return err;
  238. }
  239. static int __init twl4030_config_warmreset_sequence(u8 address)
  240. {
  241. int err;
  242. u8 rd_data;
  243. /* Set WARM RESET SEQ address for P1 */
  244. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
  245. R_SEQ_ADD_WARM);
  246. if (err)
  247. goto out;
  248. /* P1/P2/P3 enable WARMRESET */
  249. err = twl_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
  250. R_P1_SW_EVENTS);
  251. if (err)
  252. goto out;
  253. rd_data |= ENABLE_WARMRESET;
  254. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
  255. R_P1_SW_EVENTS);
  256. if (err)
  257. goto out;
  258. err = twl_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
  259. R_P2_SW_EVENTS);
  260. if (err)
  261. goto out;
  262. rd_data |= ENABLE_WARMRESET;
  263. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
  264. R_P2_SW_EVENTS);
  265. if (err)
  266. goto out;
  267. err = twl_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &rd_data,
  268. R_P3_SW_EVENTS);
  269. if (err)
  270. goto out;
  271. rd_data |= ENABLE_WARMRESET;
  272. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, rd_data,
  273. R_P3_SW_EVENTS);
  274. out:
  275. if (err)
  276. pr_err("TWL4030 warmreset seq config error\n");
  277. return err;
  278. }
  279. static int __init twl4030_configure_resource(struct twl4030_resconfig *rconfig)
  280. {
  281. int rconfig_addr;
  282. int err;
  283. u8 type;
  284. u8 grp;
  285. u8 remap;
  286. if (rconfig->resource > TOTAL_RESOURCES) {
  287. pr_err("TWL4030 Resource %d does not exist\n",
  288. rconfig->resource);
  289. return -EINVAL;
  290. }
  291. rconfig_addr = res_config_addrs[rconfig->resource];
  292. /* Set resource group */
  293. err = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &grp,
  294. rconfig_addr + DEV_GRP_OFFSET);
  295. if (err) {
  296. pr_err("TWL4030 Resource %d group could not be read\n",
  297. rconfig->resource);
  298. return err;
  299. }
  300. if (rconfig->devgroup != TWL4030_RESCONFIG_UNDEF) {
  301. grp &= ~DEV_GRP_MASK;
  302. grp |= rconfig->devgroup << DEV_GRP_SHIFT;
  303. err = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
  304. grp, rconfig_addr + DEV_GRP_OFFSET);
  305. if (err < 0) {
  306. pr_err("TWL4030 failed to program devgroup\n");
  307. return err;
  308. }
  309. }
  310. /* Set resource types */
  311. err = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &type,
  312. rconfig_addr + TYPE_OFFSET);
  313. if (err < 0) {
  314. pr_err("TWL4030 Resource %d type could not be read\n",
  315. rconfig->resource);
  316. return err;
  317. }
  318. if (rconfig->type != TWL4030_RESCONFIG_UNDEF) {
  319. type &= ~TYPE_MASK;
  320. type |= rconfig->type << TYPE_SHIFT;
  321. }
  322. if (rconfig->type2 != TWL4030_RESCONFIG_UNDEF) {
  323. type &= ~TYPE2_MASK;
  324. type |= rconfig->type2 << TYPE2_SHIFT;
  325. }
  326. err = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
  327. type, rconfig_addr + TYPE_OFFSET);
  328. if (err < 0) {
  329. pr_err("TWL4030 failed to program resource type\n");
  330. return err;
  331. }
  332. /* Set remap states */
  333. err = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &remap,
  334. rconfig_addr + REMAP_OFFSET);
  335. if (err < 0) {
  336. pr_err("TWL4030 Resource %d remap could not be read\n",
  337. rconfig->resource);
  338. return err;
  339. }
  340. if (rconfig->remap_off != TWL4030_RESCONFIG_UNDEF) {
  341. remap &= ~OFF_STATE_MASK;
  342. remap |= rconfig->remap_off << OFF_STATE_SHIFT;
  343. }
  344. if (rconfig->remap_sleep != TWL4030_RESCONFIG_UNDEF) {
  345. remap &= ~SLEEP_STATE_MASK;
  346. remap |= rconfig->remap_sleep << SLEEP_STATE_SHIFT;
  347. }
  348. err = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
  349. remap,
  350. rconfig_addr + REMAP_OFFSET);
  351. if (err < 0) {
  352. pr_err("TWL4030 failed to program remap\n");
  353. return err;
  354. }
  355. return 0;
  356. }
  357. static int __init load_twl4030_script(struct twl4030_script *tscript,
  358. u8 address)
  359. {
  360. int err;
  361. static int order;
  362. /* Make sure the script isn't going beyond last valid address (0x3f) */
  363. if ((address + tscript->size) > END_OF_SCRIPT) {
  364. pr_err("TWL4030 scripts too big error\n");
  365. return -EINVAL;
  366. }
  367. err = twl4030_write_script(address, tscript->script, tscript->size);
  368. if (err)
  369. goto out;
  370. if (tscript->flags & TWL4030_WRST_SCRIPT) {
  371. err = twl4030_config_warmreset_sequence(address);
  372. if (err)
  373. goto out;
  374. }
  375. if (tscript->flags & TWL4030_WAKEUP12_SCRIPT) {
  376. err = twl4030_config_wakeup12_sequence(address);
  377. if (err)
  378. goto out;
  379. order = 1;
  380. }
  381. if (tscript->flags & TWL4030_WAKEUP3_SCRIPT) {
  382. err = twl4030_config_wakeup3_sequence(address);
  383. if (err)
  384. goto out;
  385. }
  386. if (tscript->flags & TWL4030_SLEEP_SCRIPT) {
  387. if (!order)
  388. pr_warning("TWL4030: Bad order of scripts (sleep "\
  389. "script before wakeup) Leads to boot"\
  390. "failure on some boards\n");
  391. err = twl4030_config_sleep_sequence(address);
  392. }
  393. out:
  394. return err;
  395. }
  396. int twl4030_remove_script(u8 flags)
  397. {
  398. int err = 0;
  399. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER,
  400. TWL4030_PM_MASTER_KEY_CFG1,
  401. TWL4030_PM_MASTER_PROTECT_KEY);
  402. if (err) {
  403. pr_err("twl4030: unable to unlock PROTECT_KEY\n");
  404. return err;
  405. }
  406. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER,
  407. TWL4030_PM_MASTER_KEY_CFG2,
  408. TWL4030_PM_MASTER_PROTECT_KEY);
  409. if (err) {
  410. pr_err("twl4030: unable to unlock PROTECT_KEY\n");
  411. return err;
  412. }
  413. if (flags & TWL4030_WRST_SCRIPT) {
  414. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, END_OF_SCRIPT,
  415. R_SEQ_ADD_WARM);
  416. if (err)
  417. return err;
  418. }
  419. if (flags & TWL4030_WAKEUP12_SCRIPT) {
  420. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, END_OF_SCRIPT,
  421. R_SEQ_ADD_S2A12);
  422. if (err)
  423. return err;
  424. }
  425. if (flags & TWL4030_WAKEUP3_SCRIPT) {
  426. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, END_OF_SCRIPT,
  427. R_SEQ_ADD_S2A3);
  428. if (err)
  429. return err;
  430. }
  431. if (flags & TWL4030_SLEEP_SCRIPT) {
  432. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, END_OF_SCRIPT,
  433. R_SEQ_ADD_A2S);
  434. if (err)
  435. return err;
  436. }
  437. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0,
  438. TWL4030_PM_MASTER_PROTECT_KEY);
  439. if (err)
  440. pr_err("TWL4030 Unable to relock registers\n");
  441. return err;
  442. }
  443. void __init twl4030_power_init(struct twl4030_power_data *twl4030_scripts)
  444. {
  445. int err = 0;
  446. int i;
  447. struct twl4030_resconfig *resconfig;
  448. u8 address = twl4030_start_script_address;
  449. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER,
  450. TWL4030_PM_MASTER_KEY_CFG1,
  451. TWL4030_PM_MASTER_PROTECT_KEY);
  452. if (err)
  453. goto unlock;
  454. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER,
  455. TWL4030_PM_MASTER_KEY_CFG2,
  456. TWL4030_PM_MASTER_PROTECT_KEY);
  457. if (err)
  458. goto unlock;
  459. for (i = 0; i < twl4030_scripts->num; i++) {
  460. err = load_twl4030_script(twl4030_scripts->scripts[i], address);
  461. if (err)
  462. goto load;
  463. address += twl4030_scripts->scripts[i]->size;
  464. }
  465. resconfig = twl4030_scripts->resource_config;
  466. if (resconfig) {
  467. while (resconfig->resource) {
  468. err = twl4030_configure_resource(resconfig);
  469. if (err)
  470. goto resource;
  471. resconfig++;
  472. }
  473. }
  474. err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0,
  475. TWL4030_PM_MASTER_PROTECT_KEY);
  476. if (err)
  477. pr_err("TWL4030 Unable to relock registers\n");
  478. return;
  479. unlock:
  480. if (err)
  481. pr_err("TWL4030 Unable to unlock registers\n");
  482. return;
  483. load:
  484. if (err)
  485. pr_err("TWL4030 failed to load scripts\n");
  486. return;
  487. resource:
  488. if (err)
  489. pr_err("TWL4030 failed to configure resource\n");
  490. return;
  491. }