t7l66xb.c 11 KB

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  1. /*
  2. *
  3. * Toshiba T7L66XB core mfd support
  4. *
  5. * Copyright (c) 2005, 2007, 2008 Ian Molton
  6. * Copyright (c) 2008 Dmitry Baryshkov
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * T7L66 features:
  13. *
  14. * Supported in this driver:
  15. * SD/MMC
  16. * SM/NAND flash controller
  17. *
  18. * As yet not supported
  19. * GPIO interface (on NAND pins)
  20. * Serial interface
  21. * TFT 'interface converter'
  22. * PCMCIA interface logic
  23. */
  24. #include <linux/kernel.h>
  25. #include <linux/module.h>
  26. #include <linux/err.h>
  27. #include <linux/io.h>
  28. #include <linux/slab.h>
  29. #include <linux/irq.h>
  30. #include <linux/clk.h>
  31. #include <linux/platform_device.h>
  32. #include <linux/mfd/core.h>
  33. #include <linux/mfd/tmio.h>
  34. #include <linux/mfd/t7l66xb.h>
  35. enum {
  36. T7L66XB_CELL_NAND,
  37. T7L66XB_CELL_MMC,
  38. };
  39. static const struct resource t7l66xb_mmc_resources[] = {
  40. {
  41. .start = 0x800,
  42. .end = 0x9ff,
  43. .flags = IORESOURCE_MEM,
  44. },
  45. {
  46. .start = IRQ_T7L66XB_MMC,
  47. .end = IRQ_T7L66XB_MMC,
  48. .flags = IORESOURCE_IRQ,
  49. },
  50. };
  51. #define SCR_REVID 0x08 /* b Revision ID */
  52. #define SCR_IMR 0x42 /* b Interrupt Mask */
  53. #define SCR_DEV_CTL 0xe0 /* b Device control */
  54. #define SCR_ISR 0xe1 /* b Interrupt Status */
  55. #define SCR_GPO_OC 0xf0 /* b GPO output control */
  56. #define SCR_GPO_OS 0xf1 /* b GPO output enable */
  57. #define SCR_GPI_S 0xf2 /* w GPI status */
  58. #define SCR_APDC 0xf8 /* b Active pullup down ctrl */
  59. #define SCR_DEV_CTL_USB BIT(0) /* USB enable */
  60. #define SCR_DEV_CTL_MMC BIT(1) /* MMC enable */
  61. /*--------------------------------------------------------------------------*/
  62. struct t7l66xb {
  63. void __iomem *scr;
  64. /* Lock to protect registers requiring read/modify/write ops. */
  65. spinlock_t lock;
  66. struct resource rscr;
  67. struct clk *clk48m;
  68. struct clk *clk32k;
  69. int irq;
  70. int irq_base;
  71. };
  72. /*--------------------------------------------------------------------------*/
  73. static int t7l66xb_mmc_enable(struct platform_device *mmc)
  74. {
  75. struct platform_device *dev = to_platform_device(mmc->dev.parent);
  76. struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
  77. unsigned long flags;
  78. u8 dev_ctl;
  79. clk_enable(t7l66xb->clk32k);
  80. spin_lock_irqsave(&t7l66xb->lock, flags);
  81. dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
  82. dev_ctl |= SCR_DEV_CTL_MMC;
  83. tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);
  84. spin_unlock_irqrestore(&t7l66xb->lock, flags);
  85. tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,
  86. t7l66xb_mmc_resources[0].start & 0xfffe);
  87. return 0;
  88. }
  89. static int t7l66xb_mmc_disable(struct platform_device *mmc)
  90. {
  91. struct platform_device *dev = to_platform_device(mmc->dev.parent);
  92. struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
  93. unsigned long flags;
  94. u8 dev_ctl;
  95. spin_lock_irqsave(&t7l66xb->lock, flags);
  96. dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
  97. dev_ctl &= ~SCR_DEV_CTL_MMC;
  98. tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);
  99. spin_unlock_irqrestore(&t7l66xb->lock, flags);
  100. clk_disable(t7l66xb->clk32k);
  101. return 0;
  102. }
  103. static void t7l66xb_mmc_pwr(struct platform_device *mmc, int state)
  104. {
  105. struct platform_device *dev = to_platform_device(mmc->dev.parent);
  106. struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
  107. tmio_core_mmc_pwr(t7l66xb->scr + 0x200, 0, state);
  108. }
  109. static void t7l66xb_mmc_clk_div(struct platform_device *mmc, int state)
  110. {
  111. struct platform_device *dev = to_platform_device(mmc->dev.parent);
  112. struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
  113. tmio_core_mmc_clk_div(t7l66xb->scr + 0x200, 0, state);
  114. }
  115. /*--------------------------------------------------------------------------*/
  116. static struct tmio_mmc_data t7166xb_mmc_data = {
  117. .hclk = 24000000,
  118. .set_pwr = t7l66xb_mmc_pwr,
  119. .set_clk_div = t7l66xb_mmc_clk_div,
  120. };
  121. static const struct resource t7l66xb_nand_resources[] = {
  122. {
  123. .start = 0xc00,
  124. .end = 0xc07,
  125. .flags = IORESOURCE_MEM,
  126. },
  127. {
  128. .start = 0x0100,
  129. .end = 0x01ff,
  130. .flags = IORESOURCE_MEM,
  131. },
  132. {
  133. .start = IRQ_T7L66XB_NAND,
  134. .end = IRQ_T7L66XB_NAND,
  135. .flags = IORESOURCE_IRQ,
  136. },
  137. };
  138. static struct mfd_cell t7l66xb_cells[] = {
  139. [T7L66XB_CELL_MMC] = {
  140. .name = "tmio-mmc",
  141. .enable = t7l66xb_mmc_enable,
  142. .disable = t7l66xb_mmc_disable,
  143. .platform_data = &t7166xb_mmc_data,
  144. .pdata_size = sizeof(t7166xb_mmc_data),
  145. .num_resources = ARRAY_SIZE(t7l66xb_mmc_resources),
  146. .resources = t7l66xb_mmc_resources,
  147. },
  148. [T7L66XB_CELL_NAND] = {
  149. .name = "tmio-nand",
  150. .num_resources = ARRAY_SIZE(t7l66xb_nand_resources),
  151. .resources = t7l66xb_nand_resources,
  152. },
  153. };
  154. /*--------------------------------------------------------------------------*/
  155. /* Handle the T7L66XB interrupt mux */
  156. static void t7l66xb_irq(unsigned int irq, struct irq_desc *desc)
  157. {
  158. struct t7l66xb *t7l66xb = irq_get_handler_data(irq);
  159. unsigned int isr;
  160. unsigned int i, irq_base;
  161. irq_base = t7l66xb->irq_base;
  162. while ((isr = tmio_ioread8(t7l66xb->scr + SCR_ISR) &
  163. ~tmio_ioread8(t7l66xb->scr + SCR_IMR)))
  164. for (i = 0; i < T7L66XB_NR_IRQS; i++)
  165. if (isr & (1 << i))
  166. generic_handle_irq(irq_base + i);
  167. }
  168. static void t7l66xb_irq_mask(struct irq_data *data)
  169. {
  170. struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data);
  171. unsigned long flags;
  172. u8 imr;
  173. spin_lock_irqsave(&t7l66xb->lock, flags);
  174. imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
  175. imr |= 1 << (data->irq - t7l66xb->irq_base);
  176. tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
  177. spin_unlock_irqrestore(&t7l66xb->lock, flags);
  178. }
  179. static void t7l66xb_irq_unmask(struct irq_data *data)
  180. {
  181. struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data);
  182. unsigned long flags;
  183. u8 imr;
  184. spin_lock_irqsave(&t7l66xb->lock, flags);
  185. imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
  186. imr &= ~(1 << (data->irq - t7l66xb->irq_base));
  187. tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
  188. spin_unlock_irqrestore(&t7l66xb->lock, flags);
  189. }
  190. static struct irq_chip t7l66xb_chip = {
  191. .name = "t7l66xb",
  192. .irq_ack = t7l66xb_irq_mask,
  193. .irq_mask = t7l66xb_irq_mask,
  194. .irq_unmask = t7l66xb_irq_unmask,
  195. };
  196. /*--------------------------------------------------------------------------*/
  197. /* Install the IRQ handler */
  198. static void t7l66xb_attach_irq(struct platform_device *dev)
  199. {
  200. struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
  201. unsigned int irq, irq_base;
  202. irq_base = t7l66xb->irq_base;
  203. for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) {
  204. irq_set_chip_and_handler(irq, &t7l66xb_chip, handle_level_irq);
  205. irq_set_chip_data(irq, t7l66xb);
  206. #ifdef CONFIG_ARM
  207. set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
  208. #endif
  209. }
  210. irq_set_irq_type(t7l66xb->irq, IRQ_TYPE_EDGE_FALLING);
  211. irq_set_handler_data(t7l66xb->irq, t7l66xb);
  212. irq_set_chained_handler(t7l66xb->irq, t7l66xb_irq);
  213. }
  214. static void t7l66xb_detach_irq(struct platform_device *dev)
  215. {
  216. struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
  217. unsigned int irq, irq_base;
  218. irq_base = t7l66xb->irq_base;
  219. irq_set_chained_handler(t7l66xb->irq, NULL);
  220. irq_set_handler_data(t7l66xb->irq, NULL);
  221. for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) {
  222. #ifdef CONFIG_ARM
  223. set_irq_flags(irq, 0);
  224. #endif
  225. irq_set_chip(irq, NULL);
  226. irq_set_chip_data(irq, NULL);
  227. }
  228. }
  229. /*--------------------------------------------------------------------------*/
  230. #ifdef CONFIG_PM
  231. static int t7l66xb_suspend(struct platform_device *dev, pm_message_t state)
  232. {
  233. struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
  234. struct t7l66xb_platform_data *pdata = dev->dev.platform_data;
  235. if (pdata && pdata->suspend)
  236. pdata->suspend(dev);
  237. clk_disable(t7l66xb->clk48m);
  238. return 0;
  239. }
  240. static int t7l66xb_resume(struct platform_device *dev)
  241. {
  242. struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
  243. struct t7l66xb_platform_data *pdata = dev->dev.platform_data;
  244. clk_enable(t7l66xb->clk48m);
  245. if (pdata && pdata->resume)
  246. pdata->resume(dev);
  247. tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,
  248. t7l66xb_mmc_resources[0].start & 0xfffe);
  249. return 0;
  250. }
  251. #else
  252. #define t7l66xb_suspend NULL
  253. #define t7l66xb_resume NULL
  254. #endif
  255. /*--------------------------------------------------------------------------*/
  256. static int t7l66xb_probe(struct platform_device *dev)
  257. {
  258. struct t7l66xb_platform_data *pdata = dev->dev.platform_data;
  259. struct t7l66xb *t7l66xb;
  260. struct resource *iomem, *rscr;
  261. int ret;
  262. if (pdata == NULL)
  263. return -EINVAL;
  264. iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
  265. if (!iomem)
  266. return -EINVAL;
  267. t7l66xb = kzalloc(sizeof *t7l66xb, GFP_KERNEL);
  268. if (!t7l66xb)
  269. return -ENOMEM;
  270. spin_lock_init(&t7l66xb->lock);
  271. platform_set_drvdata(dev, t7l66xb);
  272. ret = platform_get_irq(dev, 0);
  273. if (ret >= 0)
  274. t7l66xb->irq = ret;
  275. else
  276. goto err_noirq;
  277. t7l66xb->irq_base = pdata->irq_base;
  278. t7l66xb->clk32k = clk_get(&dev->dev, "CLK_CK32K");
  279. if (IS_ERR(t7l66xb->clk32k)) {
  280. ret = PTR_ERR(t7l66xb->clk32k);
  281. goto err_clk32k_get;
  282. }
  283. t7l66xb->clk48m = clk_get(&dev->dev, "CLK_CK48M");
  284. if (IS_ERR(t7l66xb->clk48m)) {
  285. ret = PTR_ERR(t7l66xb->clk48m);
  286. goto err_clk48m_get;
  287. }
  288. rscr = &t7l66xb->rscr;
  289. rscr->name = "t7l66xb-core";
  290. rscr->start = iomem->start;
  291. rscr->end = iomem->start + 0xff;
  292. rscr->flags = IORESOURCE_MEM;
  293. ret = request_resource(iomem, rscr);
  294. if (ret)
  295. goto err_request_scr;
  296. t7l66xb->scr = ioremap(rscr->start, resource_size(rscr));
  297. if (!t7l66xb->scr) {
  298. ret = -ENOMEM;
  299. goto err_ioremap;
  300. }
  301. clk_enable(t7l66xb->clk48m);
  302. if (pdata && pdata->enable)
  303. pdata->enable(dev);
  304. /* Mask all interrupts */
  305. tmio_iowrite8(0xbf, t7l66xb->scr + SCR_IMR);
  306. printk(KERN_INFO "%s rev %d @ 0x%08lx, irq %d\n",
  307. dev->name, tmio_ioread8(t7l66xb->scr + SCR_REVID),
  308. (unsigned long)iomem->start, t7l66xb->irq);
  309. t7l66xb_attach_irq(dev);
  310. t7l66xb_cells[T7L66XB_CELL_NAND].platform_data = pdata->nand_data;
  311. t7l66xb_cells[T7L66XB_CELL_NAND].pdata_size = sizeof(*pdata->nand_data);
  312. ret = mfd_add_devices(&dev->dev, dev->id,
  313. t7l66xb_cells, ARRAY_SIZE(t7l66xb_cells),
  314. iomem, t7l66xb->irq_base);
  315. if (!ret)
  316. return 0;
  317. t7l66xb_detach_irq(dev);
  318. iounmap(t7l66xb->scr);
  319. err_ioremap:
  320. release_resource(&t7l66xb->rscr);
  321. err_request_scr:
  322. clk_put(t7l66xb->clk48m);
  323. err_clk48m_get:
  324. clk_put(t7l66xb->clk32k);
  325. err_clk32k_get:
  326. err_noirq:
  327. kfree(t7l66xb);
  328. return ret;
  329. }
  330. static int t7l66xb_remove(struct platform_device *dev)
  331. {
  332. struct t7l66xb_platform_data *pdata = dev->dev.platform_data;
  333. struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
  334. int ret;
  335. ret = pdata->disable(dev);
  336. clk_disable(t7l66xb->clk48m);
  337. clk_put(t7l66xb->clk48m);
  338. clk_disable(t7l66xb->clk32k);
  339. clk_put(t7l66xb->clk32k);
  340. t7l66xb_detach_irq(dev);
  341. iounmap(t7l66xb->scr);
  342. release_resource(&t7l66xb->rscr);
  343. mfd_remove_devices(&dev->dev);
  344. platform_set_drvdata(dev, NULL);
  345. kfree(t7l66xb);
  346. return ret;
  347. }
  348. static struct platform_driver t7l66xb_platform_driver = {
  349. .driver = {
  350. .name = "t7l66xb",
  351. .owner = THIS_MODULE,
  352. },
  353. .suspend = t7l66xb_suspend,
  354. .resume = t7l66xb_resume,
  355. .probe = t7l66xb_probe,
  356. .remove = t7l66xb_remove,
  357. };
  358. /*--------------------------------------------------------------------------*/
  359. static int __init t7l66xb_init(void)
  360. {
  361. int retval = 0;
  362. retval = platform_driver_register(&t7l66xb_platform_driver);
  363. return retval;
  364. }
  365. static void __exit t7l66xb_exit(void)
  366. {
  367. platform_driver_unregister(&t7l66xb_platform_driver);
  368. }
  369. module_init(t7l66xb_init);
  370. module_exit(t7l66xb_exit);
  371. MODULE_DESCRIPTION("Toshiba T7L66XB core driver");
  372. MODULE_LICENSE("GPL v2");
  373. MODULE_AUTHOR("Ian Molton");
  374. MODULE_ALIAS("platform:t7l66xb");