max8998-irq.c 6.1 KB

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  1. /*
  2. * Interrupt controller support for MAX8998
  3. *
  4. * Copyright (C) 2010 Samsung Electronics Co.Ltd
  5. * Author: Joonyoung Shim <jy0922.shim@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. *
  12. */
  13. #include <linux/device.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/irq.h>
  16. #include <linux/mfd/max8998-private.h>
  17. struct max8998_irq_data {
  18. int reg;
  19. int mask;
  20. };
  21. static struct max8998_irq_data max8998_irqs[] = {
  22. [MAX8998_IRQ_DCINF] = {
  23. .reg = 1,
  24. .mask = MAX8998_IRQ_DCINF_MASK,
  25. },
  26. [MAX8998_IRQ_DCINR] = {
  27. .reg = 1,
  28. .mask = MAX8998_IRQ_DCINR_MASK,
  29. },
  30. [MAX8998_IRQ_JIGF] = {
  31. .reg = 1,
  32. .mask = MAX8998_IRQ_JIGF_MASK,
  33. },
  34. [MAX8998_IRQ_JIGR] = {
  35. .reg = 1,
  36. .mask = MAX8998_IRQ_JIGR_MASK,
  37. },
  38. [MAX8998_IRQ_PWRONF] = {
  39. .reg = 1,
  40. .mask = MAX8998_IRQ_PWRONF_MASK,
  41. },
  42. [MAX8998_IRQ_PWRONR] = {
  43. .reg = 1,
  44. .mask = MAX8998_IRQ_PWRONR_MASK,
  45. },
  46. [MAX8998_IRQ_WTSREVNT] = {
  47. .reg = 2,
  48. .mask = MAX8998_IRQ_WTSREVNT_MASK,
  49. },
  50. [MAX8998_IRQ_SMPLEVNT] = {
  51. .reg = 2,
  52. .mask = MAX8998_IRQ_SMPLEVNT_MASK,
  53. },
  54. [MAX8998_IRQ_ALARM1] = {
  55. .reg = 2,
  56. .mask = MAX8998_IRQ_ALARM1_MASK,
  57. },
  58. [MAX8998_IRQ_ALARM0] = {
  59. .reg = 2,
  60. .mask = MAX8998_IRQ_ALARM0_MASK,
  61. },
  62. [MAX8998_IRQ_ONKEY1S] = {
  63. .reg = 3,
  64. .mask = MAX8998_IRQ_ONKEY1S_MASK,
  65. },
  66. [MAX8998_IRQ_TOPOFFR] = {
  67. .reg = 3,
  68. .mask = MAX8998_IRQ_TOPOFFR_MASK,
  69. },
  70. [MAX8998_IRQ_DCINOVPR] = {
  71. .reg = 3,
  72. .mask = MAX8998_IRQ_DCINOVPR_MASK,
  73. },
  74. [MAX8998_IRQ_CHGRSTF] = {
  75. .reg = 3,
  76. .mask = MAX8998_IRQ_CHGRSTF_MASK,
  77. },
  78. [MAX8998_IRQ_DONER] = {
  79. .reg = 3,
  80. .mask = MAX8998_IRQ_DONER_MASK,
  81. },
  82. [MAX8998_IRQ_CHGFAULT] = {
  83. .reg = 3,
  84. .mask = MAX8998_IRQ_CHGFAULT_MASK,
  85. },
  86. [MAX8998_IRQ_LOBAT1] = {
  87. .reg = 4,
  88. .mask = MAX8998_IRQ_LOBAT1_MASK,
  89. },
  90. [MAX8998_IRQ_LOBAT2] = {
  91. .reg = 4,
  92. .mask = MAX8998_IRQ_LOBAT2_MASK,
  93. },
  94. };
  95. static inline struct max8998_irq_data *
  96. irq_to_max8998_irq(struct max8998_dev *max8998, int irq)
  97. {
  98. return &max8998_irqs[irq - max8998->irq_base];
  99. }
  100. static void max8998_irq_lock(struct irq_data *data)
  101. {
  102. struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
  103. mutex_lock(&max8998->irqlock);
  104. }
  105. static void max8998_irq_sync_unlock(struct irq_data *data)
  106. {
  107. struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
  108. int i;
  109. for (i = 0; i < ARRAY_SIZE(max8998->irq_masks_cur); i++) {
  110. /*
  111. * If there's been a change in the mask write it back
  112. * to the hardware.
  113. */
  114. if (max8998->irq_masks_cur[i] != max8998->irq_masks_cache[i]) {
  115. max8998->irq_masks_cache[i] = max8998->irq_masks_cur[i];
  116. max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i,
  117. max8998->irq_masks_cur[i]);
  118. }
  119. }
  120. mutex_unlock(&max8998->irqlock);
  121. }
  122. static void max8998_irq_unmask(struct irq_data *data)
  123. {
  124. struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
  125. struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998,
  126. data->irq);
  127. max8998->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
  128. }
  129. static void max8998_irq_mask(struct irq_data *data)
  130. {
  131. struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
  132. struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998,
  133. data->irq);
  134. max8998->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
  135. }
  136. static struct irq_chip max8998_irq_chip = {
  137. .name = "max8998",
  138. .irq_bus_lock = max8998_irq_lock,
  139. .irq_bus_sync_unlock = max8998_irq_sync_unlock,
  140. .irq_mask = max8998_irq_mask,
  141. .irq_unmask = max8998_irq_unmask,
  142. };
  143. static irqreturn_t max8998_irq_thread(int irq, void *data)
  144. {
  145. struct max8998_dev *max8998 = data;
  146. u8 irq_reg[MAX8998_NUM_IRQ_REGS];
  147. int ret;
  148. int i;
  149. ret = max8998_bulk_read(max8998->i2c, MAX8998_REG_IRQ1,
  150. MAX8998_NUM_IRQ_REGS, irq_reg);
  151. if (ret < 0) {
  152. dev_err(max8998->dev, "Failed to read interrupt register: %d\n",
  153. ret);
  154. return IRQ_NONE;
  155. }
  156. /* Apply masking */
  157. for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++)
  158. irq_reg[i] &= ~max8998->irq_masks_cur[i];
  159. /* Report */
  160. for (i = 0; i < MAX8998_IRQ_NR; i++) {
  161. if (irq_reg[max8998_irqs[i].reg - 1] & max8998_irqs[i].mask)
  162. handle_nested_irq(max8998->irq_base + i);
  163. }
  164. return IRQ_HANDLED;
  165. }
  166. int max8998_irq_resume(struct max8998_dev *max8998)
  167. {
  168. if (max8998->irq && max8998->irq_base)
  169. max8998_irq_thread(max8998->irq_base, max8998);
  170. return 0;
  171. }
  172. int max8998_irq_init(struct max8998_dev *max8998)
  173. {
  174. int i;
  175. int cur_irq;
  176. int ret;
  177. if (!max8998->irq) {
  178. dev_warn(max8998->dev,
  179. "No interrupt specified, no interrupts\n");
  180. max8998->irq_base = 0;
  181. return 0;
  182. }
  183. if (!max8998->irq_base) {
  184. dev_err(max8998->dev,
  185. "No interrupt base specified, no interrupts\n");
  186. return 0;
  187. }
  188. mutex_init(&max8998->irqlock);
  189. /* Mask the individual interrupt sources */
  190. for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++) {
  191. max8998->irq_masks_cur[i] = 0xff;
  192. max8998->irq_masks_cache[i] = 0xff;
  193. max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i, 0xff);
  194. }
  195. max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM1, 0xff);
  196. max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM2, 0xff);
  197. /* register with genirq */
  198. for (i = 0; i < MAX8998_IRQ_NR; i++) {
  199. cur_irq = i + max8998->irq_base;
  200. irq_set_chip_data(cur_irq, max8998);
  201. irq_set_chip_and_handler(cur_irq, &max8998_irq_chip,
  202. handle_edge_irq);
  203. irq_set_nested_thread(cur_irq, 1);
  204. #ifdef CONFIG_ARM
  205. set_irq_flags(cur_irq, IRQF_VALID);
  206. #else
  207. irq_set_noprobe(cur_irq);
  208. #endif
  209. }
  210. ret = request_threaded_irq(max8998->irq, NULL, max8998_irq_thread,
  211. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  212. "max8998-irq", max8998);
  213. if (ret) {
  214. dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
  215. max8998->irq, ret);
  216. return ret;
  217. }
  218. if (!max8998->ono)
  219. return 0;
  220. ret = request_threaded_irq(max8998->ono, NULL, max8998_irq_thread,
  221. IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
  222. IRQF_ONESHOT, "max8998-ono", max8998);
  223. if (ret)
  224. dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
  225. max8998->ono, ret);
  226. return 0;
  227. }
  228. void max8998_irq_exit(struct max8998_dev *max8998)
  229. {
  230. if (max8998->ono)
  231. free_irq(max8998->ono, max8998);
  232. if (max8998->irq)
  233. free_irq(max8998->irq, max8998);
  234. }