ab8500-core.c 19 KB

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  1. /*
  2. * Copyright (C) ST-Ericsson SA 2010
  3. *
  4. * License Terms: GNU General Public License v2
  5. * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
  6. * Author: Rabin Vincent <rabin.vincent@stericsson.com>
  7. * Author: Mattias Wallin <mattias.wallin@stericsson.com>
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/slab.h>
  11. #include <linux/init.h>
  12. #include <linux/irq.h>
  13. #include <linux/delay.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/module.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/mfd/core.h>
  18. #include <linux/mfd/abx500.h>
  19. #include <linux/mfd/ab8500.h>
  20. #include <linux/regulator/ab8500.h>
  21. /*
  22. * Interrupt register offsets
  23. * Bank : 0x0E
  24. */
  25. #define AB8500_IT_SOURCE1_REG 0x00
  26. #define AB8500_IT_SOURCE2_REG 0x01
  27. #define AB8500_IT_SOURCE3_REG 0x02
  28. #define AB8500_IT_SOURCE4_REG 0x03
  29. #define AB8500_IT_SOURCE5_REG 0x04
  30. #define AB8500_IT_SOURCE6_REG 0x05
  31. #define AB8500_IT_SOURCE7_REG 0x06
  32. #define AB8500_IT_SOURCE8_REG 0x07
  33. #define AB8500_IT_SOURCE19_REG 0x12
  34. #define AB8500_IT_SOURCE20_REG 0x13
  35. #define AB8500_IT_SOURCE21_REG 0x14
  36. #define AB8500_IT_SOURCE22_REG 0x15
  37. #define AB8500_IT_SOURCE23_REG 0x16
  38. #define AB8500_IT_SOURCE24_REG 0x17
  39. /*
  40. * latch registers
  41. */
  42. #define AB8500_IT_LATCH1_REG 0x20
  43. #define AB8500_IT_LATCH2_REG 0x21
  44. #define AB8500_IT_LATCH3_REG 0x22
  45. #define AB8500_IT_LATCH4_REG 0x23
  46. #define AB8500_IT_LATCH5_REG 0x24
  47. #define AB8500_IT_LATCH6_REG 0x25
  48. #define AB8500_IT_LATCH7_REG 0x26
  49. #define AB8500_IT_LATCH8_REG 0x27
  50. #define AB8500_IT_LATCH9_REG 0x28
  51. #define AB8500_IT_LATCH10_REG 0x29
  52. #define AB8500_IT_LATCH12_REG 0x2B
  53. #define AB8500_IT_LATCH19_REG 0x32
  54. #define AB8500_IT_LATCH20_REG 0x33
  55. #define AB8500_IT_LATCH21_REG 0x34
  56. #define AB8500_IT_LATCH22_REG 0x35
  57. #define AB8500_IT_LATCH23_REG 0x36
  58. #define AB8500_IT_LATCH24_REG 0x37
  59. /*
  60. * mask registers
  61. */
  62. #define AB8500_IT_MASK1_REG 0x40
  63. #define AB8500_IT_MASK2_REG 0x41
  64. #define AB8500_IT_MASK3_REG 0x42
  65. #define AB8500_IT_MASK4_REG 0x43
  66. #define AB8500_IT_MASK5_REG 0x44
  67. #define AB8500_IT_MASK6_REG 0x45
  68. #define AB8500_IT_MASK7_REG 0x46
  69. #define AB8500_IT_MASK8_REG 0x47
  70. #define AB8500_IT_MASK9_REG 0x48
  71. #define AB8500_IT_MASK10_REG 0x49
  72. #define AB8500_IT_MASK11_REG 0x4A
  73. #define AB8500_IT_MASK12_REG 0x4B
  74. #define AB8500_IT_MASK13_REG 0x4C
  75. #define AB8500_IT_MASK14_REG 0x4D
  76. #define AB8500_IT_MASK15_REG 0x4E
  77. #define AB8500_IT_MASK16_REG 0x4F
  78. #define AB8500_IT_MASK17_REG 0x50
  79. #define AB8500_IT_MASK18_REG 0x51
  80. #define AB8500_IT_MASK19_REG 0x52
  81. #define AB8500_IT_MASK20_REG 0x53
  82. #define AB8500_IT_MASK21_REG 0x54
  83. #define AB8500_IT_MASK22_REG 0x55
  84. #define AB8500_IT_MASK23_REG 0x56
  85. #define AB8500_IT_MASK24_REG 0x57
  86. #define AB8500_REV_REG 0x80
  87. #define AB8500_SWITCH_OFF_STATUS 0x00
  88. /*
  89. * Map interrupt numbers to the LATCH and MASK register offsets, Interrupt
  90. * numbers are indexed into this array with (num / 8).
  91. *
  92. * This is one off from the register names, i.e. AB8500_IT_MASK1_REG is at
  93. * offset 0.
  94. */
  95. static const int ab8500_irq_regoffset[AB8500_NUM_IRQ_REGS] = {
  96. 0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21,
  97. };
  98. static int ab8500_get_chip_id(struct device *dev)
  99. {
  100. struct ab8500 *ab8500;
  101. if (!dev)
  102. return -EINVAL;
  103. ab8500 = dev_get_drvdata(dev->parent);
  104. return ab8500 ? (int)ab8500->chip_id : -EINVAL;
  105. }
  106. static int set_register_interruptible(struct ab8500 *ab8500, u8 bank,
  107. u8 reg, u8 data)
  108. {
  109. int ret;
  110. /*
  111. * Put the u8 bank and u8 register together into a an u16.
  112. * The bank on higher 8 bits and register in lower 8 bits.
  113. * */
  114. u16 addr = ((u16)bank) << 8 | reg;
  115. dev_vdbg(ab8500->dev, "wr: addr %#x <= %#x\n", addr, data);
  116. ret = mutex_lock_interruptible(&ab8500->lock);
  117. if (ret)
  118. return ret;
  119. ret = ab8500->write(ab8500, addr, data);
  120. if (ret < 0)
  121. dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
  122. addr, ret);
  123. mutex_unlock(&ab8500->lock);
  124. return ret;
  125. }
  126. static int ab8500_set_register(struct device *dev, u8 bank,
  127. u8 reg, u8 value)
  128. {
  129. struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
  130. return set_register_interruptible(ab8500, bank, reg, value);
  131. }
  132. static int get_register_interruptible(struct ab8500 *ab8500, u8 bank,
  133. u8 reg, u8 *value)
  134. {
  135. int ret;
  136. /* put the u8 bank and u8 reg together into a an u16.
  137. * bank on higher 8 bits and reg in lower */
  138. u16 addr = ((u16)bank) << 8 | reg;
  139. ret = mutex_lock_interruptible(&ab8500->lock);
  140. if (ret)
  141. return ret;
  142. ret = ab8500->read(ab8500, addr);
  143. if (ret < 0)
  144. dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
  145. addr, ret);
  146. else
  147. *value = ret;
  148. mutex_unlock(&ab8500->lock);
  149. dev_vdbg(ab8500->dev, "rd: addr %#x => data %#x\n", addr, ret);
  150. return ret;
  151. }
  152. static int ab8500_get_register(struct device *dev, u8 bank,
  153. u8 reg, u8 *value)
  154. {
  155. struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
  156. return get_register_interruptible(ab8500, bank, reg, value);
  157. }
  158. static int mask_and_set_register_interruptible(struct ab8500 *ab8500, u8 bank,
  159. u8 reg, u8 bitmask, u8 bitvalues)
  160. {
  161. int ret;
  162. u8 data;
  163. /* put the u8 bank and u8 reg together into a an u16.
  164. * bank on higher 8 bits and reg in lower */
  165. u16 addr = ((u16)bank) << 8 | reg;
  166. ret = mutex_lock_interruptible(&ab8500->lock);
  167. if (ret)
  168. return ret;
  169. ret = ab8500->read(ab8500, addr);
  170. if (ret < 0) {
  171. dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
  172. addr, ret);
  173. goto out;
  174. }
  175. data = (u8)ret;
  176. data = (~bitmask & data) | (bitmask & bitvalues);
  177. ret = ab8500->write(ab8500, addr, data);
  178. if (ret < 0)
  179. dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
  180. addr, ret);
  181. dev_vdbg(ab8500->dev, "mask: addr %#x => data %#x\n", addr, data);
  182. out:
  183. mutex_unlock(&ab8500->lock);
  184. return ret;
  185. }
  186. static int ab8500_mask_and_set_register(struct device *dev,
  187. u8 bank, u8 reg, u8 bitmask, u8 bitvalues)
  188. {
  189. struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
  190. return mask_and_set_register_interruptible(ab8500, bank, reg,
  191. bitmask, bitvalues);
  192. }
  193. static struct abx500_ops ab8500_ops = {
  194. .get_chip_id = ab8500_get_chip_id,
  195. .get_register = ab8500_get_register,
  196. .set_register = ab8500_set_register,
  197. .get_register_page = NULL,
  198. .set_register_page = NULL,
  199. .mask_and_set_register = ab8500_mask_and_set_register,
  200. .event_registers_startup_state_get = NULL,
  201. .startup_irq_enabled = NULL,
  202. };
  203. static void ab8500_irq_lock(struct irq_data *data)
  204. {
  205. struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
  206. mutex_lock(&ab8500->irq_lock);
  207. }
  208. static void ab8500_irq_sync_unlock(struct irq_data *data)
  209. {
  210. struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
  211. int i;
  212. for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) {
  213. u8 old = ab8500->oldmask[i];
  214. u8 new = ab8500->mask[i];
  215. int reg;
  216. if (new == old)
  217. continue;
  218. /* Interrupt register 12 doesn't exist prior to version 2.0 */
  219. if (ab8500_irq_regoffset[i] == 11 &&
  220. ab8500->chip_id < AB8500_CUT2P0)
  221. continue;
  222. ab8500->oldmask[i] = new;
  223. reg = AB8500_IT_MASK1_REG + ab8500_irq_regoffset[i];
  224. set_register_interruptible(ab8500, AB8500_INTERRUPT, reg, new);
  225. }
  226. mutex_unlock(&ab8500->irq_lock);
  227. }
  228. static void ab8500_irq_mask(struct irq_data *data)
  229. {
  230. struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
  231. int offset = data->irq - ab8500->irq_base;
  232. int index = offset / 8;
  233. int mask = 1 << (offset % 8);
  234. ab8500->mask[index] |= mask;
  235. }
  236. static void ab8500_irq_unmask(struct irq_data *data)
  237. {
  238. struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
  239. int offset = data->irq - ab8500->irq_base;
  240. int index = offset / 8;
  241. int mask = 1 << (offset % 8);
  242. ab8500->mask[index] &= ~mask;
  243. }
  244. static struct irq_chip ab8500_irq_chip = {
  245. .name = "ab8500",
  246. .irq_bus_lock = ab8500_irq_lock,
  247. .irq_bus_sync_unlock = ab8500_irq_sync_unlock,
  248. .irq_mask = ab8500_irq_mask,
  249. .irq_unmask = ab8500_irq_unmask,
  250. };
  251. static irqreturn_t ab8500_irq(int irq, void *dev)
  252. {
  253. struct ab8500 *ab8500 = dev;
  254. int i;
  255. dev_vdbg(ab8500->dev, "interrupt\n");
  256. for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) {
  257. int regoffset = ab8500_irq_regoffset[i];
  258. int status;
  259. u8 value;
  260. /* Interrupt register 12 doesn't exist prior to version 2.0 */
  261. if (regoffset == 11 && ab8500->chip_id < AB8500_CUT2P0)
  262. continue;
  263. status = get_register_interruptible(ab8500, AB8500_INTERRUPT,
  264. AB8500_IT_LATCH1_REG + regoffset, &value);
  265. if (status < 0 || value == 0)
  266. continue;
  267. do {
  268. int bit = __ffs(value);
  269. int line = i * 8 + bit;
  270. handle_nested_irq(ab8500->irq_base + line);
  271. value &= ~(1 << bit);
  272. } while (value);
  273. }
  274. return IRQ_HANDLED;
  275. }
  276. static int ab8500_irq_init(struct ab8500 *ab8500)
  277. {
  278. int base = ab8500->irq_base;
  279. int irq;
  280. for (irq = base; irq < base + AB8500_NR_IRQS; irq++) {
  281. irq_set_chip_data(irq, ab8500);
  282. irq_set_chip_and_handler(irq, &ab8500_irq_chip,
  283. handle_simple_irq);
  284. irq_set_nested_thread(irq, 1);
  285. #ifdef CONFIG_ARM
  286. set_irq_flags(irq, IRQF_VALID);
  287. #else
  288. irq_set_noprobe(irq);
  289. #endif
  290. }
  291. return 0;
  292. }
  293. static void ab8500_irq_remove(struct ab8500 *ab8500)
  294. {
  295. int base = ab8500->irq_base;
  296. int irq;
  297. for (irq = base; irq < base + AB8500_NR_IRQS; irq++) {
  298. #ifdef CONFIG_ARM
  299. set_irq_flags(irq, 0);
  300. #endif
  301. irq_set_chip_and_handler(irq, NULL, NULL);
  302. irq_set_chip_data(irq, NULL);
  303. }
  304. }
  305. static struct resource ab8500_gpio_resources[] = {
  306. {
  307. .name = "GPIO_INT6",
  308. .start = AB8500_INT_GPIO6R,
  309. .end = AB8500_INT_GPIO41F,
  310. .flags = IORESOURCE_IRQ,
  311. }
  312. };
  313. static struct resource ab8500_gpadc_resources[] = {
  314. {
  315. .name = "HW_CONV_END",
  316. .start = AB8500_INT_GP_HW_ADC_CONV_END,
  317. .end = AB8500_INT_GP_HW_ADC_CONV_END,
  318. .flags = IORESOURCE_IRQ,
  319. },
  320. {
  321. .name = "SW_CONV_END",
  322. .start = AB8500_INT_GP_SW_ADC_CONV_END,
  323. .end = AB8500_INT_GP_SW_ADC_CONV_END,
  324. .flags = IORESOURCE_IRQ,
  325. },
  326. };
  327. static struct resource ab8500_rtc_resources[] = {
  328. {
  329. .name = "60S",
  330. .start = AB8500_INT_RTC_60S,
  331. .end = AB8500_INT_RTC_60S,
  332. .flags = IORESOURCE_IRQ,
  333. },
  334. {
  335. .name = "ALARM",
  336. .start = AB8500_INT_RTC_ALARM,
  337. .end = AB8500_INT_RTC_ALARM,
  338. .flags = IORESOURCE_IRQ,
  339. },
  340. };
  341. static struct resource ab8500_poweronkey_db_resources[] = {
  342. {
  343. .name = "ONKEY_DBF",
  344. .start = AB8500_INT_PON_KEY1DB_F,
  345. .end = AB8500_INT_PON_KEY1DB_F,
  346. .flags = IORESOURCE_IRQ,
  347. },
  348. {
  349. .name = "ONKEY_DBR",
  350. .start = AB8500_INT_PON_KEY1DB_R,
  351. .end = AB8500_INT_PON_KEY1DB_R,
  352. .flags = IORESOURCE_IRQ,
  353. },
  354. };
  355. static struct resource ab8500_bm_resources[] = {
  356. {
  357. .name = "MAIN_EXT_CH_NOT_OK",
  358. .start = AB8500_INT_MAIN_EXT_CH_NOT_OK,
  359. .end = AB8500_INT_MAIN_EXT_CH_NOT_OK,
  360. .flags = IORESOURCE_IRQ,
  361. },
  362. {
  363. .name = "BATT_OVV",
  364. .start = AB8500_INT_BATT_OVV,
  365. .end = AB8500_INT_BATT_OVV,
  366. .flags = IORESOURCE_IRQ,
  367. },
  368. {
  369. .name = "MAIN_CH_UNPLUG_DET",
  370. .start = AB8500_INT_MAIN_CH_UNPLUG_DET,
  371. .end = AB8500_INT_MAIN_CH_UNPLUG_DET,
  372. .flags = IORESOURCE_IRQ,
  373. },
  374. {
  375. .name = "MAIN_CHARGE_PLUG_DET",
  376. .start = AB8500_INT_MAIN_CH_PLUG_DET,
  377. .end = AB8500_INT_MAIN_CH_PLUG_DET,
  378. .flags = IORESOURCE_IRQ,
  379. },
  380. {
  381. .name = "VBUS_DET_F",
  382. .start = AB8500_INT_VBUS_DET_F,
  383. .end = AB8500_INT_VBUS_DET_F,
  384. .flags = IORESOURCE_IRQ,
  385. },
  386. {
  387. .name = "VBUS_DET_R",
  388. .start = AB8500_INT_VBUS_DET_R,
  389. .end = AB8500_INT_VBUS_DET_R,
  390. .flags = IORESOURCE_IRQ,
  391. },
  392. {
  393. .name = "BAT_CTRL_INDB",
  394. .start = AB8500_INT_BAT_CTRL_INDB,
  395. .end = AB8500_INT_BAT_CTRL_INDB,
  396. .flags = IORESOURCE_IRQ,
  397. },
  398. {
  399. .name = "CH_WD_EXP",
  400. .start = AB8500_INT_CH_WD_EXP,
  401. .end = AB8500_INT_CH_WD_EXP,
  402. .flags = IORESOURCE_IRQ,
  403. },
  404. {
  405. .name = "VBUS_OVV",
  406. .start = AB8500_INT_VBUS_OVV,
  407. .end = AB8500_INT_VBUS_OVV,
  408. .flags = IORESOURCE_IRQ,
  409. },
  410. {
  411. .name = "NCONV_ACCU",
  412. .start = AB8500_INT_CCN_CONV_ACC,
  413. .end = AB8500_INT_CCN_CONV_ACC,
  414. .flags = IORESOURCE_IRQ,
  415. },
  416. {
  417. .name = "LOW_BAT_F",
  418. .start = AB8500_INT_LOW_BAT_F,
  419. .end = AB8500_INT_LOW_BAT_F,
  420. .flags = IORESOURCE_IRQ,
  421. },
  422. {
  423. .name = "LOW_BAT_R",
  424. .start = AB8500_INT_LOW_BAT_R,
  425. .end = AB8500_INT_LOW_BAT_R,
  426. .flags = IORESOURCE_IRQ,
  427. },
  428. {
  429. .name = "BTEMP_LOW",
  430. .start = AB8500_INT_BTEMP_LOW,
  431. .end = AB8500_INT_BTEMP_LOW,
  432. .flags = IORESOURCE_IRQ,
  433. },
  434. {
  435. .name = "BTEMP_HIGH",
  436. .start = AB8500_INT_BTEMP_HIGH,
  437. .end = AB8500_INT_BTEMP_HIGH,
  438. .flags = IORESOURCE_IRQ,
  439. },
  440. {
  441. .name = "USB_CHARGER_NOT_OKR",
  442. .start = AB8500_INT_USB_CHARGER_NOT_OK,
  443. .end = AB8500_INT_USB_CHARGER_NOT_OK,
  444. .flags = IORESOURCE_IRQ,
  445. },
  446. {
  447. .name = "USB_CHARGE_DET_DONE",
  448. .start = AB8500_INT_USB_CHG_DET_DONE,
  449. .end = AB8500_INT_USB_CHG_DET_DONE,
  450. .flags = IORESOURCE_IRQ,
  451. },
  452. {
  453. .name = "USB_CH_TH_PROT_R",
  454. .start = AB8500_INT_USB_CH_TH_PROT_R,
  455. .end = AB8500_INT_USB_CH_TH_PROT_R,
  456. .flags = IORESOURCE_IRQ,
  457. },
  458. {
  459. .name = "MAIN_CH_TH_PROT_R",
  460. .start = AB8500_INT_MAIN_CH_TH_PROT_R,
  461. .end = AB8500_INT_MAIN_CH_TH_PROT_R,
  462. .flags = IORESOURCE_IRQ,
  463. },
  464. {
  465. .name = "USB_CHARGER_NOT_OKF",
  466. .start = AB8500_INT_USB_CHARGER_NOT_OKF,
  467. .end = AB8500_INT_USB_CHARGER_NOT_OKF,
  468. .flags = IORESOURCE_IRQ,
  469. },
  470. };
  471. static struct resource ab8500_debug_resources[] = {
  472. {
  473. .name = "IRQ_FIRST",
  474. .start = AB8500_INT_MAIN_EXT_CH_NOT_OK,
  475. .end = AB8500_INT_MAIN_EXT_CH_NOT_OK,
  476. .flags = IORESOURCE_IRQ,
  477. },
  478. {
  479. .name = "IRQ_LAST",
  480. .start = AB8500_INT_USB_CHARGER_NOT_OKF,
  481. .end = AB8500_INT_USB_CHARGER_NOT_OKF,
  482. .flags = IORESOURCE_IRQ,
  483. },
  484. };
  485. static struct resource ab8500_usb_resources[] = {
  486. {
  487. .name = "ID_WAKEUP_R",
  488. .start = AB8500_INT_ID_WAKEUP_R,
  489. .end = AB8500_INT_ID_WAKEUP_R,
  490. .flags = IORESOURCE_IRQ,
  491. },
  492. {
  493. .name = "ID_WAKEUP_F",
  494. .start = AB8500_INT_ID_WAKEUP_F,
  495. .end = AB8500_INT_ID_WAKEUP_F,
  496. .flags = IORESOURCE_IRQ,
  497. },
  498. {
  499. .name = "VBUS_DET_F",
  500. .start = AB8500_INT_VBUS_DET_F,
  501. .end = AB8500_INT_VBUS_DET_F,
  502. .flags = IORESOURCE_IRQ,
  503. },
  504. {
  505. .name = "VBUS_DET_R",
  506. .start = AB8500_INT_VBUS_DET_R,
  507. .end = AB8500_INT_VBUS_DET_R,
  508. .flags = IORESOURCE_IRQ,
  509. },
  510. {
  511. .name = "USB_LINK_STATUS",
  512. .start = AB8500_INT_USB_LINK_STATUS,
  513. .end = AB8500_INT_USB_LINK_STATUS,
  514. .flags = IORESOURCE_IRQ,
  515. },
  516. };
  517. static struct resource ab8500_temp_resources[] = {
  518. {
  519. .name = "AB8500_TEMP_WARM",
  520. .start = AB8500_INT_TEMP_WARM,
  521. .end = AB8500_INT_TEMP_WARM,
  522. .flags = IORESOURCE_IRQ,
  523. },
  524. };
  525. static struct mfd_cell ab8500_devs[] = {
  526. #ifdef CONFIG_DEBUG_FS
  527. {
  528. .name = "ab8500-debug",
  529. .num_resources = ARRAY_SIZE(ab8500_debug_resources),
  530. .resources = ab8500_debug_resources,
  531. },
  532. #endif
  533. {
  534. .name = "ab8500-sysctrl",
  535. },
  536. {
  537. .name = "ab8500-regulator",
  538. },
  539. {
  540. .name = "ab8500-gpio",
  541. .num_resources = ARRAY_SIZE(ab8500_gpio_resources),
  542. .resources = ab8500_gpio_resources,
  543. },
  544. {
  545. .name = "ab8500-gpadc",
  546. .num_resources = ARRAY_SIZE(ab8500_gpadc_resources),
  547. .resources = ab8500_gpadc_resources,
  548. },
  549. {
  550. .name = "ab8500-rtc",
  551. .num_resources = ARRAY_SIZE(ab8500_rtc_resources),
  552. .resources = ab8500_rtc_resources,
  553. },
  554. {
  555. .name = "ab8500-bm",
  556. .num_resources = ARRAY_SIZE(ab8500_bm_resources),
  557. .resources = ab8500_bm_resources,
  558. },
  559. { .name = "ab8500-codec", },
  560. {
  561. .name = "ab8500-usb",
  562. .num_resources = ARRAY_SIZE(ab8500_usb_resources),
  563. .resources = ab8500_usb_resources,
  564. },
  565. {
  566. .name = "ab8500-poweron-key",
  567. .num_resources = ARRAY_SIZE(ab8500_poweronkey_db_resources),
  568. .resources = ab8500_poweronkey_db_resources,
  569. },
  570. {
  571. .name = "ab8500-pwm",
  572. .id = 1,
  573. },
  574. {
  575. .name = "ab8500-pwm",
  576. .id = 2,
  577. },
  578. {
  579. .name = "ab8500-pwm",
  580. .id = 3,
  581. },
  582. { .name = "ab8500-leds", },
  583. {
  584. .name = "ab8500-denc",
  585. },
  586. {
  587. .name = "ab8500-temp",
  588. .num_resources = ARRAY_SIZE(ab8500_temp_resources),
  589. .resources = ab8500_temp_resources,
  590. },
  591. };
  592. static ssize_t show_chip_id(struct device *dev,
  593. struct device_attribute *attr, char *buf)
  594. {
  595. struct ab8500 *ab8500;
  596. ab8500 = dev_get_drvdata(dev);
  597. return sprintf(buf, "%#x\n", ab8500 ? ab8500->chip_id : -EINVAL);
  598. }
  599. /*
  600. * ab8500 has switched off due to (SWITCH_OFF_STATUS):
  601. * 0x01 Swoff bit programming
  602. * 0x02 Thermal protection activation
  603. * 0x04 Vbat lower then BattOk falling threshold
  604. * 0x08 Watchdog expired
  605. * 0x10 Non presence of 32kHz clock
  606. * 0x20 Battery level lower than power on reset threshold
  607. * 0x40 Power on key 1 pressed longer than 10 seconds
  608. * 0x80 DB8500 thermal shutdown
  609. */
  610. static ssize_t show_switch_off_status(struct device *dev,
  611. struct device_attribute *attr, char *buf)
  612. {
  613. int ret;
  614. u8 value;
  615. struct ab8500 *ab8500;
  616. ab8500 = dev_get_drvdata(dev);
  617. ret = get_register_interruptible(ab8500, AB8500_RTC,
  618. AB8500_SWITCH_OFF_STATUS, &value);
  619. if (ret < 0)
  620. return ret;
  621. return sprintf(buf, "%#x\n", value);
  622. }
  623. static DEVICE_ATTR(chip_id, S_IRUGO, show_chip_id, NULL);
  624. static DEVICE_ATTR(switch_off_status, S_IRUGO, show_switch_off_status, NULL);
  625. static struct attribute *ab8500_sysfs_entries[] = {
  626. &dev_attr_chip_id.attr,
  627. &dev_attr_switch_off_status.attr,
  628. NULL,
  629. };
  630. static struct attribute_group ab8500_attr_group = {
  631. .attrs = ab8500_sysfs_entries,
  632. };
  633. int __devinit ab8500_init(struct ab8500 *ab8500)
  634. {
  635. struct ab8500_platform_data *plat = dev_get_platdata(ab8500->dev);
  636. int ret;
  637. int i;
  638. u8 value;
  639. if (plat)
  640. ab8500->irq_base = plat->irq_base;
  641. mutex_init(&ab8500->lock);
  642. mutex_init(&ab8500->irq_lock);
  643. ret = get_register_interruptible(ab8500, AB8500_MISC,
  644. AB8500_REV_REG, &value);
  645. if (ret < 0)
  646. return ret;
  647. switch (value) {
  648. case AB8500_CUTEARLY:
  649. case AB8500_CUT1P0:
  650. case AB8500_CUT1P1:
  651. case AB8500_CUT2P0:
  652. case AB8500_CUT3P0:
  653. dev_info(ab8500->dev, "detected chip, revision: %#x\n", value);
  654. break;
  655. default:
  656. dev_err(ab8500->dev, "unknown chip, revision: %#x\n", value);
  657. return -EINVAL;
  658. }
  659. ab8500->chip_id = value;
  660. /*
  661. * ab8500 has switched off due to (SWITCH_OFF_STATUS):
  662. * 0x01 Swoff bit programming
  663. * 0x02 Thermal protection activation
  664. * 0x04 Vbat lower then BattOk falling threshold
  665. * 0x08 Watchdog expired
  666. * 0x10 Non presence of 32kHz clock
  667. * 0x20 Battery level lower than power on reset threshold
  668. * 0x40 Power on key 1 pressed longer than 10 seconds
  669. * 0x80 DB8500 thermal shutdown
  670. */
  671. ret = get_register_interruptible(ab8500, AB8500_RTC,
  672. AB8500_SWITCH_OFF_STATUS, &value);
  673. if (ret < 0)
  674. return ret;
  675. dev_info(ab8500->dev, "switch off status: %#x", value);
  676. if (plat && plat->init)
  677. plat->init(ab8500);
  678. /* Clear and mask all interrupts */
  679. for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) {
  680. /* Interrupt register 12 doesn't exist prior to version 2.0 */
  681. if (ab8500_irq_regoffset[i] == 11 &&
  682. ab8500->chip_id < AB8500_CUT2P0)
  683. continue;
  684. get_register_interruptible(ab8500, AB8500_INTERRUPT,
  685. AB8500_IT_LATCH1_REG + ab8500_irq_regoffset[i],
  686. &value);
  687. set_register_interruptible(ab8500, AB8500_INTERRUPT,
  688. AB8500_IT_MASK1_REG + ab8500_irq_regoffset[i], 0xff);
  689. }
  690. ret = abx500_register_ops(ab8500->dev, &ab8500_ops);
  691. if (ret)
  692. return ret;
  693. for (i = 0; i < AB8500_NUM_IRQ_REGS; i++)
  694. ab8500->mask[i] = ab8500->oldmask[i] = 0xff;
  695. if (ab8500->irq_base) {
  696. ret = ab8500_irq_init(ab8500);
  697. if (ret)
  698. return ret;
  699. ret = request_threaded_irq(ab8500->irq, NULL, ab8500_irq,
  700. IRQF_ONESHOT | IRQF_NO_SUSPEND,
  701. "ab8500", ab8500);
  702. if (ret)
  703. goto out_removeirq;
  704. }
  705. ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs,
  706. ARRAY_SIZE(ab8500_devs), NULL,
  707. ab8500->irq_base);
  708. if (ret)
  709. goto out_freeirq;
  710. ret = sysfs_create_group(&ab8500->dev->kobj, &ab8500_attr_group);
  711. if (ret)
  712. dev_err(ab8500->dev, "error creating sysfs entries\n");
  713. return ret;
  714. out_freeirq:
  715. if (ab8500->irq_base) {
  716. free_irq(ab8500->irq, ab8500);
  717. out_removeirq:
  718. ab8500_irq_remove(ab8500);
  719. }
  720. return ret;
  721. }
  722. int __devexit ab8500_exit(struct ab8500 *ab8500)
  723. {
  724. sysfs_remove_group(&ab8500->dev->kobj, &ab8500_attr_group);
  725. mfd_remove_devices(ab8500->dev);
  726. if (ab8500->irq_base) {
  727. free_irq(ab8500->irq, ab8500);
  728. ab8500_irq_remove(ab8500);
  729. }
  730. return 0;
  731. }
  732. MODULE_AUTHOR("Mattias Wallin, Srinidhi Kasagar, Rabin Vincent");
  733. MODULE_DESCRIPTION("AB8500 MFD core");
  734. MODULE_LICENSE("GPL v2");