mb86a16.c 46 KB

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  1. /*
  2. Fujitsu MB86A16 DVB-S/DSS DC Receiver driver
  3. Copyright (C) Manu Abraham (abraham.manu@gmail.com)
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. */
  16. #include <linux/init.h>
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/moduleparam.h>
  20. #include <linux/slab.h>
  21. #include "dvb_frontend.h"
  22. #include "mb86a16.h"
  23. #include "mb86a16_priv.h"
  24. unsigned int verbose = 5;
  25. module_param(verbose, int, 0644);
  26. #define ABS(x) ((x) < 0 ? (-x) : (x))
  27. struct mb86a16_state {
  28. struct i2c_adapter *i2c_adap;
  29. const struct mb86a16_config *config;
  30. struct dvb_frontend frontend;
  31. /* tuning parameters */
  32. int frequency;
  33. int srate;
  34. /* Internal stuff */
  35. int master_clk;
  36. int deci;
  37. int csel;
  38. int rsel;
  39. };
  40. #define MB86A16_ERROR 0
  41. #define MB86A16_NOTICE 1
  42. #define MB86A16_INFO 2
  43. #define MB86A16_DEBUG 3
  44. #define dprintk(x, y, z, format, arg...) do { \
  45. if (z) { \
  46. if ((x > MB86A16_ERROR) && (x > y)) \
  47. printk(KERN_ERR "%s: " format "\n", __func__, ##arg); \
  48. else if ((x > MB86A16_NOTICE) && (x > y)) \
  49. printk(KERN_NOTICE "%s: " format "\n", __func__, ##arg); \
  50. else if ((x > MB86A16_INFO) && (x > y)) \
  51. printk(KERN_INFO "%s: " format "\n", __func__, ##arg); \
  52. else if ((x > MB86A16_DEBUG) && (x > y)) \
  53. printk(KERN_DEBUG "%s: " format "\n", __func__, ##arg); \
  54. } else { \
  55. if (x > y) \
  56. printk(format, ##arg); \
  57. } \
  58. } while (0)
  59. #define TRACE_IN dprintk(verbose, MB86A16_DEBUG, 1, "-->()")
  60. #define TRACE_OUT dprintk(verbose, MB86A16_DEBUG, 1, "()-->")
  61. static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val)
  62. {
  63. int ret;
  64. u8 buf[] = { reg, val };
  65. struct i2c_msg msg = {
  66. .addr = state->config->demod_address,
  67. .flags = 0,
  68. .buf = buf,
  69. .len = 2
  70. };
  71. dprintk(verbose, MB86A16_DEBUG, 1,
  72. "writing to [0x%02x],Reg[0x%02x],Data[0x%02x]",
  73. state->config->demod_address, buf[0], buf[1]);
  74. ret = i2c_transfer(state->i2c_adap, &msg, 1);
  75. return (ret != 1) ? -EREMOTEIO : 0;
  76. }
  77. static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val)
  78. {
  79. int ret;
  80. u8 b0[] = { reg };
  81. u8 b1[] = { 0 };
  82. struct i2c_msg msg[] = {
  83. {
  84. .addr = state->config->demod_address,
  85. .flags = 0,
  86. .buf = b0,
  87. .len = 1
  88. }, {
  89. .addr = state->config->demod_address,
  90. .flags = I2C_M_RD,
  91. .buf = b1,
  92. .len = 1
  93. }
  94. };
  95. ret = i2c_transfer(state->i2c_adap, msg, 2);
  96. if (ret != 2) {
  97. dprintk(verbose, MB86A16_ERROR, 1, "read error(reg=0x%02x, ret=0x%i)",
  98. reg, ret);
  99. return -EREMOTEIO;
  100. }
  101. *val = b1[0];
  102. return ret;
  103. }
  104. static int CNTM_set(struct mb86a16_state *state,
  105. unsigned char timint1,
  106. unsigned char timint2,
  107. unsigned char cnext)
  108. {
  109. unsigned char val;
  110. val = (timint1 << 4) | (timint2 << 2) | cnext;
  111. if (mb86a16_write(state, MB86A16_CNTMR, val) < 0)
  112. goto err;
  113. return 0;
  114. err:
  115. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  116. return -EREMOTEIO;
  117. }
  118. static int smrt_set(struct mb86a16_state *state, int rate)
  119. {
  120. int tmp ;
  121. int m ;
  122. unsigned char STOFS0, STOFS1;
  123. m = 1 << state->deci;
  124. tmp = (8192 * state->master_clk - 2 * m * rate * 8192 + state->master_clk / 2) / state->master_clk;
  125. STOFS0 = tmp & 0x0ff;
  126. STOFS1 = (tmp & 0xf00) >> 8;
  127. if (mb86a16_write(state, MB86A16_SRATE1, (state->deci << 2) |
  128. (state->csel << 1) |
  129. state->rsel) < 0)
  130. goto err;
  131. if (mb86a16_write(state, MB86A16_SRATE2, STOFS0) < 0)
  132. goto err;
  133. if (mb86a16_write(state, MB86A16_SRATE3, STOFS1) < 0)
  134. goto err;
  135. return 0;
  136. err:
  137. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  138. return -1;
  139. }
  140. static int srst(struct mb86a16_state *state)
  141. {
  142. if (mb86a16_write(state, MB86A16_RESET, 0x04) < 0)
  143. goto err;
  144. return 0;
  145. err:
  146. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  147. return -EREMOTEIO;
  148. }
  149. static int afcex_data_set(struct mb86a16_state *state,
  150. unsigned char AFCEX_L,
  151. unsigned char AFCEX_H)
  152. {
  153. if (mb86a16_write(state, MB86A16_AFCEXL, AFCEX_L) < 0)
  154. goto err;
  155. if (mb86a16_write(state, MB86A16_AFCEXH, AFCEX_H) < 0)
  156. goto err;
  157. return 0;
  158. err:
  159. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  160. return -1;
  161. }
  162. static int afcofs_data_set(struct mb86a16_state *state,
  163. unsigned char AFCEX_L,
  164. unsigned char AFCEX_H)
  165. {
  166. if (mb86a16_write(state, 0x58, AFCEX_L) < 0)
  167. goto err;
  168. if (mb86a16_write(state, 0x59, AFCEX_H) < 0)
  169. goto err;
  170. return 0;
  171. err:
  172. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  173. return -EREMOTEIO;
  174. }
  175. static int stlp_set(struct mb86a16_state *state,
  176. unsigned char STRAS,
  177. unsigned char STRBS)
  178. {
  179. if (mb86a16_write(state, MB86A16_STRFILTCOEF1, (STRBS << 3) | (STRAS)) < 0)
  180. goto err;
  181. return 0;
  182. err:
  183. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  184. return -EREMOTEIO;
  185. }
  186. static int Vi_set(struct mb86a16_state *state, unsigned char ETH, unsigned char VIA)
  187. {
  188. if (mb86a16_write(state, MB86A16_VISET2, 0x04) < 0)
  189. goto err;
  190. if (mb86a16_write(state, MB86A16_VISET3, 0xf5) < 0)
  191. goto err;
  192. return 0;
  193. err:
  194. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  195. return -EREMOTEIO;
  196. }
  197. static int initial_set(struct mb86a16_state *state)
  198. {
  199. if (stlp_set(state, 5, 7))
  200. goto err;
  201. udelay(100);
  202. if (afcex_data_set(state, 0, 0))
  203. goto err;
  204. udelay(100);
  205. if (afcofs_data_set(state, 0, 0))
  206. goto err;
  207. udelay(100);
  208. if (mb86a16_write(state, MB86A16_CRLFILTCOEF1, 0x16) < 0)
  209. goto err;
  210. if (mb86a16_write(state, 0x2f, 0x21) < 0)
  211. goto err;
  212. if (mb86a16_write(state, MB86A16_VIMAG, 0x38) < 0)
  213. goto err;
  214. if (mb86a16_write(state, MB86A16_FAGCS1, 0x00) < 0)
  215. goto err;
  216. if (mb86a16_write(state, MB86A16_FAGCS2, 0x1c) < 0)
  217. goto err;
  218. if (mb86a16_write(state, MB86A16_FAGCS3, 0x20) < 0)
  219. goto err;
  220. if (mb86a16_write(state, MB86A16_FAGCS4, 0x1e) < 0)
  221. goto err;
  222. if (mb86a16_write(state, MB86A16_FAGCS5, 0x23) < 0)
  223. goto err;
  224. if (mb86a16_write(state, 0x54, 0xff) < 0)
  225. goto err;
  226. if (mb86a16_write(state, MB86A16_TSOUT, 0x00) < 0)
  227. goto err;
  228. return 0;
  229. err:
  230. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  231. return -EREMOTEIO;
  232. }
  233. static int S01T_set(struct mb86a16_state *state,
  234. unsigned char s1t,
  235. unsigned s0t)
  236. {
  237. if (mb86a16_write(state, 0x33, (s1t << 3) | s0t) < 0)
  238. goto err;
  239. return 0;
  240. err:
  241. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  242. return -EREMOTEIO;
  243. }
  244. static int EN_set(struct mb86a16_state *state,
  245. int cren,
  246. int afcen)
  247. {
  248. unsigned char val;
  249. val = 0x7a | (cren << 7) | (afcen << 2);
  250. if (mb86a16_write(state, 0x49, val) < 0)
  251. goto err;
  252. return 0;
  253. err:
  254. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  255. return -EREMOTEIO;
  256. }
  257. static int AFCEXEN_set(struct mb86a16_state *state,
  258. int afcexen,
  259. int smrt)
  260. {
  261. unsigned char AFCA ;
  262. if (smrt > 18875)
  263. AFCA = 4;
  264. else if (smrt > 9375)
  265. AFCA = 3;
  266. else if (smrt > 2250)
  267. AFCA = 2;
  268. else
  269. AFCA = 1;
  270. if (mb86a16_write(state, 0x2a, 0x02 | (afcexen << 5) | (AFCA << 2)) < 0)
  271. goto err;
  272. return 0;
  273. err:
  274. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  275. return -EREMOTEIO;
  276. }
  277. static int DAGC_data_set(struct mb86a16_state *state,
  278. unsigned char DAGCA,
  279. unsigned char DAGCW)
  280. {
  281. if (mb86a16_write(state, 0x2d, (DAGCA << 3) | DAGCW) < 0)
  282. goto err;
  283. return 0;
  284. err:
  285. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  286. return -EREMOTEIO;
  287. }
  288. static void smrt_info_get(struct mb86a16_state *state, int rate)
  289. {
  290. if (rate >= 37501) {
  291. state->deci = 0; state->csel = 0; state->rsel = 0;
  292. } else if (rate >= 30001) {
  293. state->deci = 0; state->csel = 0; state->rsel = 1;
  294. } else if (rate >= 26251) {
  295. state->deci = 0; state->csel = 1; state->rsel = 0;
  296. } else if (rate >= 22501) {
  297. state->deci = 0; state->csel = 1; state->rsel = 1;
  298. } else if (rate >= 18751) {
  299. state->deci = 1; state->csel = 0; state->rsel = 0;
  300. } else if (rate >= 15001) {
  301. state->deci = 1; state->csel = 0; state->rsel = 1;
  302. } else if (rate >= 13126) {
  303. state->deci = 1; state->csel = 1; state->rsel = 0;
  304. } else if (rate >= 11251) {
  305. state->deci = 1; state->csel = 1; state->rsel = 1;
  306. } else if (rate >= 9376) {
  307. state->deci = 2; state->csel = 0; state->rsel = 0;
  308. } else if (rate >= 7501) {
  309. state->deci = 2; state->csel = 0; state->rsel = 1;
  310. } else if (rate >= 6563) {
  311. state->deci = 2; state->csel = 1; state->rsel = 0;
  312. } else if (rate >= 5626) {
  313. state->deci = 2; state->csel = 1; state->rsel = 1;
  314. } else if (rate >= 4688) {
  315. state->deci = 3; state->csel = 0; state->rsel = 0;
  316. } else if (rate >= 3751) {
  317. state->deci = 3; state->csel = 0; state->rsel = 1;
  318. } else if (rate >= 3282) {
  319. state->deci = 3; state->csel = 1; state->rsel = 0;
  320. } else if (rate >= 2814) {
  321. state->deci = 3; state->csel = 1; state->rsel = 1;
  322. } else if (rate >= 2344) {
  323. state->deci = 4; state->csel = 0; state->rsel = 0;
  324. } else if (rate >= 1876) {
  325. state->deci = 4; state->csel = 0; state->rsel = 1;
  326. } else if (rate >= 1641) {
  327. state->deci = 4; state->csel = 1; state->rsel = 0;
  328. } else if (rate >= 1407) {
  329. state->deci = 4; state->csel = 1; state->rsel = 1;
  330. } else if (rate >= 1172) {
  331. state->deci = 5; state->csel = 0; state->rsel = 0;
  332. } else if (rate >= 939) {
  333. state->deci = 5; state->csel = 0; state->rsel = 1;
  334. } else if (rate >= 821) {
  335. state->deci = 5; state->csel = 1; state->rsel = 0;
  336. } else {
  337. state->deci = 5; state->csel = 1; state->rsel = 1;
  338. }
  339. if (state->csel == 0)
  340. state->master_clk = 92000;
  341. else
  342. state->master_clk = 61333;
  343. }
  344. static int signal_det(struct mb86a16_state *state,
  345. int smrt,
  346. unsigned char *SIG)
  347. {
  348. int ret ;
  349. int smrtd ;
  350. int wait_sym ;
  351. u32 wait_t;
  352. unsigned char S[3] ;
  353. int i ;
  354. if (*SIG > 45) {
  355. if (CNTM_set(state, 2, 1, 2) < 0) {
  356. dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
  357. return -1;
  358. }
  359. wait_sym = 40000;
  360. } else {
  361. if (CNTM_set(state, 3, 1, 2) < 0) {
  362. dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
  363. return -1;
  364. }
  365. wait_sym = 80000;
  366. }
  367. for (i = 0; i < 3; i++) {
  368. if (i == 0)
  369. smrtd = smrt * 98 / 100;
  370. else if (i == 1)
  371. smrtd = smrt;
  372. else
  373. smrtd = smrt * 102 / 100;
  374. smrt_info_get(state, smrtd);
  375. smrt_set(state, smrtd);
  376. srst(state);
  377. wait_t = (wait_sym + 99 * smrtd / 100) / smrtd;
  378. if (wait_t == 0)
  379. wait_t = 1;
  380. msleep_interruptible(10);
  381. if (mb86a16_read(state, 0x37, &(S[i])) != 2) {
  382. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  383. return -EREMOTEIO;
  384. }
  385. }
  386. if ((S[1] > S[0] * 112 / 100) &&
  387. (S[1] > S[2] * 112 / 100)) {
  388. ret = 1;
  389. } else {
  390. ret = 0;
  391. }
  392. *SIG = S[1];
  393. if (CNTM_set(state, 0, 1, 2) < 0) {
  394. dprintk(verbose, MB86A16_ERROR, 1, "CNTM set Error");
  395. return -1;
  396. }
  397. return ret;
  398. }
  399. static int rf_val_set(struct mb86a16_state *state,
  400. int f,
  401. int smrt,
  402. unsigned char R)
  403. {
  404. unsigned char C, F, B;
  405. int M;
  406. unsigned char rf_val[5];
  407. int ack = -1;
  408. if (smrt > 37750)
  409. C = 1;
  410. else if (smrt > 18875)
  411. C = 2;
  412. else if (smrt > 5500)
  413. C = 3;
  414. else
  415. C = 4;
  416. if (smrt > 30500)
  417. F = 3;
  418. else if (smrt > 9375)
  419. F = 1;
  420. else if (smrt > 4625)
  421. F = 0;
  422. else
  423. F = 2;
  424. if (f < 1060)
  425. B = 0;
  426. else if (f < 1175)
  427. B = 1;
  428. else if (f < 1305)
  429. B = 2;
  430. else if (f < 1435)
  431. B = 3;
  432. else if (f < 1570)
  433. B = 4;
  434. else if (f < 1715)
  435. B = 5;
  436. else if (f < 1845)
  437. B = 6;
  438. else if (f < 1980)
  439. B = 7;
  440. else if (f < 2080)
  441. B = 8;
  442. else
  443. B = 9;
  444. M = f * (1 << R) / 2;
  445. rf_val[0] = 0x01 | (C << 3) | (F << 1);
  446. rf_val[1] = (R << 5) | ((M & 0x1f000) >> 12);
  447. rf_val[2] = (M & 0x00ff0) >> 4;
  448. rf_val[3] = ((M & 0x0000f) << 4) | B;
  449. /* Frequency Set */
  450. if (mb86a16_write(state, 0x21, rf_val[0]) < 0)
  451. ack = 0;
  452. if (mb86a16_write(state, 0x22, rf_val[1]) < 0)
  453. ack = 0;
  454. if (mb86a16_write(state, 0x23, rf_val[2]) < 0)
  455. ack = 0;
  456. if (mb86a16_write(state, 0x24, rf_val[3]) < 0)
  457. ack = 0;
  458. if (mb86a16_write(state, 0x25, 0x01) < 0)
  459. ack = 0;
  460. if (ack == 0) {
  461. dprintk(verbose, MB86A16_ERROR, 1, "RF Setup - I2C transfer error");
  462. return -EREMOTEIO;
  463. }
  464. return 0;
  465. }
  466. static int afcerr_chk(struct mb86a16_state *state)
  467. {
  468. unsigned char AFCM_L, AFCM_H ;
  469. int AFCM ;
  470. int afcm, afcerr ;
  471. if (mb86a16_read(state, 0x0e, &AFCM_L) != 2)
  472. goto err;
  473. if (mb86a16_read(state, 0x0f, &AFCM_H) != 2)
  474. goto err;
  475. AFCM = (AFCM_H << 8) + AFCM_L;
  476. if (AFCM > 2048)
  477. afcm = AFCM - 4096;
  478. else
  479. afcm = AFCM;
  480. afcerr = afcm * state->master_clk / 8192;
  481. return afcerr;
  482. err:
  483. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  484. return -EREMOTEIO;
  485. }
  486. static int dagcm_val_get(struct mb86a16_state *state)
  487. {
  488. int DAGCM;
  489. unsigned char DAGCM_H, DAGCM_L;
  490. if (mb86a16_read(state, 0x45, &DAGCM_L) != 2)
  491. goto err;
  492. if (mb86a16_read(state, 0x46, &DAGCM_H) != 2)
  493. goto err;
  494. DAGCM = (DAGCM_H << 8) + DAGCM_L;
  495. return DAGCM;
  496. err:
  497. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  498. return -EREMOTEIO;
  499. }
  500. static int mb86a16_read_status(struct dvb_frontend *fe, fe_status_t *status)
  501. {
  502. u8 stat, stat2;
  503. struct mb86a16_state *state = fe->demodulator_priv;
  504. *status = 0;
  505. if (mb86a16_read(state, MB86A16_SIG1, &stat) != 2)
  506. goto err;
  507. if (mb86a16_read(state, MB86A16_SIG2, &stat2) != 2)
  508. goto err;
  509. if ((stat > 25) && (stat2 > 25))
  510. *status |= FE_HAS_SIGNAL;
  511. if ((stat > 45) && (stat2 > 45))
  512. *status |= FE_HAS_CARRIER;
  513. if (mb86a16_read(state, MB86A16_STATUS, &stat) != 2)
  514. goto err;
  515. if (stat & 0x01)
  516. *status |= FE_HAS_SYNC;
  517. if (stat & 0x01)
  518. *status |= FE_HAS_VITERBI;
  519. if (mb86a16_read(state, MB86A16_FRAMESYNC, &stat) != 2)
  520. goto err;
  521. if ((stat & 0x0f) && (*status & FE_HAS_VITERBI))
  522. *status |= FE_HAS_LOCK;
  523. return 0;
  524. err:
  525. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  526. return -EREMOTEIO;
  527. }
  528. static int sync_chk(struct mb86a16_state *state,
  529. unsigned char *VIRM)
  530. {
  531. unsigned char val;
  532. int sync;
  533. if (mb86a16_read(state, 0x0d, &val) != 2)
  534. goto err;
  535. dprintk(verbose, MB86A16_INFO, 1, "Status = %02x,", val);
  536. sync = val & 0x01;
  537. *VIRM = (val & 0x1c) >> 2;
  538. return sync;
  539. err:
  540. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  541. return -EREMOTEIO;
  542. }
  543. static int freqerr_chk(struct mb86a16_state *state,
  544. int fTP,
  545. int smrt,
  546. int unit)
  547. {
  548. unsigned char CRM, AFCML, AFCMH;
  549. unsigned char temp1, temp2, temp3;
  550. int crm, afcm, AFCM;
  551. int crrerr, afcerr; /* kHz */
  552. int frqerr; /* MHz */
  553. int afcen, afcexen = 0;
  554. int R, M, fOSC, fOSC_OFS;
  555. if (mb86a16_read(state, 0x43, &CRM) != 2)
  556. goto err;
  557. if (CRM > 127)
  558. crm = CRM - 256;
  559. else
  560. crm = CRM;
  561. crrerr = smrt * crm / 256;
  562. if (mb86a16_read(state, 0x49, &temp1) != 2)
  563. goto err;
  564. afcen = (temp1 & 0x04) >> 2;
  565. if (afcen == 0) {
  566. if (mb86a16_read(state, 0x2a, &temp1) != 2)
  567. goto err;
  568. afcexen = (temp1 & 0x20) >> 5;
  569. }
  570. if (afcen == 1) {
  571. if (mb86a16_read(state, 0x0e, &AFCML) != 2)
  572. goto err;
  573. if (mb86a16_read(state, 0x0f, &AFCMH) != 2)
  574. goto err;
  575. } else if (afcexen == 1) {
  576. if (mb86a16_read(state, 0x2b, &AFCML) != 2)
  577. goto err;
  578. if (mb86a16_read(state, 0x2c, &AFCMH) != 2)
  579. goto err;
  580. }
  581. if ((afcen == 1) || (afcexen == 1)) {
  582. smrt_info_get(state, smrt);
  583. AFCM = ((AFCMH & 0x01) << 8) + AFCML;
  584. if (AFCM > 255)
  585. afcm = AFCM - 512;
  586. else
  587. afcm = AFCM;
  588. afcerr = afcm * state->master_clk / 8192;
  589. } else
  590. afcerr = 0;
  591. if (mb86a16_read(state, 0x22, &temp1) != 2)
  592. goto err;
  593. if (mb86a16_read(state, 0x23, &temp2) != 2)
  594. goto err;
  595. if (mb86a16_read(state, 0x24, &temp3) != 2)
  596. goto err;
  597. R = (temp1 & 0xe0) >> 5;
  598. M = ((temp1 & 0x1f) << 12) + (temp2 << 4) + (temp3 >> 4);
  599. if (R == 0)
  600. fOSC = 2 * M;
  601. else
  602. fOSC = M;
  603. fOSC_OFS = fOSC - fTP;
  604. if (unit == 0) { /* MHz */
  605. if (crrerr + afcerr + fOSC_OFS * 1000 >= 0)
  606. frqerr = (crrerr + afcerr + fOSC_OFS * 1000 + 500) / 1000;
  607. else
  608. frqerr = (crrerr + afcerr + fOSC_OFS * 1000 - 500) / 1000;
  609. } else { /* kHz */
  610. frqerr = crrerr + afcerr + fOSC_OFS * 1000;
  611. }
  612. return frqerr;
  613. err:
  614. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  615. return -EREMOTEIO;
  616. }
  617. static unsigned char vco_dev_get(struct mb86a16_state *state, int smrt)
  618. {
  619. unsigned char R;
  620. if (smrt > 9375)
  621. R = 0;
  622. else
  623. R = 1;
  624. return R;
  625. }
  626. static void swp_info_get(struct mb86a16_state *state,
  627. int fOSC_start,
  628. int smrt,
  629. int v, int R,
  630. int swp_ofs,
  631. int *fOSC,
  632. int *afcex_freq,
  633. unsigned char *AFCEX_L,
  634. unsigned char *AFCEX_H)
  635. {
  636. int AFCEX ;
  637. int crnt_swp_freq ;
  638. crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs;
  639. if (R == 0)
  640. *fOSC = (crnt_swp_freq + 1000) / 2000 * 2;
  641. else
  642. *fOSC = (crnt_swp_freq + 500) / 1000;
  643. if (*fOSC >= crnt_swp_freq)
  644. *afcex_freq = *fOSC * 1000 - crnt_swp_freq;
  645. else
  646. *afcex_freq = crnt_swp_freq - *fOSC * 1000;
  647. AFCEX = *afcex_freq * 8192 / state->master_clk;
  648. *AFCEX_L = AFCEX & 0x00ff;
  649. *AFCEX_H = (AFCEX & 0x0f00) >> 8;
  650. }
  651. static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vmin,
  652. int SIGMIN, int fOSC, int afcex_freq, int swp_ofs, unsigned char *SIG1)
  653. {
  654. int swp_freq ;
  655. if ((i % 2 == 1) && (v <= vmax)) {
  656. /* positive v (case 1) */
  657. if ((v - 1 == vmin) &&
  658. (*(V + 30 + v) >= 0) &&
  659. (*(V + 30 + v - 1) >= 0) &&
  660. (*(V + 30 + v - 1) > *(V + 30 + v)) &&
  661. (*(V + 30 + v - 1) > SIGMIN)) {
  662. swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
  663. *SIG1 = *(V + 30 + v - 1);
  664. } else if ((v == vmax) &&
  665. (*(V + 30 + v) >= 0) &&
  666. (*(V + 30 + v - 1) >= 0) &&
  667. (*(V + 30 + v) > *(V + 30 + v - 1)) &&
  668. (*(V + 30 + v) > SIGMIN)) {
  669. /* (case 2) */
  670. swp_freq = fOSC * 1000 + afcex_freq;
  671. *SIG1 = *(V + 30 + v);
  672. } else if ((*(V + 30 + v) > 0) &&
  673. (*(V + 30 + v - 1) > 0) &&
  674. (*(V + 30 + v - 2) > 0) &&
  675. (*(V + 30 + v - 3) > 0) &&
  676. (*(V + 30 + v - 1) > *(V + 30 + v)) &&
  677. (*(V + 30 + v - 2) > *(V + 30 + v - 3)) &&
  678. ((*(V + 30 + v - 1) > SIGMIN) ||
  679. (*(V + 30 + v - 2) > SIGMIN))) {
  680. /* (case 3) */
  681. if (*(V + 30 + v - 1) >= *(V + 30 + v - 2)) {
  682. swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
  683. *SIG1 = *(V + 30 + v - 1);
  684. } else {
  685. swp_freq = fOSC * 1000 + afcex_freq - swp_ofs * 2;
  686. *SIG1 = *(V + 30 + v - 2);
  687. }
  688. } else if ((v == vmax) &&
  689. (*(V + 30 + v) >= 0) &&
  690. (*(V + 30 + v - 1) >= 0) &&
  691. (*(V + 30 + v - 2) >= 0) &&
  692. (*(V + 30 + v) > *(V + 30 + v - 2)) &&
  693. (*(V + 30 + v - 1) > *(V + 30 + v - 2)) &&
  694. ((*(V + 30 + v) > SIGMIN) ||
  695. (*(V + 30 + v - 1) > SIGMIN))) {
  696. /* (case 4) */
  697. if (*(V + 30 + v) >= *(V + 30 + v - 1)) {
  698. swp_freq = fOSC * 1000 + afcex_freq;
  699. *SIG1 = *(V + 30 + v);
  700. } else {
  701. swp_freq = fOSC * 1000 + afcex_freq - swp_ofs;
  702. *SIG1 = *(V + 30 + v - 1);
  703. }
  704. } else {
  705. swp_freq = -1 ;
  706. }
  707. } else if ((i % 2 == 0) && (v >= vmin)) {
  708. /* Negative v (case 1) */
  709. if ((*(V + 30 + v) > 0) &&
  710. (*(V + 30 + v + 1) > 0) &&
  711. (*(V + 30 + v + 2) > 0) &&
  712. (*(V + 30 + v + 1) > *(V + 30 + v)) &&
  713. (*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
  714. (*(V + 30 + v + 1) > SIGMIN)) {
  715. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
  716. *SIG1 = *(V + 30 + v + 1);
  717. } else if ((v + 1 == vmax) &&
  718. (*(V + 30 + v) >= 0) &&
  719. (*(V + 30 + v + 1) >= 0) &&
  720. (*(V + 30 + v + 1) > *(V + 30 + v)) &&
  721. (*(V + 30 + v + 1) > SIGMIN)) {
  722. /* (case 2) */
  723. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
  724. *SIG1 = *(V + 30 + v);
  725. } else if ((v == vmin) &&
  726. (*(V + 30 + v) > 0) &&
  727. (*(V + 30 + v + 1) > 0) &&
  728. (*(V + 30 + v + 2) > 0) &&
  729. (*(V + 30 + v) > *(V + 30 + v + 1)) &&
  730. (*(V + 30 + v) > *(V + 30 + v + 2)) &&
  731. (*(V + 30 + v) > SIGMIN)) {
  732. /* (case 3) */
  733. swp_freq = fOSC * 1000 + afcex_freq;
  734. *SIG1 = *(V + 30 + v);
  735. } else if ((*(V + 30 + v) >= 0) &&
  736. (*(V + 30 + v + 1) >= 0) &&
  737. (*(V + 30 + v + 2) >= 0) &&
  738. (*(V + 30 + v + 3) >= 0) &&
  739. (*(V + 30 + v + 1) > *(V + 30 + v)) &&
  740. (*(V + 30 + v + 2) > *(V + 30 + v + 3)) &&
  741. ((*(V + 30 + v + 1) > SIGMIN) ||
  742. (*(V + 30 + v + 2) > SIGMIN))) {
  743. /* (case 4) */
  744. if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
  745. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
  746. *SIG1 = *(V + 30 + v + 1);
  747. } else {
  748. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
  749. *SIG1 = *(V + 30 + v + 2);
  750. }
  751. } else if ((*(V + 30 + v) >= 0) &&
  752. (*(V + 30 + v + 1) >= 0) &&
  753. (*(V + 30 + v + 2) >= 0) &&
  754. (*(V + 30 + v + 3) >= 0) &&
  755. (*(V + 30 + v) > *(V + 30 + v + 2)) &&
  756. (*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
  757. (*(V + 30 + v) > *(V + 30 + v + 3)) &&
  758. (*(V + 30 + v + 1) > *(V + 30 + v + 3)) &&
  759. ((*(V + 30 + v) > SIGMIN) ||
  760. (*(V + 30 + v + 1) > SIGMIN))) {
  761. /* (case 5) */
  762. if (*(V + 30 + v) >= *(V + 30 + v + 1)) {
  763. swp_freq = fOSC * 1000 + afcex_freq;
  764. *SIG1 = *(V + 30 + v);
  765. } else {
  766. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
  767. *SIG1 = *(V + 30 + v + 1);
  768. }
  769. } else if ((v + 2 == vmin) &&
  770. (*(V + 30 + v) >= 0) &&
  771. (*(V + 30 + v + 1) >= 0) &&
  772. (*(V + 30 + v + 2) >= 0) &&
  773. (*(V + 30 + v + 1) > *(V + 30 + v)) &&
  774. (*(V + 30 + v + 2) > *(V + 30 + v)) &&
  775. ((*(V + 30 + v + 1) > SIGMIN) ||
  776. (*(V + 30 + v + 2) > SIGMIN))) {
  777. /* (case 6) */
  778. if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
  779. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs;
  780. *SIG1 = *(V + 30 + v + 1);
  781. } else {
  782. swp_freq = fOSC * 1000 + afcex_freq + swp_ofs * 2;
  783. *SIG1 = *(V + 30 + v + 2);
  784. }
  785. } else if ((vmax == 0) && (vmin == 0) && (*(V + 30 + v) > SIGMIN)) {
  786. swp_freq = fOSC * 1000;
  787. *SIG1 = *(V + 30 + v);
  788. } else
  789. swp_freq = -1;
  790. } else
  791. swp_freq = -1;
  792. return swp_freq;
  793. }
  794. static void swp_info_get2(struct mb86a16_state *state,
  795. int smrt,
  796. int R,
  797. int swp_freq,
  798. int *afcex_freq,
  799. int *fOSC,
  800. unsigned char *AFCEX_L,
  801. unsigned char *AFCEX_H)
  802. {
  803. int AFCEX ;
  804. if (R == 0)
  805. *fOSC = (swp_freq + 1000) / 2000 * 2;
  806. else
  807. *fOSC = (swp_freq + 500) / 1000;
  808. if (*fOSC >= swp_freq)
  809. *afcex_freq = *fOSC * 1000 - swp_freq;
  810. else
  811. *afcex_freq = swp_freq - *fOSC * 1000;
  812. AFCEX = *afcex_freq * 8192 / state->master_clk;
  813. *AFCEX_L = AFCEX & 0x00ff;
  814. *AFCEX_H = (AFCEX & 0x0f00) >> 8;
  815. }
  816. static void afcex_info_get(struct mb86a16_state *state,
  817. int afcex_freq,
  818. unsigned char *AFCEX_L,
  819. unsigned char *AFCEX_H)
  820. {
  821. int AFCEX ;
  822. AFCEX = afcex_freq * 8192 / state->master_clk;
  823. *AFCEX_L = AFCEX & 0x00ff;
  824. *AFCEX_H = (AFCEX & 0x0f00) >> 8;
  825. }
  826. static int SEQ_set(struct mb86a16_state *state, unsigned char loop)
  827. {
  828. /* SLOCK0 = 0 */
  829. if (mb86a16_write(state, 0x32, 0x02 | (loop << 2)) < 0) {
  830. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  831. return -EREMOTEIO;
  832. }
  833. return 0;
  834. }
  835. static int iq_vt_set(struct mb86a16_state *state, unsigned char IQINV)
  836. {
  837. /* Viterbi Rate, IQ Settings */
  838. if (mb86a16_write(state, 0x06, 0xdf | (IQINV << 5)) < 0) {
  839. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  840. return -EREMOTEIO;
  841. }
  842. return 0;
  843. }
  844. static int FEC_srst(struct mb86a16_state *state)
  845. {
  846. if (mb86a16_write(state, MB86A16_RESET, 0x02) < 0) {
  847. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  848. return -EREMOTEIO;
  849. }
  850. return 0;
  851. }
  852. static int S2T_set(struct mb86a16_state *state, unsigned char S2T)
  853. {
  854. if (mb86a16_write(state, 0x34, 0x70 | S2T) < 0) {
  855. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  856. return -EREMOTEIO;
  857. }
  858. return 0;
  859. }
  860. static int S45T_set(struct mb86a16_state *state, unsigned char S4T, unsigned char S5T)
  861. {
  862. if (mb86a16_write(state, 0x35, 0x00 | (S5T << 4) | S4T) < 0) {
  863. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  864. return -EREMOTEIO;
  865. }
  866. return 0;
  867. }
  868. static int mb86a16_set_fe(struct mb86a16_state *state)
  869. {
  870. u8 agcval, cnmval;
  871. int i, j;
  872. int fOSC = 0;
  873. int fOSC_start = 0;
  874. int wait_t;
  875. int fcp;
  876. int swp_ofs;
  877. int V[60];
  878. u8 SIG1MIN;
  879. unsigned char CREN, AFCEN, AFCEXEN;
  880. unsigned char SIG1;
  881. unsigned char TIMINT1, TIMINT2, TIMEXT;
  882. unsigned char S0T, S1T;
  883. unsigned char S2T;
  884. /* unsigned char S2T, S3T; */
  885. unsigned char S4T, S5T;
  886. unsigned char AFCEX_L, AFCEX_H;
  887. unsigned char R;
  888. unsigned char VIRM;
  889. unsigned char ETH, VIA;
  890. unsigned char junk;
  891. int loop;
  892. int ftemp;
  893. int v, vmax, vmin;
  894. int vmax_his, vmin_his;
  895. int swp_freq, prev_swp_freq[20];
  896. int prev_freq_num;
  897. int signal_dupl;
  898. int afcex_freq;
  899. int signal;
  900. int afcerr;
  901. int temp_freq, delta_freq;
  902. int dagcm[4];
  903. int smrt_d;
  904. /* int freq_err; */
  905. int n;
  906. int ret = -1;
  907. int sync;
  908. dprintk(verbose, MB86A16_INFO, 1, "freq=%d Mhz, symbrt=%d Ksps", state->frequency, state->srate);
  909. fcp = 3000;
  910. swp_ofs = state->srate / 4;
  911. for (i = 0; i < 60; i++)
  912. V[i] = -1;
  913. for (i = 0; i < 20; i++)
  914. prev_swp_freq[i] = 0;
  915. SIG1MIN = 25;
  916. for (n = 0; ((n < 3) && (ret == -1)); n++) {
  917. SEQ_set(state, 0);
  918. iq_vt_set(state, 0);
  919. CREN = 0;
  920. AFCEN = 0;
  921. AFCEXEN = 1;
  922. TIMINT1 = 0;
  923. TIMINT2 = 1;
  924. TIMEXT = 2;
  925. S1T = 0;
  926. S0T = 0;
  927. if (initial_set(state) < 0) {
  928. dprintk(verbose, MB86A16_ERROR, 1, "initial set failed");
  929. return -1;
  930. }
  931. if (DAGC_data_set(state, 3, 2) < 0) {
  932. dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
  933. return -1;
  934. }
  935. if (EN_set(state, CREN, AFCEN) < 0) {
  936. dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
  937. return -1; /* (0, 0) */
  938. }
  939. if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
  940. dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
  941. return -1; /* (1, smrt) = (1, symbolrate) */
  942. }
  943. if (CNTM_set(state, TIMINT1, TIMINT2, TIMEXT) < 0) {
  944. dprintk(verbose, MB86A16_ERROR, 1, "CNTM set error");
  945. return -1; /* (0, 1, 2) */
  946. }
  947. if (S01T_set(state, S1T, S0T) < 0) {
  948. dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
  949. return -1; /* (0, 0) */
  950. }
  951. smrt_info_get(state, state->srate);
  952. if (smrt_set(state, state->srate) < 0) {
  953. dprintk(verbose, MB86A16_ERROR, 1, "smrt info get error");
  954. return -1;
  955. }
  956. R = vco_dev_get(state, state->srate);
  957. if (R == 1)
  958. fOSC_start = state->frequency;
  959. else if (R == 0) {
  960. if (state->frequency % 2 == 0) {
  961. fOSC_start = state->frequency;
  962. } else {
  963. fOSC_start = state->frequency + 1;
  964. if (fOSC_start > 2150)
  965. fOSC_start = state->frequency - 1;
  966. }
  967. }
  968. loop = 1;
  969. ftemp = fOSC_start * 1000;
  970. vmax = 0 ;
  971. while (loop == 1) {
  972. ftemp = ftemp + swp_ofs;
  973. vmax++;
  974. /* Upper bound */
  975. if (ftemp > 2150000) {
  976. loop = 0;
  977. vmax--;
  978. } else {
  979. if ((ftemp == 2150000) ||
  980. (ftemp - state->frequency * 1000 >= fcp + state->srate / 4))
  981. loop = 0;
  982. }
  983. }
  984. loop = 1;
  985. ftemp = fOSC_start * 1000;
  986. vmin = 0 ;
  987. while (loop == 1) {
  988. ftemp = ftemp - swp_ofs;
  989. vmin--;
  990. /* Lower bound */
  991. if (ftemp < 950000) {
  992. loop = 0;
  993. vmin++;
  994. } else {
  995. if ((ftemp == 950000) ||
  996. (state->frequency * 1000 - ftemp >= fcp + state->srate / 4))
  997. loop = 0;
  998. }
  999. }
  1000. wait_t = (8000 + state->srate / 2) / state->srate;
  1001. if (wait_t == 0)
  1002. wait_t = 1;
  1003. i = 0;
  1004. j = 0;
  1005. prev_freq_num = 0;
  1006. loop = 1;
  1007. signal = 0;
  1008. vmax_his = 0;
  1009. vmin_his = 0;
  1010. v = 0;
  1011. while (loop == 1) {
  1012. swp_info_get(state, fOSC_start, state->srate,
  1013. v, R, swp_ofs, &fOSC,
  1014. &afcex_freq, &AFCEX_L, &AFCEX_H);
  1015. udelay(100);
  1016. if (rf_val_set(state, fOSC, state->srate, R) < 0) {
  1017. dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
  1018. return -1;
  1019. }
  1020. udelay(100);
  1021. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1022. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
  1023. return -1;
  1024. }
  1025. if (srst(state) < 0) {
  1026. dprintk(verbose, MB86A16_ERROR, 1, "srst error");
  1027. return -1;
  1028. }
  1029. msleep_interruptible(wait_t);
  1030. if (mb86a16_read(state, 0x37, &SIG1) != 2) {
  1031. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1032. return -1;
  1033. }
  1034. V[30 + v] = SIG1 ;
  1035. swp_freq = swp_freq_calcuation(state, i, v, V, vmax, vmin,
  1036. SIG1MIN, fOSC, afcex_freq,
  1037. swp_ofs, &SIG1); /* changed */
  1038. signal_dupl = 0;
  1039. for (j = 0; j < prev_freq_num; j++) {
  1040. if ((ABS(prev_swp_freq[j] - swp_freq)) < (swp_ofs * 3 / 2)) {
  1041. signal_dupl = 1;
  1042. dprintk(verbose, MB86A16_INFO, 1, "Probably Duplicate Signal, j = %d", j);
  1043. }
  1044. }
  1045. if ((signal_dupl == 0) && (swp_freq > 0) && (ABS(swp_freq - state->frequency * 1000) < fcp + state->srate / 6)) {
  1046. dprintk(verbose, MB86A16_DEBUG, 1, "------ Signal detect ------ [swp_freq=[%07d, srate=%05d]]", swp_freq, state->srate);
  1047. prev_swp_freq[prev_freq_num] = swp_freq;
  1048. prev_freq_num++;
  1049. swp_info_get2(state, state->srate, R, swp_freq,
  1050. &afcex_freq, &fOSC,
  1051. &AFCEX_L, &AFCEX_H);
  1052. if (rf_val_set(state, fOSC, state->srate, R) < 0) {
  1053. dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
  1054. return -1;
  1055. }
  1056. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1057. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
  1058. return -1;
  1059. }
  1060. signal = signal_det(state, state->srate, &SIG1);
  1061. if (signal == 1) {
  1062. dprintk(verbose, MB86A16_ERROR, 1, "***** Signal Found *****");
  1063. loop = 0;
  1064. } else {
  1065. dprintk(verbose, MB86A16_ERROR, 1, "!!!!! No signal !!!!!, try again...");
  1066. smrt_info_get(state, state->srate);
  1067. if (smrt_set(state, state->srate) < 0) {
  1068. dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
  1069. return -1;
  1070. }
  1071. }
  1072. }
  1073. if (v > vmax)
  1074. vmax_his = 1 ;
  1075. if (v < vmin)
  1076. vmin_his = 1 ;
  1077. i++;
  1078. if ((i % 2 == 1) && (vmax_his == 1))
  1079. i++;
  1080. if ((i % 2 == 0) && (vmin_his == 1))
  1081. i++;
  1082. if (i % 2 == 1)
  1083. v = (i + 1) / 2;
  1084. else
  1085. v = -i / 2;
  1086. if ((vmax_his == 1) && (vmin_his == 1))
  1087. loop = 0 ;
  1088. }
  1089. if (signal == 1) {
  1090. dprintk(verbose, MB86A16_INFO, 1, " Start Freq Error Check");
  1091. S1T = 7 ;
  1092. S0T = 1 ;
  1093. CREN = 0 ;
  1094. AFCEN = 1 ;
  1095. AFCEXEN = 0 ;
  1096. if (S01T_set(state, S1T, S0T) < 0) {
  1097. dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
  1098. return -1;
  1099. }
  1100. smrt_info_get(state, state->srate);
  1101. if (smrt_set(state, state->srate) < 0) {
  1102. dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
  1103. return -1;
  1104. }
  1105. if (EN_set(state, CREN, AFCEN) < 0) {
  1106. dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
  1107. return -1;
  1108. }
  1109. if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
  1110. dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
  1111. return -1;
  1112. }
  1113. afcex_info_get(state, afcex_freq, &AFCEX_L, &AFCEX_H);
  1114. if (afcofs_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1115. dprintk(verbose, MB86A16_ERROR, 1, "AFCOFS data set error");
  1116. return -1;
  1117. }
  1118. if (srst(state) < 0) {
  1119. dprintk(verbose, MB86A16_ERROR, 1, "srst error");
  1120. return -1;
  1121. }
  1122. /* delay 4~200 */
  1123. wait_t = 200000 / state->master_clk + 200000 / state->srate;
  1124. msleep(wait_t);
  1125. afcerr = afcerr_chk(state);
  1126. if (afcerr == -1)
  1127. return -1;
  1128. swp_freq = fOSC * 1000 + afcerr ;
  1129. AFCEXEN = 1 ;
  1130. if (state->srate >= 1500)
  1131. smrt_d = state->srate / 3;
  1132. else
  1133. smrt_d = state->srate / 2;
  1134. smrt_info_get(state, smrt_d);
  1135. if (smrt_set(state, smrt_d) < 0) {
  1136. dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
  1137. return -1;
  1138. }
  1139. if (AFCEXEN_set(state, AFCEXEN, smrt_d) < 0) {
  1140. dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
  1141. return -1;
  1142. }
  1143. R = vco_dev_get(state, smrt_d);
  1144. if (DAGC_data_set(state, 2, 0) < 0) {
  1145. dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
  1146. return -1;
  1147. }
  1148. for (i = 0; i < 3; i++) {
  1149. temp_freq = swp_freq + (i - 1) * state->srate / 8;
  1150. swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
  1151. if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
  1152. dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
  1153. return -1;
  1154. }
  1155. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1156. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
  1157. return -1;
  1158. }
  1159. wait_t = 200000 / state->master_clk + 40000 / smrt_d;
  1160. msleep(wait_t);
  1161. dagcm[i] = dagcm_val_get(state);
  1162. }
  1163. if ((dagcm[0] > dagcm[1]) &&
  1164. (dagcm[0] > dagcm[2]) &&
  1165. (dagcm[0] - dagcm[1] > 2 * (dagcm[2] - dagcm[1]))) {
  1166. temp_freq = swp_freq - 2 * state->srate / 8;
  1167. swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
  1168. if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
  1169. dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
  1170. return -1;
  1171. }
  1172. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1173. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
  1174. return -1;
  1175. }
  1176. wait_t = 200000 / state->master_clk + 40000 / smrt_d;
  1177. msleep(wait_t);
  1178. dagcm[3] = dagcm_val_get(state);
  1179. if (dagcm[3] > dagcm[1])
  1180. delta_freq = (dagcm[2] - dagcm[0] + dagcm[1] - dagcm[3]) * state->srate / 300;
  1181. else
  1182. delta_freq = 0;
  1183. } else if ((dagcm[2] > dagcm[1]) &&
  1184. (dagcm[2] > dagcm[0]) &&
  1185. (dagcm[2] - dagcm[1] > 2 * (dagcm[0] - dagcm[1]))) {
  1186. temp_freq = swp_freq + 2 * state->srate / 8;
  1187. swp_info_get2(state, smrt_d, R, temp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
  1188. if (rf_val_set(state, fOSC, smrt_d, R) < 0) {
  1189. dprintk(verbose, MB86A16_ERROR, 1, "rf val set");
  1190. return -1;
  1191. }
  1192. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1193. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set");
  1194. return -1;
  1195. }
  1196. wait_t = 200000 / state->master_clk + 40000 / smrt_d;
  1197. msleep(wait_t);
  1198. dagcm[3] = dagcm_val_get(state);
  1199. if (dagcm[3] > dagcm[1])
  1200. delta_freq = (dagcm[2] - dagcm[0] + dagcm[3] - dagcm[1]) * state->srate / 300;
  1201. else
  1202. delta_freq = 0 ;
  1203. } else {
  1204. delta_freq = 0 ;
  1205. }
  1206. dprintk(verbose, MB86A16_INFO, 1, "SWEEP Frequency = %d", swp_freq);
  1207. swp_freq += delta_freq;
  1208. dprintk(verbose, MB86A16_INFO, 1, "Adjusting .., DELTA Freq = %d, SWEEP Freq=%d", delta_freq, swp_freq);
  1209. if (ABS(state->frequency * 1000 - swp_freq) > 3800) {
  1210. dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL !");
  1211. } else {
  1212. S1T = 0;
  1213. S0T = 3;
  1214. CREN = 1;
  1215. AFCEN = 0;
  1216. AFCEXEN = 1;
  1217. if (S01T_set(state, S1T, S0T) < 0) {
  1218. dprintk(verbose, MB86A16_ERROR, 1, "S01T set error");
  1219. return -1;
  1220. }
  1221. if (DAGC_data_set(state, 0, 0) < 0) {
  1222. dprintk(verbose, MB86A16_ERROR, 1, "DAGC data set error");
  1223. return -1;
  1224. }
  1225. R = vco_dev_get(state, state->srate);
  1226. smrt_info_get(state, state->srate);
  1227. if (smrt_set(state, state->srate) < 0) {
  1228. dprintk(verbose, MB86A16_ERROR, 1, "smrt set error");
  1229. return -1;
  1230. }
  1231. if (EN_set(state, CREN, AFCEN) < 0) {
  1232. dprintk(verbose, MB86A16_ERROR, 1, "EN set error");
  1233. return -1;
  1234. }
  1235. if (AFCEXEN_set(state, AFCEXEN, state->srate) < 0) {
  1236. dprintk(verbose, MB86A16_ERROR, 1, "AFCEXEN set error");
  1237. return -1;
  1238. }
  1239. swp_info_get2(state, state->srate, R, swp_freq, &afcex_freq, &fOSC, &AFCEX_L, &AFCEX_H);
  1240. if (rf_val_set(state, fOSC, state->srate, R) < 0) {
  1241. dprintk(verbose, MB86A16_ERROR, 1, "rf val set error");
  1242. return -1;
  1243. }
  1244. if (afcex_data_set(state, AFCEX_L, AFCEX_H) < 0) {
  1245. dprintk(verbose, MB86A16_ERROR, 1, "afcex data set error");
  1246. return -1;
  1247. }
  1248. if (srst(state) < 0) {
  1249. dprintk(verbose, MB86A16_ERROR, 1, "srst error");
  1250. return -1;
  1251. }
  1252. wait_t = 7 + (10000 + state->srate / 2) / state->srate;
  1253. if (wait_t == 0)
  1254. wait_t = 1;
  1255. msleep_interruptible(wait_t);
  1256. if (mb86a16_read(state, 0x37, &SIG1) != 2) {
  1257. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1258. return -EREMOTEIO;
  1259. }
  1260. if (SIG1 > 110) {
  1261. S2T = 4; S4T = 1; S5T = 6; ETH = 4; VIA = 6;
  1262. wait_t = 7 + (917504 + state->srate / 2) / state->srate;
  1263. } else if (SIG1 > 105) {
  1264. S2T = 4; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
  1265. wait_t = 7 + (1048576 + state->srate / 2) / state->srate;
  1266. } else if (SIG1 > 85) {
  1267. S2T = 5; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
  1268. wait_t = 7 + (1310720 + state->srate / 2) / state->srate;
  1269. } else if (SIG1 > 65) {
  1270. S2T = 6; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
  1271. wait_t = 7 + (1572864 + state->srate / 2) / state->srate;
  1272. } else {
  1273. S2T = 7; S4T = 2; S5T = 8; ETH = 7; VIA = 2;
  1274. wait_t = 7 + (2097152 + state->srate / 2) / state->srate;
  1275. }
  1276. wait_t *= 2; /* FOS */
  1277. S2T_set(state, S2T);
  1278. S45T_set(state, S4T, S5T);
  1279. Vi_set(state, ETH, VIA);
  1280. srst(state);
  1281. msleep_interruptible(wait_t);
  1282. sync = sync_chk(state, &VIRM);
  1283. dprintk(verbose, MB86A16_INFO, 1, "-------- Viterbi=[%d] SYNC=[%d] ---------", VIRM, sync);
  1284. if (VIRM) {
  1285. if (VIRM == 4) {
  1286. /* 5/6 */
  1287. if (SIG1 > 110)
  1288. wait_t = (786432 + state->srate / 2) / state->srate;
  1289. else
  1290. wait_t = (1572864 + state->srate / 2) / state->srate;
  1291. if (state->srate < 5000)
  1292. /* FIXME ! , should be a long wait ! */
  1293. msleep_interruptible(wait_t);
  1294. else
  1295. msleep_interruptible(wait_t);
  1296. if (sync_chk(state, &junk) == 0) {
  1297. iq_vt_set(state, 1);
  1298. FEC_srst(state);
  1299. }
  1300. }
  1301. /* 1/2, 2/3, 3/4, 7/8 */
  1302. if (SIG1 > 110)
  1303. wait_t = (786432 + state->srate / 2) / state->srate;
  1304. else
  1305. wait_t = (1572864 + state->srate / 2) / state->srate;
  1306. msleep_interruptible(wait_t);
  1307. SEQ_set(state, 1);
  1308. } else {
  1309. dprintk(verbose, MB86A16_INFO, 1, "NO -- SYNC");
  1310. SEQ_set(state, 1);
  1311. ret = -1;
  1312. }
  1313. }
  1314. } else {
  1315. dprintk(verbose, MB86A16_INFO, 1, "NO -- SIGNAL");
  1316. ret = -1;
  1317. }
  1318. sync = sync_chk(state, &junk);
  1319. if (sync) {
  1320. dprintk(verbose, MB86A16_INFO, 1, "******* SYNC *******");
  1321. freqerr_chk(state, state->frequency, state->srate, 1);
  1322. ret = 0;
  1323. break;
  1324. }
  1325. }
  1326. mb86a16_read(state, 0x15, &agcval);
  1327. mb86a16_read(state, 0x26, &cnmval);
  1328. dprintk(verbose, MB86A16_INFO, 1, "AGC = %02x CNM = %02x", agcval, cnmval);
  1329. return ret;
  1330. }
  1331. static int mb86a16_send_diseqc_msg(struct dvb_frontend *fe,
  1332. struct dvb_diseqc_master_cmd *cmd)
  1333. {
  1334. struct mb86a16_state *state = fe->demodulator_priv;
  1335. int i;
  1336. u8 regs;
  1337. if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
  1338. goto err;
  1339. if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
  1340. goto err;
  1341. if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
  1342. goto err;
  1343. regs = 0x18;
  1344. if (cmd->msg_len > 5 || cmd->msg_len < 4)
  1345. return -EINVAL;
  1346. for (i = 0; i < cmd->msg_len; i++) {
  1347. if (mb86a16_write(state, regs, cmd->msg[i]) < 0)
  1348. goto err;
  1349. regs++;
  1350. }
  1351. i += 0x90;
  1352. msleep_interruptible(10);
  1353. if (mb86a16_write(state, MB86A16_DCC1, i) < 0)
  1354. goto err;
  1355. if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
  1356. goto err;
  1357. return 0;
  1358. err:
  1359. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1360. return -EREMOTEIO;
  1361. }
  1362. static int mb86a16_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
  1363. {
  1364. struct mb86a16_state *state = fe->demodulator_priv;
  1365. switch (burst) {
  1366. case SEC_MINI_A:
  1367. if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
  1368. MB86A16_DCC1_TBEN |
  1369. MB86A16_DCC1_TBO) < 0)
  1370. goto err;
  1371. if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
  1372. goto err;
  1373. break;
  1374. case SEC_MINI_B:
  1375. if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
  1376. MB86A16_DCC1_TBEN) < 0)
  1377. goto err;
  1378. if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
  1379. goto err;
  1380. break;
  1381. }
  1382. return 0;
  1383. err:
  1384. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1385. return -EREMOTEIO;
  1386. }
  1387. static int mb86a16_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
  1388. {
  1389. struct mb86a16_state *state = fe->demodulator_priv;
  1390. switch (tone) {
  1391. case SEC_TONE_ON:
  1392. if (mb86a16_write(state, MB86A16_TONEOUT2, 0x00) < 0)
  1393. goto err;
  1394. if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA |
  1395. MB86A16_DCC1_CTOE) < 0)
  1396. goto err;
  1397. if (mb86a16_write(state, MB86A16_DCCOUT, MB86A16_DCCOUT_DISEN) < 0)
  1398. goto err;
  1399. break;
  1400. case SEC_TONE_OFF:
  1401. if (mb86a16_write(state, MB86A16_TONEOUT2, 0x04) < 0)
  1402. goto err;
  1403. if (mb86a16_write(state, MB86A16_DCC1, MB86A16_DCC1_DISTA) < 0)
  1404. goto err;
  1405. if (mb86a16_write(state, MB86A16_DCCOUT, 0x00) < 0)
  1406. goto err;
  1407. break;
  1408. default:
  1409. return -EINVAL;
  1410. }
  1411. return 0;
  1412. err:
  1413. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1414. return -EREMOTEIO;
  1415. }
  1416. static enum dvbfe_search mb86a16_search(struct dvb_frontend *fe,
  1417. struct dvb_frontend_parameters *p)
  1418. {
  1419. struct mb86a16_state *state = fe->demodulator_priv;
  1420. state->frequency = p->frequency / 1000;
  1421. state->srate = p->u.qpsk.symbol_rate / 1000;
  1422. if (!mb86a16_set_fe(state)) {
  1423. dprintk(verbose, MB86A16_ERROR, 1, "Successfully acquired LOCK");
  1424. return DVBFE_ALGO_SEARCH_SUCCESS;
  1425. }
  1426. dprintk(verbose, MB86A16_ERROR, 1, "Lock acquisition failed!");
  1427. return DVBFE_ALGO_SEARCH_FAILED;
  1428. }
  1429. static void mb86a16_release(struct dvb_frontend *fe)
  1430. {
  1431. struct mb86a16_state *state = fe->demodulator_priv;
  1432. kfree(state);
  1433. }
  1434. static int mb86a16_init(struct dvb_frontend *fe)
  1435. {
  1436. return 0;
  1437. }
  1438. static int mb86a16_sleep(struct dvb_frontend *fe)
  1439. {
  1440. return 0;
  1441. }
  1442. static int mb86a16_read_ber(struct dvb_frontend *fe, u32 *ber)
  1443. {
  1444. u8 ber_mon, ber_tab, ber_lsb, ber_mid, ber_msb, ber_tim, ber_rst;
  1445. u32 timer;
  1446. struct mb86a16_state *state = fe->demodulator_priv;
  1447. *ber = 0;
  1448. if (mb86a16_read(state, MB86A16_BERMON, &ber_mon) != 2)
  1449. goto err;
  1450. if (mb86a16_read(state, MB86A16_BERTAB, &ber_tab) != 2)
  1451. goto err;
  1452. if (mb86a16_read(state, MB86A16_BERLSB, &ber_lsb) != 2)
  1453. goto err;
  1454. if (mb86a16_read(state, MB86A16_BERMID, &ber_mid) != 2)
  1455. goto err;
  1456. if (mb86a16_read(state, MB86A16_BERMSB, &ber_msb) != 2)
  1457. goto err;
  1458. /* BER monitor invalid when BER_EN = 0 */
  1459. if (ber_mon & 0x04) {
  1460. /* coarse, fast calculation */
  1461. *ber = ber_tab & 0x1f;
  1462. dprintk(verbose, MB86A16_DEBUG, 1, "BER coarse=[0x%02x]", *ber);
  1463. if (ber_mon & 0x01) {
  1464. /*
  1465. * BER_SEL = 1, The monitored BER is the estimated
  1466. * value with a Reed-Solomon decoder error amount at
  1467. * the deinterleaver output.
  1468. * monitored BER is expressed as a 20 bit output in total
  1469. */
  1470. ber_rst = ber_mon >> 3;
  1471. *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
  1472. if (ber_rst == 0)
  1473. timer = 12500000;
  1474. if (ber_rst == 1)
  1475. timer = 25000000;
  1476. if (ber_rst == 2)
  1477. timer = 50000000;
  1478. if (ber_rst == 3)
  1479. timer = 100000000;
  1480. *ber /= timer;
  1481. dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
  1482. } else {
  1483. /*
  1484. * BER_SEL = 0, The monitored BER is the estimated
  1485. * value with a Viterbi decoder error amount at the
  1486. * QPSK demodulator output.
  1487. * monitored BER is expressed as a 24 bit output in total
  1488. */
  1489. ber_tim = ber_mon >> 1;
  1490. *ber = (((ber_msb << 8) | ber_mid) << 8) | ber_lsb;
  1491. if (ber_tim == 0)
  1492. timer = 16;
  1493. if (ber_tim == 1)
  1494. timer = 24;
  1495. *ber /= 2 ^ timer;
  1496. dprintk(verbose, MB86A16_DEBUG, 1, "BER fine=[0x%02x]", *ber);
  1497. }
  1498. }
  1499. return 0;
  1500. err:
  1501. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1502. return -EREMOTEIO;
  1503. }
  1504. static int mb86a16_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
  1505. {
  1506. u8 agcm = 0;
  1507. struct mb86a16_state *state = fe->demodulator_priv;
  1508. *strength = 0;
  1509. if (mb86a16_read(state, MB86A16_AGCM, &agcm) != 2) {
  1510. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1511. return -EREMOTEIO;
  1512. }
  1513. *strength = ((0xff - agcm) * 100) / 256;
  1514. dprintk(verbose, MB86A16_DEBUG, 1, "Signal strength=[%d %%]", (u8) *strength);
  1515. *strength = (0xffff - 0xff) + agcm;
  1516. return 0;
  1517. }
  1518. struct cnr {
  1519. u8 cn_reg;
  1520. u8 cn_val;
  1521. };
  1522. static const struct cnr cnr_tab[] = {
  1523. { 35, 2 },
  1524. { 40, 3 },
  1525. { 50, 4 },
  1526. { 60, 5 },
  1527. { 70, 6 },
  1528. { 80, 7 },
  1529. { 92, 8 },
  1530. { 103, 9 },
  1531. { 115, 10 },
  1532. { 138, 12 },
  1533. { 162, 15 },
  1534. { 180, 18 },
  1535. { 185, 19 },
  1536. { 189, 20 },
  1537. { 195, 22 },
  1538. { 199, 24 },
  1539. { 201, 25 },
  1540. { 202, 26 },
  1541. { 203, 27 },
  1542. { 205, 28 },
  1543. { 208, 30 }
  1544. };
  1545. static int mb86a16_read_snr(struct dvb_frontend *fe, u16 *snr)
  1546. {
  1547. struct mb86a16_state *state = fe->demodulator_priv;
  1548. int i = 0;
  1549. int low_tide = 2, high_tide = 30, q_level;
  1550. u8 cn;
  1551. *snr = 0;
  1552. if (mb86a16_read(state, 0x26, &cn) != 2) {
  1553. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1554. return -EREMOTEIO;
  1555. }
  1556. for (i = 0; i < ARRAY_SIZE(cnr_tab); i++) {
  1557. if (cn < cnr_tab[i].cn_reg) {
  1558. *snr = cnr_tab[i].cn_val;
  1559. break;
  1560. }
  1561. }
  1562. q_level = (*snr * 100) / (high_tide - low_tide);
  1563. dprintk(verbose, MB86A16_ERROR, 1, "SNR (Quality) = [%d dB], Level=%d %%", *snr, q_level);
  1564. *snr = (0xffff - 0xff) + *snr;
  1565. return 0;
  1566. }
  1567. static int mb86a16_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
  1568. {
  1569. u8 dist;
  1570. struct mb86a16_state *state = fe->demodulator_priv;
  1571. if (mb86a16_read(state, MB86A16_DISTMON, &dist) != 2) {
  1572. dprintk(verbose, MB86A16_ERROR, 1, "I2C transfer error");
  1573. return -EREMOTEIO;
  1574. }
  1575. *ucblocks = dist;
  1576. return 0;
  1577. }
  1578. static enum dvbfe_algo mb86a16_frontend_algo(struct dvb_frontend *fe)
  1579. {
  1580. return DVBFE_ALGO_CUSTOM;
  1581. }
  1582. static struct dvb_frontend_ops mb86a16_ops = {
  1583. .info = {
  1584. .name = "Fujitsu MB86A16 DVB-S",
  1585. .type = FE_QPSK,
  1586. .frequency_min = 950000,
  1587. .frequency_max = 2150000,
  1588. .frequency_stepsize = 3000,
  1589. .frequency_tolerance = 0,
  1590. .symbol_rate_min = 1000000,
  1591. .symbol_rate_max = 45000000,
  1592. .symbol_rate_tolerance = 500,
  1593. .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
  1594. FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
  1595. FE_CAN_FEC_7_8 | FE_CAN_QPSK |
  1596. FE_CAN_FEC_AUTO
  1597. },
  1598. .release = mb86a16_release,
  1599. .get_frontend_algo = mb86a16_frontend_algo,
  1600. .search = mb86a16_search,
  1601. .init = mb86a16_init,
  1602. .sleep = mb86a16_sleep,
  1603. .read_status = mb86a16_read_status,
  1604. .read_ber = mb86a16_read_ber,
  1605. .read_signal_strength = mb86a16_read_signal_strength,
  1606. .read_snr = mb86a16_read_snr,
  1607. .read_ucblocks = mb86a16_read_ucblocks,
  1608. .diseqc_send_master_cmd = mb86a16_send_diseqc_msg,
  1609. .diseqc_send_burst = mb86a16_send_diseqc_burst,
  1610. .set_tone = mb86a16_set_tone,
  1611. };
  1612. struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config,
  1613. struct i2c_adapter *i2c_adap)
  1614. {
  1615. u8 dev_id = 0;
  1616. struct mb86a16_state *state = NULL;
  1617. state = kmalloc(sizeof(struct mb86a16_state), GFP_KERNEL);
  1618. if (state == NULL)
  1619. goto error;
  1620. state->config = config;
  1621. state->i2c_adap = i2c_adap;
  1622. mb86a16_read(state, 0x7f, &dev_id);
  1623. if (dev_id != 0xfe)
  1624. goto error;
  1625. memcpy(&state->frontend.ops, &mb86a16_ops, sizeof(struct dvb_frontend_ops));
  1626. state->frontend.demodulator_priv = state;
  1627. state->frontend.ops.set_voltage = state->config->set_voltage;
  1628. return &state->frontend;
  1629. error:
  1630. kfree(state);
  1631. return NULL;
  1632. }
  1633. EXPORT_SYMBOL(mb86a16_attach);
  1634. MODULE_LICENSE("GPL");
  1635. MODULE_AUTHOR("Manu Abraham");