q40ide.c 4.1 KB

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  1. /*
  2. * Q40 I/O port IDE Driver
  3. *
  4. * (c) Richard Zidlicky
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file COPYING in the main directory of this archive for
  8. * more details.
  9. *
  10. *
  11. */
  12. #include <linux/types.h>
  13. #include <linux/mm.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/blkdev.h>
  16. #include <linux/ide.h>
  17. #include <asm/ide.h>
  18. /*
  19. * Bases of the IDE interfaces
  20. */
  21. #define Q40IDE_NUM_HWIFS 2
  22. #define PCIDE_BASE1 0x1f0
  23. #define PCIDE_BASE2 0x170
  24. #define PCIDE_BASE3 0x1e8
  25. #define PCIDE_BASE4 0x168
  26. #define PCIDE_BASE5 0x1e0
  27. #define PCIDE_BASE6 0x160
  28. static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = {
  29. PCIDE_BASE1, PCIDE_BASE2, /* PCIDE_BASE3, PCIDE_BASE4 , PCIDE_BASE5,
  30. PCIDE_BASE6 */
  31. };
  32. static int q40ide_default_irq(unsigned long base)
  33. {
  34. switch (base) {
  35. case 0x1f0: return 14;
  36. case 0x170: return 15;
  37. case 0x1e8: return 11;
  38. default:
  39. return 0;
  40. }
  41. }
  42. /*
  43. * Addresses are pretranslated for Q40 ISA access.
  44. */
  45. static void q40_ide_setup_ports(struct ide_hw *hw, unsigned long base, int irq)
  46. {
  47. memset(hw, 0, sizeof(*hw));
  48. /* BIG FAT WARNING:
  49. assumption: only DATA port is ever used in 16 bit mode */
  50. hw->io_ports.data_addr = Q40_ISA_IO_W(base);
  51. hw->io_ports.error_addr = Q40_ISA_IO_B(base + 1);
  52. hw->io_ports.nsect_addr = Q40_ISA_IO_B(base + 2);
  53. hw->io_ports.lbal_addr = Q40_ISA_IO_B(base + 3);
  54. hw->io_ports.lbam_addr = Q40_ISA_IO_B(base + 4);
  55. hw->io_ports.lbah_addr = Q40_ISA_IO_B(base + 5);
  56. hw->io_ports.device_addr = Q40_ISA_IO_B(base + 6);
  57. hw->io_ports.status_addr = Q40_ISA_IO_B(base + 7);
  58. hw->io_ports.ctl_addr = Q40_ISA_IO_B(base + 0x206);
  59. hw->irq = irq;
  60. }
  61. static void q40ide_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
  62. void *buf, unsigned int len)
  63. {
  64. unsigned long data_addr = drive->hwif->io_ports.data_addr;
  65. if (drive->media == ide_disk && cmd && (cmd->tf_flags & IDE_TFLAG_FS)) {
  66. __ide_mm_insw(data_addr, buf, (len + 1) / 2);
  67. return;
  68. }
  69. raw_insw_swapw((u16 *)data_addr, buf, (len + 1) / 2);
  70. }
  71. static void q40ide_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
  72. void *buf, unsigned int len)
  73. {
  74. unsigned long data_addr = drive->hwif->io_ports.data_addr;
  75. if (drive->media == ide_disk && cmd && (cmd->tf_flags & IDE_TFLAG_FS)) {
  76. __ide_mm_outsw(data_addr, buf, (len + 1) / 2);
  77. return;
  78. }
  79. raw_outsw_swapw((u16 *)data_addr, buf, (len + 1) / 2);
  80. }
  81. /* Q40 has a byte-swapped IDE interface */
  82. static const struct ide_tp_ops q40ide_tp_ops = {
  83. .exec_command = ide_exec_command,
  84. .read_status = ide_read_status,
  85. .read_altstatus = ide_read_altstatus,
  86. .write_devctl = ide_write_devctl,
  87. .dev_select = ide_dev_select,
  88. .tf_load = ide_tf_load,
  89. .tf_read = ide_tf_read,
  90. .input_data = q40ide_input_data,
  91. .output_data = q40ide_output_data,
  92. };
  93. static const struct ide_port_info q40ide_port_info = {
  94. .tp_ops = &q40ide_tp_ops,
  95. .host_flags = IDE_HFLAG_MMIO | IDE_HFLAG_NO_DMA,
  96. .irq_flags = IRQF_SHARED,
  97. .chipset = ide_generic,
  98. };
  99. /*
  100. * the static array is needed to have the name reported in /proc/ioports,
  101. * hwif->name unfortunately isn't available yet
  102. */
  103. static const char *q40_ide_names[Q40IDE_NUM_HWIFS]={
  104. "ide0", "ide1"
  105. };
  106. /*
  107. * Probe for Q40 IDE interfaces
  108. */
  109. static int __init q40ide_init(void)
  110. {
  111. int i;
  112. struct ide_hw hw[Q40IDE_NUM_HWIFS], *hws[] = { NULL, NULL };
  113. if (!MACH_IS_Q40)
  114. return -ENODEV;
  115. printk(KERN_INFO "ide: Q40 IDE controller\n");
  116. for (i = 0; i < Q40IDE_NUM_HWIFS; i++) {
  117. const char *name = q40_ide_names[i];
  118. if (!request_region(pcide_bases[i], 8, name)) {
  119. printk("could not reserve ports %lx-%lx for %s\n",
  120. pcide_bases[i],pcide_bases[i]+8,name);
  121. continue;
  122. }
  123. if (!request_region(pcide_bases[i]+0x206, 1, name)) {
  124. printk("could not reserve port %lx for %s\n",
  125. pcide_bases[i]+0x206,name);
  126. release_region(pcide_bases[i], 8);
  127. continue;
  128. }
  129. q40_ide_setup_ports(&hw[i], pcide_bases[i],
  130. q40ide_default_irq(pcide_bases[i]));
  131. hws[i] = &hw[i];
  132. }
  133. return ide_host_add(&q40ide_port_info, hws, Q40IDE_NUM_HWIFS, NULL);
  134. }
  135. module_init(q40ide_init);
  136. MODULE_LICENSE("GPL");