ml_ioh_gpio.c 8.2 KB

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  1. /*
  2. * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; version 2 of the License.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/slab.h>
  19. #include <linux/pci.h>
  20. #include <linux/gpio.h>
  21. #define PCI_VENDOR_ID_ROHM 0x10DB
  22. struct ioh_reg_comn {
  23. u32 ien;
  24. u32 istatus;
  25. u32 idisp;
  26. u32 iclr;
  27. u32 imask;
  28. u32 imaskclr;
  29. u32 po;
  30. u32 pi;
  31. u32 pm;
  32. u32 im_0;
  33. u32 im_1;
  34. u32 reserved;
  35. };
  36. struct ioh_regs {
  37. struct ioh_reg_comn regs[8];
  38. u32 reserve1[16];
  39. u32 ioh_sel_reg[4];
  40. u32 reserve2[11];
  41. u32 srst;
  42. };
  43. /**
  44. * struct ioh_gpio_reg_data - The register store data.
  45. * @po_reg: To store contents of PO register.
  46. * @pm_reg: To store contents of PM register.
  47. */
  48. struct ioh_gpio_reg_data {
  49. u32 po_reg;
  50. u32 pm_reg;
  51. };
  52. /**
  53. * struct ioh_gpio - GPIO private data structure.
  54. * @base: PCI base address of Memory mapped I/O register.
  55. * @reg: Memory mapped IOH GPIO register list.
  56. * @dev: Pointer to device structure.
  57. * @gpio: Data for GPIO infrastructure.
  58. * @ioh_gpio_reg: Memory mapped Register data is saved here
  59. * when suspend.
  60. * @ch: Indicate GPIO channel
  61. */
  62. struct ioh_gpio {
  63. void __iomem *base;
  64. struct ioh_regs __iomem *reg;
  65. struct device *dev;
  66. struct gpio_chip gpio;
  67. struct ioh_gpio_reg_data ioh_gpio_reg;
  68. struct mutex lock;
  69. int ch;
  70. };
  71. static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
  72. static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
  73. {
  74. u32 reg_val;
  75. struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
  76. mutex_lock(&chip->lock);
  77. reg_val = ioread32(&chip->reg->regs[chip->ch].po);
  78. if (val)
  79. reg_val |= (1 << nr);
  80. else
  81. reg_val &= ~(1 << nr);
  82. iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
  83. mutex_unlock(&chip->lock);
  84. }
  85. static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
  86. {
  87. struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
  88. return ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr);
  89. }
  90. static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
  91. int val)
  92. {
  93. struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
  94. u32 pm;
  95. u32 reg_val;
  96. mutex_lock(&chip->lock);
  97. pm = ioread32(&chip->reg->regs[chip->ch].pm) &
  98. ((1 << num_ports[chip->ch]) - 1);
  99. pm |= (1 << nr);
  100. iowrite32(pm, &chip->reg->regs[chip->ch].pm);
  101. reg_val = ioread32(&chip->reg->regs[chip->ch].po);
  102. if (val)
  103. reg_val |= (1 << nr);
  104. else
  105. reg_val &= ~(1 << nr);
  106. iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
  107. mutex_unlock(&chip->lock);
  108. return 0;
  109. }
  110. static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
  111. {
  112. struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
  113. u32 pm;
  114. mutex_lock(&chip->lock);
  115. pm = ioread32(&chip->reg->regs[chip->ch].pm) &
  116. ((1 << num_ports[chip->ch]) - 1);
  117. pm &= ~(1 << nr);
  118. iowrite32(pm, &chip->reg->regs[chip->ch].pm);
  119. mutex_unlock(&chip->lock);
  120. return 0;
  121. }
  122. #ifdef CONFIG_PM
  123. /*
  124. * Save register configuration and disable interrupts.
  125. */
  126. static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
  127. {
  128. chip->ioh_gpio_reg.po_reg = ioread32(&chip->reg->regs[chip->ch].po);
  129. chip->ioh_gpio_reg.pm_reg = ioread32(&chip->reg->regs[chip->ch].pm);
  130. }
  131. /*
  132. * This function restores the register configuration of the GPIO device.
  133. */
  134. static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
  135. {
  136. /* to store contents of PO register */
  137. iowrite32(chip->ioh_gpio_reg.po_reg, &chip->reg->regs[chip->ch].po);
  138. /* to store contents of PM register */
  139. iowrite32(chip->ioh_gpio_reg.pm_reg, &chip->reg->regs[chip->ch].pm);
  140. }
  141. #endif
  142. static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
  143. {
  144. struct gpio_chip *gpio = &chip->gpio;
  145. gpio->label = dev_name(chip->dev);
  146. gpio->owner = THIS_MODULE;
  147. gpio->direction_input = ioh_gpio_direction_input;
  148. gpio->get = ioh_gpio_get;
  149. gpio->direction_output = ioh_gpio_direction_output;
  150. gpio->set = ioh_gpio_set;
  151. gpio->dbg_show = NULL;
  152. gpio->base = -1;
  153. gpio->ngpio = num_port;
  154. gpio->can_sleep = 0;
  155. }
  156. static int __devinit ioh_gpio_probe(struct pci_dev *pdev,
  157. const struct pci_device_id *id)
  158. {
  159. int ret;
  160. int i;
  161. struct ioh_gpio *chip;
  162. void __iomem *base;
  163. void __iomem *chip_save;
  164. ret = pci_enable_device(pdev);
  165. if (ret) {
  166. dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
  167. goto err_pci_enable;
  168. }
  169. ret = pci_request_regions(pdev, KBUILD_MODNAME);
  170. if (ret) {
  171. dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
  172. goto err_request_regions;
  173. }
  174. base = pci_iomap(pdev, 1, 0);
  175. if (base == 0) {
  176. dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
  177. ret = -ENOMEM;
  178. goto err_iomap;
  179. }
  180. chip_save = kzalloc(sizeof(*chip) * 8, GFP_KERNEL);
  181. if (chip_save == NULL) {
  182. dev_err(&pdev->dev, "%s : kzalloc failed", __func__);
  183. ret = -ENOMEM;
  184. goto err_kzalloc;
  185. }
  186. chip = chip_save;
  187. for (i = 0; i < 8; i++, chip++) {
  188. chip->dev = &pdev->dev;
  189. chip->base = base;
  190. chip->reg = chip->base;
  191. chip->ch = i;
  192. mutex_init(&chip->lock);
  193. ioh_gpio_setup(chip, num_ports[i]);
  194. ret = gpiochip_add(&chip->gpio);
  195. if (ret) {
  196. dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
  197. goto err_gpiochip_add;
  198. }
  199. }
  200. chip = chip_save;
  201. pci_set_drvdata(pdev, chip);
  202. return 0;
  203. err_gpiochip_add:
  204. for (; i != 0; i--) {
  205. chip--;
  206. ret = gpiochip_remove(&chip->gpio);
  207. if (ret)
  208. dev_err(&pdev->dev, "Failed gpiochip_remove(%d)\n", i);
  209. }
  210. kfree(chip_save);
  211. err_kzalloc:
  212. pci_iounmap(pdev, base);
  213. err_iomap:
  214. pci_release_regions(pdev);
  215. err_request_regions:
  216. pci_disable_device(pdev);
  217. err_pci_enable:
  218. dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
  219. return ret;
  220. }
  221. static void __devexit ioh_gpio_remove(struct pci_dev *pdev)
  222. {
  223. int err;
  224. int i;
  225. struct ioh_gpio *chip = pci_get_drvdata(pdev);
  226. void __iomem *chip_save;
  227. chip_save = chip;
  228. for (i = 0; i < 8; i++, chip++) {
  229. err = gpiochip_remove(&chip->gpio);
  230. if (err)
  231. dev_err(&pdev->dev, "Failed gpiochip_remove\n");
  232. }
  233. chip = chip_save;
  234. pci_iounmap(pdev, chip->base);
  235. pci_release_regions(pdev);
  236. pci_disable_device(pdev);
  237. kfree(chip);
  238. }
  239. #ifdef CONFIG_PM
  240. static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
  241. {
  242. s32 ret;
  243. struct ioh_gpio *chip = pci_get_drvdata(pdev);
  244. ioh_gpio_save_reg_conf(chip);
  245. ioh_gpio_restore_reg_conf(chip);
  246. ret = pci_save_state(pdev);
  247. if (ret) {
  248. dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
  249. return ret;
  250. }
  251. pci_disable_device(pdev);
  252. pci_set_power_state(pdev, PCI_D0);
  253. ret = pci_enable_wake(pdev, PCI_D0, 1);
  254. if (ret)
  255. dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
  256. return 0;
  257. }
  258. static int ioh_gpio_resume(struct pci_dev *pdev)
  259. {
  260. s32 ret;
  261. struct ioh_gpio *chip = pci_get_drvdata(pdev);
  262. ret = pci_enable_wake(pdev, PCI_D0, 0);
  263. pci_set_power_state(pdev, PCI_D0);
  264. ret = pci_enable_device(pdev);
  265. if (ret) {
  266. dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
  267. return ret;
  268. }
  269. pci_restore_state(pdev);
  270. iowrite32(0x01, &chip->reg->srst);
  271. iowrite32(0x00, &chip->reg->srst);
  272. ioh_gpio_restore_reg_conf(chip);
  273. return 0;
  274. }
  275. #else
  276. #define ioh_gpio_suspend NULL
  277. #define ioh_gpio_resume NULL
  278. #endif
  279. static DEFINE_PCI_DEVICE_TABLE(ioh_gpio_pcidev_id) = {
  280. { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
  281. { 0, }
  282. };
  283. MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
  284. static struct pci_driver ioh_gpio_driver = {
  285. .name = "ml_ioh_gpio",
  286. .id_table = ioh_gpio_pcidev_id,
  287. .probe = ioh_gpio_probe,
  288. .remove = __devexit_p(ioh_gpio_remove),
  289. .suspend = ioh_gpio_suspend,
  290. .resume = ioh_gpio_resume
  291. };
  292. static int __init ioh_gpio_pci_init(void)
  293. {
  294. return pci_register_driver(&ioh_gpio_driver);
  295. }
  296. module_init(ioh_gpio_pci_init);
  297. static void __exit ioh_gpio_pci_exit(void)
  298. {
  299. pci_unregister_driver(&ioh_gpio_driver);
  300. }
  301. module_exit(ioh_gpio_pci_exit);
  302. MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
  303. MODULE_LICENSE("GPL");