sh_mtu2.c 8.1 KB

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  1. /*
  2. * SuperH Timer Support - MTU2
  3. *
  4. * Copyright (C) 2009 Magnus Damm
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/init.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/ioport.h>
  24. #include <linux/delay.h>
  25. #include <linux/io.h>
  26. #include <linux/clk.h>
  27. #include <linux/irq.h>
  28. #include <linux/err.h>
  29. #include <linux/clockchips.h>
  30. #include <linux/sh_timer.h>
  31. #include <linux/slab.h>
  32. struct sh_mtu2_priv {
  33. void __iomem *mapbase;
  34. struct clk *clk;
  35. struct irqaction irqaction;
  36. struct platform_device *pdev;
  37. unsigned long rate;
  38. unsigned long periodic;
  39. struct clock_event_device ced;
  40. };
  41. static DEFINE_SPINLOCK(sh_mtu2_lock);
  42. #define TSTR -1 /* shared register */
  43. #define TCR 0 /* channel register */
  44. #define TMDR 1 /* channel register */
  45. #define TIOR 2 /* channel register */
  46. #define TIER 3 /* channel register */
  47. #define TSR 4 /* channel register */
  48. #define TCNT 5 /* channel register */
  49. #define TGR 6 /* channel register */
  50. static unsigned long mtu2_reg_offs[] = {
  51. [TCR] = 0,
  52. [TMDR] = 1,
  53. [TIOR] = 2,
  54. [TIER] = 4,
  55. [TSR] = 5,
  56. [TCNT] = 6,
  57. [TGR] = 8,
  58. };
  59. static inline unsigned long sh_mtu2_read(struct sh_mtu2_priv *p, int reg_nr)
  60. {
  61. struct sh_timer_config *cfg = p->pdev->dev.platform_data;
  62. void __iomem *base = p->mapbase;
  63. unsigned long offs;
  64. if (reg_nr == TSTR)
  65. return ioread8(base + cfg->channel_offset);
  66. offs = mtu2_reg_offs[reg_nr];
  67. if ((reg_nr == TCNT) || (reg_nr == TGR))
  68. return ioread16(base + offs);
  69. else
  70. return ioread8(base + offs);
  71. }
  72. static inline void sh_mtu2_write(struct sh_mtu2_priv *p, int reg_nr,
  73. unsigned long value)
  74. {
  75. struct sh_timer_config *cfg = p->pdev->dev.platform_data;
  76. void __iomem *base = p->mapbase;
  77. unsigned long offs;
  78. if (reg_nr == TSTR) {
  79. iowrite8(value, base + cfg->channel_offset);
  80. return;
  81. }
  82. offs = mtu2_reg_offs[reg_nr];
  83. if ((reg_nr == TCNT) || (reg_nr == TGR))
  84. iowrite16(value, base + offs);
  85. else
  86. iowrite8(value, base + offs);
  87. }
  88. static void sh_mtu2_start_stop_ch(struct sh_mtu2_priv *p, int start)
  89. {
  90. struct sh_timer_config *cfg = p->pdev->dev.platform_data;
  91. unsigned long flags, value;
  92. /* start stop register shared by multiple timer channels */
  93. spin_lock_irqsave(&sh_mtu2_lock, flags);
  94. value = sh_mtu2_read(p, TSTR);
  95. if (start)
  96. value |= 1 << cfg->timer_bit;
  97. else
  98. value &= ~(1 << cfg->timer_bit);
  99. sh_mtu2_write(p, TSTR, value);
  100. spin_unlock_irqrestore(&sh_mtu2_lock, flags);
  101. }
  102. static int sh_mtu2_enable(struct sh_mtu2_priv *p)
  103. {
  104. int ret;
  105. /* enable clock */
  106. ret = clk_enable(p->clk);
  107. if (ret) {
  108. dev_err(&p->pdev->dev, "cannot enable clock\n");
  109. return ret;
  110. }
  111. /* make sure channel is disabled */
  112. sh_mtu2_start_stop_ch(p, 0);
  113. p->rate = clk_get_rate(p->clk) / 64;
  114. p->periodic = (p->rate + HZ/2) / HZ;
  115. /* "Periodic Counter Operation" */
  116. sh_mtu2_write(p, TCR, 0x23); /* TGRA clear, divide clock by 64 */
  117. sh_mtu2_write(p, TIOR, 0);
  118. sh_mtu2_write(p, TGR, p->periodic);
  119. sh_mtu2_write(p, TCNT, 0);
  120. sh_mtu2_write(p, TMDR, 0);
  121. sh_mtu2_write(p, TIER, 0x01);
  122. /* enable channel */
  123. sh_mtu2_start_stop_ch(p, 1);
  124. return 0;
  125. }
  126. static void sh_mtu2_disable(struct sh_mtu2_priv *p)
  127. {
  128. /* disable channel */
  129. sh_mtu2_start_stop_ch(p, 0);
  130. /* stop clock */
  131. clk_disable(p->clk);
  132. }
  133. static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
  134. {
  135. struct sh_mtu2_priv *p = dev_id;
  136. /* acknowledge interrupt */
  137. sh_mtu2_read(p, TSR);
  138. sh_mtu2_write(p, TSR, 0xfe);
  139. /* notify clockevent layer */
  140. p->ced.event_handler(&p->ced);
  141. return IRQ_HANDLED;
  142. }
  143. static struct sh_mtu2_priv *ced_to_sh_mtu2(struct clock_event_device *ced)
  144. {
  145. return container_of(ced, struct sh_mtu2_priv, ced);
  146. }
  147. static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
  148. struct clock_event_device *ced)
  149. {
  150. struct sh_mtu2_priv *p = ced_to_sh_mtu2(ced);
  151. int disabled = 0;
  152. /* deal with old setting first */
  153. switch (ced->mode) {
  154. case CLOCK_EVT_MODE_PERIODIC:
  155. sh_mtu2_disable(p);
  156. disabled = 1;
  157. break;
  158. default:
  159. break;
  160. }
  161. switch (mode) {
  162. case CLOCK_EVT_MODE_PERIODIC:
  163. dev_info(&p->pdev->dev, "used for periodic clock events\n");
  164. sh_mtu2_enable(p);
  165. break;
  166. case CLOCK_EVT_MODE_UNUSED:
  167. if (!disabled)
  168. sh_mtu2_disable(p);
  169. break;
  170. case CLOCK_EVT_MODE_SHUTDOWN:
  171. default:
  172. break;
  173. }
  174. }
  175. static void sh_mtu2_register_clockevent(struct sh_mtu2_priv *p,
  176. char *name, unsigned long rating)
  177. {
  178. struct clock_event_device *ced = &p->ced;
  179. int ret;
  180. memset(ced, 0, sizeof(*ced));
  181. ced->name = name;
  182. ced->features = CLOCK_EVT_FEAT_PERIODIC;
  183. ced->rating = rating;
  184. ced->cpumask = cpumask_of(0);
  185. ced->set_mode = sh_mtu2_clock_event_mode;
  186. dev_info(&p->pdev->dev, "used for clock events\n");
  187. clockevents_register_device(ced);
  188. ret = setup_irq(p->irqaction.irq, &p->irqaction);
  189. if (ret) {
  190. dev_err(&p->pdev->dev, "failed to request irq %d\n",
  191. p->irqaction.irq);
  192. return;
  193. }
  194. }
  195. static int sh_mtu2_register(struct sh_mtu2_priv *p, char *name,
  196. unsigned long clockevent_rating)
  197. {
  198. if (clockevent_rating)
  199. sh_mtu2_register_clockevent(p, name, clockevent_rating);
  200. return 0;
  201. }
  202. static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
  203. {
  204. struct sh_timer_config *cfg = pdev->dev.platform_data;
  205. struct resource *res;
  206. int irq, ret;
  207. ret = -ENXIO;
  208. memset(p, 0, sizeof(*p));
  209. p->pdev = pdev;
  210. if (!cfg) {
  211. dev_err(&p->pdev->dev, "missing platform data\n");
  212. goto err0;
  213. }
  214. platform_set_drvdata(pdev, p);
  215. res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
  216. if (!res) {
  217. dev_err(&p->pdev->dev, "failed to get I/O memory\n");
  218. goto err0;
  219. }
  220. irq = platform_get_irq(p->pdev, 0);
  221. if (irq < 0) {
  222. dev_err(&p->pdev->dev, "failed to get irq\n");
  223. goto err0;
  224. }
  225. /* map memory, let mapbase point to our channel */
  226. p->mapbase = ioremap_nocache(res->start, resource_size(res));
  227. if (p->mapbase == NULL) {
  228. dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
  229. goto err0;
  230. }
  231. /* setup data for setup_irq() (too early for request_irq()) */
  232. p->irqaction.name = dev_name(&p->pdev->dev);
  233. p->irqaction.handler = sh_mtu2_interrupt;
  234. p->irqaction.dev_id = p;
  235. p->irqaction.irq = irq;
  236. p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
  237. IRQF_IRQPOLL | IRQF_NOBALANCING;
  238. /* get hold of clock */
  239. p->clk = clk_get(&p->pdev->dev, "mtu2_fck");
  240. if (IS_ERR(p->clk)) {
  241. dev_err(&p->pdev->dev, "cannot get clock\n");
  242. ret = PTR_ERR(p->clk);
  243. goto err1;
  244. }
  245. return sh_mtu2_register(p, (char *)dev_name(&p->pdev->dev),
  246. cfg->clockevent_rating);
  247. err1:
  248. iounmap(p->mapbase);
  249. err0:
  250. return ret;
  251. }
  252. static int __devinit sh_mtu2_probe(struct platform_device *pdev)
  253. {
  254. struct sh_mtu2_priv *p = platform_get_drvdata(pdev);
  255. int ret;
  256. if (p) {
  257. dev_info(&pdev->dev, "kept as earlytimer\n");
  258. return 0;
  259. }
  260. p = kmalloc(sizeof(*p), GFP_KERNEL);
  261. if (p == NULL) {
  262. dev_err(&pdev->dev, "failed to allocate driver data\n");
  263. return -ENOMEM;
  264. }
  265. ret = sh_mtu2_setup(p, pdev);
  266. if (ret) {
  267. kfree(p);
  268. platform_set_drvdata(pdev, NULL);
  269. }
  270. return ret;
  271. }
  272. static int __devexit sh_mtu2_remove(struct platform_device *pdev)
  273. {
  274. return -EBUSY; /* cannot unregister clockevent */
  275. }
  276. static struct platform_driver sh_mtu2_device_driver = {
  277. .probe = sh_mtu2_probe,
  278. .remove = __devexit_p(sh_mtu2_remove),
  279. .driver = {
  280. .name = "sh_mtu2",
  281. }
  282. };
  283. static int __init sh_mtu2_init(void)
  284. {
  285. return platform_driver_register(&sh_mtu2_device_driver);
  286. }
  287. static void __exit sh_mtu2_exit(void)
  288. {
  289. platform_driver_unregister(&sh_mtu2_device_driver);
  290. }
  291. early_platform_init("earlytimer", &sh_mtu2_device_driver);
  292. module_init(sh_mtu2_init);
  293. module_exit(sh_mtu2_exit);
  294. MODULE_AUTHOR("Magnus Damm");
  295. MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
  296. MODULE_LICENSE("GPL v2");