mbcs.c 20 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (c) 2005 Silicon Graphics, Inc. All rights reserved.
  7. */
  8. /*
  9. * MOATB Core Services driver.
  10. */
  11. #include <linux/interrupt.h>
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/types.h>
  15. #include <linux/ioport.h>
  16. #include <linux/kernel.h>
  17. #include <linux/notifier.h>
  18. #include <linux/reboot.h>
  19. #include <linux/init.h>
  20. #include <linux/fs.h>
  21. #include <linux/delay.h>
  22. #include <linux/device.h>
  23. #include <linux/mm.h>
  24. #include <linux/uio.h>
  25. #include <linux/mutex.h>
  26. #include <linux/slab.h>
  27. #include <asm/io.h>
  28. #include <asm/uaccess.h>
  29. #include <asm/system.h>
  30. #include <asm/pgtable.h>
  31. #include <asm/sn/addrs.h>
  32. #include <asm/sn/intr.h>
  33. #include <asm/sn/tiocx.h>
  34. #include "mbcs.h"
  35. #define MBCS_DEBUG 0
  36. #if MBCS_DEBUG
  37. #define DBG(fmt...) printk(KERN_ALERT fmt)
  38. #else
  39. #define DBG(fmt...)
  40. #endif
  41. static DEFINE_MUTEX(mbcs_mutex);
  42. static int mbcs_major;
  43. static LIST_HEAD(soft_list);
  44. /*
  45. * file operations
  46. */
  47. static const struct file_operations mbcs_ops = {
  48. .open = mbcs_open,
  49. .llseek = mbcs_sram_llseek,
  50. .read = mbcs_sram_read,
  51. .write = mbcs_sram_write,
  52. .mmap = mbcs_gscr_mmap,
  53. };
  54. struct mbcs_callback_arg {
  55. int minor;
  56. struct cx_dev *cx_dev;
  57. };
  58. static inline void mbcs_getdma_init(struct getdma *gdma)
  59. {
  60. memset(gdma, 0, sizeof(struct getdma));
  61. gdma->DoneIntEnable = 1;
  62. }
  63. static inline void mbcs_putdma_init(struct putdma *pdma)
  64. {
  65. memset(pdma, 0, sizeof(struct putdma));
  66. pdma->DoneIntEnable = 1;
  67. }
  68. static inline void mbcs_algo_init(struct algoblock *algo_soft)
  69. {
  70. memset(algo_soft, 0, sizeof(struct algoblock));
  71. }
  72. static inline void mbcs_getdma_set(void *mmr,
  73. uint64_t hostAddr,
  74. uint64_t localAddr,
  75. uint64_t localRamSel,
  76. uint64_t numPkts,
  77. uint64_t amoEnable,
  78. uint64_t intrEnable,
  79. uint64_t peerIO,
  80. uint64_t amoHostDest,
  81. uint64_t amoModType, uint64_t intrHostDest,
  82. uint64_t intrVector)
  83. {
  84. union dma_control rdma_control;
  85. union dma_amo_dest amo_dest;
  86. union intr_dest intr_dest;
  87. union dma_localaddr local_addr;
  88. union dma_hostaddr host_addr;
  89. rdma_control.dma_control_reg = 0;
  90. amo_dest.dma_amo_dest_reg = 0;
  91. intr_dest.intr_dest_reg = 0;
  92. local_addr.dma_localaddr_reg = 0;
  93. host_addr.dma_hostaddr_reg = 0;
  94. host_addr.dma_sys_addr = hostAddr;
  95. MBCS_MMR_SET(mmr, MBCS_RD_DMA_SYS_ADDR, host_addr.dma_hostaddr_reg);
  96. local_addr.dma_ram_addr = localAddr;
  97. local_addr.dma_ram_sel = localRamSel;
  98. MBCS_MMR_SET(mmr, MBCS_RD_DMA_LOC_ADDR, local_addr.dma_localaddr_reg);
  99. rdma_control.dma_op_length = numPkts;
  100. rdma_control.done_amo_en = amoEnable;
  101. rdma_control.done_int_en = intrEnable;
  102. rdma_control.pio_mem_n = peerIO;
  103. MBCS_MMR_SET(mmr, MBCS_RD_DMA_CTRL, rdma_control.dma_control_reg);
  104. amo_dest.dma_amo_sys_addr = amoHostDest;
  105. amo_dest.dma_amo_mod_type = amoModType;
  106. MBCS_MMR_SET(mmr, MBCS_RD_DMA_AMO_DEST, amo_dest.dma_amo_dest_reg);
  107. intr_dest.address = intrHostDest;
  108. intr_dest.int_vector = intrVector;
  109. MBCS_MMR_SET(mmr, MBCS_RD_DMA_INT_DEST, intr_dest.intr_dest_reg);
  110. }
  111. static inline void mbcs_putdma_set(void *mmr,
  112. uint64_t hostAddr,
  113. uint64_t localAddr,
  114. uint64_t localRamSel,
  115. uint64_t numPkts,
  116. uint64_t amoEnable,
  117. uint64_t intrEnable,
  118. uint64_t peerIO,
  119. uint64_t amoHostDest,
  120. uint64_t amoModType,
  121. uint64_t intrHostDest, uint64_t intrVector)
  122. {
  123. union dma_control wdma_control;
  124. union dma_amo_dest amo_dest;
  125. union intr_dest intr_dest;
  126. union dma_localaddr local_addr;
  127. union dma_hostaddr host_addr;
  128. wdma_control.dma_control_reg = 0;
  129. amo_dest.dma_amo_dest_reg = 0;
  130. intr_dest.intr_dest_reg = 0;
  131. local_addr.dma_localaddr_reg = 0;
  132. host_addr.dma_hostaddr_reg = 0;
  133. host_addr.dma_sys_addr = hostAddr;
  134. MBCS_MMR_SET(mmr, MBCS_WR_DMA_SYS_ADDR, host_addr.dma_hostaddr_reg);
  135. local_addr.dma_ram_addr = localAddr;
  136. local_addr.dma_ram_sel = localRamSel;
  137. MBCS_MMR_SET(mmr, MBCS_WR_DMA_LOC_ADDR, local_addr.dma_localaddr_reg);
  138. wdma_control.dma_op_length = numPkts;
  139. wdma_control.done_amo_en = amoEnable;
  140. wdma_control.done_int_en = intrEnable;
  141. wdma_control.pio_mem_n = peerIO;
  142. MBCS_MMR_SET(mmr, MBCS_WR_DMA_CTRL, wdma_control.dma_control_reg);
  143. amo_dest.dma_amo_sys_addr = amoHostDest;
  144. amo_dest.dma_amo_mod_type = amoModType;
  145. MBCS_MMR_SET(mmr, MBCS_WR_DMA_AMO_DEST, amo_dest.dma_amo_dest_reg);
  146. intr_dest.address = intrHostDest;
  147. intr_dest.int_vector = intrVector;
  148. MBCS_MMR_SET(mmr, MBCS_WR_DMA_INT_DEST, intr_dest.intr_dest_reg);
  149. }
  150. static inline void mbcs_algo_set(void *mmr,
  151. uint64_t amoHostDest,
  152. uint64_t amoModType,
  153. uint64_t intrHostDest,
  154. uint64_t intrVector, uint64_t algoStepCount)
  155. {
  156. union dma_amo_dest amo_dest;
  157. union intr_dest intr_dest;
  158. union algo_step step;
  159. step.algo_step_reg = 0;
  160. intr_dest.intr_dest_reg = 0;
  161. amo_dest.dma_amo_dest_reg = 0;
  162. amo_dest.dma_amo_sys_addr = amoHostDest;
  163. amo_dest.dma_amo_mod_type = amoModType;
  164. MBCS_MMR_SET(mmr, MBCS_ALG_AMO_DEST, amo_dest.dma_amo_dest_reg);
  165. intr_dest.address = intrHostDest;
  166. intr_dest.int_vector = intrVector;
  167. MBCS_MMR_SET(mmr, MBCS_ALG_INT_DEST, intr_dest.intr_dest_reg);
  168. step.alg_step_cnt = algoStepCount;
  169. MBCS_MMR_SET(mmr, MBCS_ALG_STEP, step.algo_step_reg);
  170. }
  171. static inline int mbcs_getdma_start(struct mbcs_soft *soft)
  172. {
  173. void *mmr_base;
  174. struct getdma *gdma;
  175. uint64_t numPkts;
  176. union cm_control cm_control;
  177. mmr_base = soft->mmr_base;
  178. gdma = &soft->getdma;
  179. /* check that host address got setup */
  180. if (!gdma->hostAddr)
  181. return -1;
  182. numPkts =
  183. (gdma->bytes + (MBCS_CACHELINE_SIZE - 1)) / MBCS_CACHELINE_SIZE;
  184. /* program engine */
  185. mbcs_getdma_set(mmr_base, tiocx_dma_addr(gdma->hostAddr),
  186. gdma->localAddr,
  187. (gdma->localAddr < MB2) ? 0 :
  188. (gdma->localAddr < MB4) ? 1 :
  189. (gdma->localAddr < MB6) ? 2 : 3,
  190. numPkts,
  191. gdma->DoneAmoEnable,
  192. gdma->DoneIntEnable,
  193. gdma->peerIO,
  194. gdma->amoHostDest,
  195. gdma->amoModType,
  196. gdma->intrHostDest, gdma->intrVector);
  197. /* start engine */
  198. cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
  199. cm_control.rd_dma_go = 1;
  200. MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
  201. return 0;
  202. }
  203. static inline int mbcs_putdma_start(struct mbcs_soft *soft)
  204. {
  205. void *mmr_base;
  206. struct putdma *pdma;
  207. uint64_t numPkts;
  208. union cm_control cm_control;
  209. mmr_base = soft->mmr_base;
  210. pdma = &soft->putdma;
  211. /* check that host address got setup */
  212. if (!pdma->hostAddr)
  213. return -1;
  214. numPkts =
  215. (pdma->bytes + (MBCS_CACHELINE_SIZE - 1)) / MBCS_CACHELINE_SIZE;
  216. /* program engine */
  217. mbcs_putdma_set(mmr_base, tiocx_dma_addr(pdma->hostAddr),
  218. pdma->localAddr,
  219. (pdma->localAddr < MB2) ? 0 :
  220. (pdma->localAddr < MB4) ? 1 :
  221. (pdma->localAddr < MB6) ? 2 : 3,
  222. numPkts,
  223. pdma->DoneAmoEnable,
  224. pdma->DoneIntEnable,
  225. pdma->peerIO,
  226. pdma->amoHostDest,
  227. pdma->amoModType,
  228. pdma->intrHostDest, pdma->intrVector);
  229. /* start engine */
  230. cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
  231. cm_control.wr_dma_go = 1;
  232. MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
  233. return 0;
  234. }
  235. static inline int mbcs_algo_start(struct mbcs_soft *soft)
  236. {
  237. struct algoblock *algo_soft = &soft->algo;
  238. void *mmr_base = soft->mmr_base;
  239. union cm_control cm_control;
  240. if (mutex_lock_interruptible(&soft->algolock))
  241. return -ERESTARTSYS;
  242. atomic_set(&soft->algo_done, 0);
  243. mbcs_algo_set(mmr_base,
  244. algo_soft->amoHostDest,
  245. algo_soft->amoModType,
  246. algo_soft->intrHostDest,
  247. algo_soft->intrVector, algo_soft->algoStepCount);
  248. /* start algorithm */
  249. cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
  250. cm_control.alg_done_int_en = 1;
  251. cm_control.alg_go = 1;
  252. MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
  253. mutex_unlock(&soft->algolock);
  254. return 0;
  255. }
  256. static inline ssize_t
  257. do_mbcs_sram_dmawrite(struct mbcs_soft *soft, uint64_t hostAddr,
  258. size_t len, loff_t * off)
  259. {
  260. int rv = 0;
  261. if (mutex_lock_interruptible(&soft->dmawritelock))
  262. return -ERESTARTSYS;
  263. atomic_set(&soft->dmawrite_done, 0);
  264. soft->putdma.hostAddr = hostAddr;
  265. soft->putdma.localAddr = *off;
  266. soft->putdma.bytes = len;
  267. if (mbcs_putdma_start(soft) < 0) {
  268. DBG(KERN_ALERT "do_mbcs_sram_dmawrite: "
  269. "mbcs_putdma_start failed\n");
  270. rv = -EAGAIN;
  271. goto dmawrite_exit;
  272. }
  273. if (wait_event_interruptible(soft->dmawrite_queue,
  274. atomic_read(&soft->dmawrite_done))) {
  275. rv = -ERESTARTSYS;
  276. goto dmawrite_exit;
  277. }
  278. rv = len;
  279. *off += len;
  280. dmawrite_exit:
  281. mutex_unlock(&soft->dmawritelock);
  282. return rv;
  283. }
  284. static inline ssize_t
  285. do_mbcs_sram_dmaread(struct mbcs_soft *soft, uint64_t hostAddr,
  286. size_t len, loff_t * off)
  287. {
  288. int rv = 0;
  289. if (mutex_lock_interruptible(&soft->dmareadlock))
  290. return -ERESTARTSYS;
  291. atomic_set(&soft->dmawrite_done, 0);
  292. soft->getdma.hostAddr = hostAddr;
  293. soft->getdma.localAddr = *off;
  294. soft->getdma.bytes = len;
  295. if (mbcs_getdma_start(soft) < 0) {
  296. DBG(KERN_ALERT "mbcs_strategy: mbcs_getdma_start failed\n");
  297. rv = -EAGAIN;
  298. goto dmaread_exit;
  299. }
  300. if (wait_event_interruptible(soft->dmaread_queue,
  301. atomic_read(&soft->dmaread_done))) {
  302. rv = -ERESTARTSYS;
  303. goto dmaread_exit;
  304. }
  305. rv = len;
  306. *off += len;
  307. dmaread_exit:
  308. mutex_unlock(&soft->dmareadlock);
  309. return rv;
  310. }
  311. static int mbcs_open(struct inode *ip, struct file *fp)
  312. {
  313. struct mbcs_soft *soft;
  314. int minor;
  315. mutex_lock(&mbcs_mutex);
  316. minor = iminor(ip);
  317. /* Nothing protects access to this list... */
  318. list_for_each_entry(soft, &soft_list, list) {
  319. if (soft->nasid == minor) {
  320. fp->private_data = soft->cxdev;
  321. mutex_unlock(&mbcs_mutex);
  322. return 0;
  323. }
  324. }
  325. mutex_unlock(&mbcs_mutex);
  326. return -ENODEV;
  327. }
  328. static ssize_t mbcs_sram_read(struct file * fp, char __user *buf, size_t len, loff_t * off)
  329. {
  330. struct cx_dev *cx_dev = fp->private_data;
  331. struct mbcs_soft *soft = cx_dev->soft;
  332. uint64_t hostAddr;
  333. int rv = 0;
  334. hostAddr = __get_dma_pages(GFP_KERNEL, get_order(len));
  335. if (hostAddr == 0)
  336. return -ENOMEM;
  337. rv = do_mbcs_sram_dmawrite(soft, hostAddr, len, off);
  338. if (rv < 0)
  339. goto exit;
  340. if (copy_to_user(buf, (void *)hostAddr, len))
  341. rv = -EFAULT;
  342. exit:
  343. free_pages(hostAddr, get_order(len));
  344. return rv;
  345. }
  346. static ssize_t
  347. mbcs_sram_write(struct file * fp, const char __user *buf, size_t len, loff_t * off)
  348. {
  349. struct cx_dev *cx_dev = fp->private_data;
  350. struct mbcs_soft *soft = cx_dev->soft;
  351. uint64_t hostAddr;
  352. int rv = 0;
  353. hostAddr = __get_dma_pages(GFP_KERNEL, get_order(len));
  354. if (hostAddr == 0)
  355. return -ENOMEM;
  356. if (copy_from_user((void *)hostAddr, buf, len)) {
  357. rv = -EFAULT;
  358. goto exit;
  359. }
  360. rv = do_mbcs_sram_dmaread(soft, hostAddr, len, off);
  361. exit:
  362. free_pages(hostAddr, get_order(len));
  363. return rv;
  364. }
  365. static loff_t mbcs_sram_llseek(struct file * filp, loff_t off, int whence)
  366. {
  367. loff_t newpos;
  368. switch (whence) {
  369. case SEEK_SET:
  370. newpos = off;
  371. break;
  372. case SEEK_CUR:
  373. newpos = filp->f_pos + off;
  374. break;
  375. case SEEK_END:
  376. newpos = MBCS_SRAM_SIZE + off;
  377. break;
  378. default: /* can't happen */
  379. return -EINVAL;
  380. }
  381. if (newpos < 0)
  382. return -EINVAL;
  383. filp->f_pos = newpos;
  384. return newpos;
  385. }
  386. static uint64_t mbcs_pioaddr(struct mbcs_soft *soft, uint64_t offset)
  387. {
  388. uint64_t mmr_base;
  389. mmr_base = (uint64_t) (soft->mmr_base + offset);
  390. return mmr_base;
  391. }
  392. static void mbcs_debug_pioaddr_set(struct mbcs_soft *soft)
  393. {
  394. soft->debug_addr = mbcs_pioaddr(soft, MBCS_DEBUG_START);
  395. }
  396. static void mbcs_gscr_pioaddr_set(struct mbcs_soft *soft)
  397. {
  398. soft->gscr_addr = mbcs_pioaddr(soft, MBCS_GSCR_START);
  399. }
  400. static int mbcs_gscr_mmap(struct file *fp, struct vm_area_struct *vma)
  401. {
  402. struct cx_dev *cx_dev = fp->private_data;
  403. struct mbcs_soft *soft = cx_dev->soft;
  404. if (vma->vm_pgoff != 0)
  405. return -EINVAL;
  406. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  407. /* Remap-pfn-range will mark the range VM_IO and VM_RESERVED */
  408. if (remap_pfn_range(vma,
  409. vma->vm_start,
  410. __pa(soft->gscr_addr) >> PAGE_SHIFT,
  411. PAGE_SIZE,
  412. vma->vm_page_prot))
  413. return -EAGAIN;
  414. return 0;
  415. }
  416. /**
  417. * mbcs_completion_intr_handler - Primary completion handler.
  418. * @irq: irq
  419. * @arg: soft struct for device
  420. *
  421. */
  422. static irqreturn_t
  423. mbcs_completion_intr_handler(int irq, void *arg)
  424. {
  425. struct mbcs_soft *soft = (struct mbcs_soft *)arg;
  426. void *mmr_base;
  427. union cm_status cm_status;
  428. union cm_control cm_control;
  429. mmr_base = soft->mmr_base;
  430. cm_status.cm_status_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_STATUS);
  431. if (cm_status.rd_dma_done) {
  432. /* stop dma-read engine, clear status */
  433. cm_control.cm_control_reg =
  434. MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
  435. cm_control.rd_dma_clr = 1;
  436. MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL,
  437. cm_control.cm_control_reg);
  438. atomic_set(&soft->dmaread_done, 1);
  439. wake_up(&soft->dmaread_queue);
  440. }
  441. if (cm_status.wr_dma_done) {
  442. /* stop dma-write engine, clear status */
  443. cm_control.cm_control_reg =
  444. MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
  445. cm_control.wr_dma_clr = 1;
  446. MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL,
  447. cm_control.cm_control_reg);
  448. atomic_set(&soft->dmawrite_done, 1);
  449. wake_up(&soft->dmawrite_queue);
  450. }
  451. if (cm_status.alg_done) {
  452. /* clear status */
  453. cm_control.cm_control_reg =
  454. MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
  455. cm_control.alg_done_clr = 1;
  456. MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL,
  457. cm_control.cm_control_reg);
  458. atomic_set(&soft->algo_done, 1);
  459. wake_up(&soft->algo_queue);
  460. }
  461. return IRQ_HANDLED;
  462. }
  463. /**
  464. * mbcs_intr_alloc - Allocate interrupts.
  465. * @dev: device pointer
  466. *
  467. */
  468. static int mbcs_intr_alloc(struct cx_dev *dev)
  469. {
  470. struct sn_irq_info *sn_irq;
  471. struct mbcs_soft *soft;
  472. struct getdma *getdma;
  473. struct putdma *putdma;
  474. struct algoblock *algo;
  475. soft = dev->soft;
  476. getdma = &soft->getdma;
  477. putdma = &soft->putdma;
  478. algo = &soft->algo;
  479. soft->get_sn_irq = NULL;
  480. soft->put_sn_irq = NULL;
  481. soft->algo_sn_irq = NULL;
  482. sn_irq = tiocx_irq_alloc(dev->cx_id.nasid, TIOCX_CORELET, -1, -1, -1);
  483. if (sn_irq == NULL)
  484. return -EAGAIN;
  485. soft->get_sn_irq = sn_irq;
  486. getdma->intrHostDest = sn_irq->irq_xtalkaddr;
  487. getdma->intrVector = sn_irq->irq_irq;
  488. if (request_irq(sn_irq->irq_irq,
  489. (void *)mbcs_completion_intr_handler, IRQF_SHARED,
  490. "MBCS get intr", (void *)soft)) {
  491. tiocx_irq_free(soft->get_sn_irq);
  492. return -EAGAIN;
  493. }
  494. sn_irq = tiocx_irq_alloc(dev->cx_id.nasid, TIOCX_CORELET, -1, -1, -1);
  495. if (sn_irq == NULL) {
  496. free_irq(soft->get_sn_irq->irq_irq, soft);
  497. tiocx_irq_free(soft->get_sn_irq);
  498. return -EAGAIN;
  499. }
  500. soft->put_sn_irq = sn_irq;
  501. putdma->intrHostDest = sn_irq->irq_xtalkaddr;
  502. putdma->intrVector = sn_irq->irq_irq;
  503. if (request_irq(sn_irq->irq_irq,
  504. (void *)mbcs_completion_intr_handler, IRQF_SHARED,
  505. "MBCS put intr", (void *)soft)) {
  506. tiocx_irq_free(soft->put_sn_irq);
  507. free_irq(soft->get_sn_irq->irq_irq, soft);
  508. tiocx_irq_free(soft->get_sn_irq);
  509. return -EAGAIN;
  510. }
  511. sn_irq = tiocx_irq_alloc(dev->cx_id.nasid, TIOCX_CORELET, -1, -1, -1);
  512. if (sn_irq == NULL) {
  513. free_irq(soft->put_sn_irq->irq_irq, soft);
  514. tiocx_irq_free(soft->put_sn_irq);
  515. free_irq(soft->get_sn_irq->irq_irq, soft);
  516. tiocx_irq_free(soft->get_sn_irq);
  517. return -EAGAIN;
  518. }
  519. soft->algo_sn_irq = sn_irq;
  520. algo->intrHostDest = sn_irq->irq_xtalkaddr;
  521. algo->intrVector = sn_irq->irq_irq;
  522. if (request_irq(sn_irq->irq_irq,
  523. (void *)mbcs_completion_intr_handler, IRQF_SHARED,
  524. "MBCS algo intr", (void *)soft)) {
  525. tiocx_irq_free(soft->algo_sn_irq);
  526. free_irq(soft->put_sn_irq->irq_irq, soft);
  527. tiocx_irq_free(soft->put_sn_irq);
  528. free_irq(soft->get_sn_irq->irq_irq, soft);
  529. tiocx_irq_free(soft->get_sn_irq);
  530. return -EAGAIN;
  531. }
  532. return 0;
  533. }
  534. /**
  535. * mbcs_intr_dealloc - Remove interrupts.
  536. * @dev: device pointer
  537. *
  538. */
  539. static void mbcs_intr_dealloc(struct cx_dev *dev)
  540. {
  541. struct mbcs_soft *soft;
  542. soft = dev->soft;
  543. free_irq(soft->get_sn_irq->irq_irq, soft);
  544. tiocx_irq_free(soft->get_sn_irq);
  545. free_irq(soft->put_sn_irq->irq_irq, soft);
  546. tiocx_irq_free(soft->put_sn_irq);
  547. free_irq(soft->algo_sn_irq->irq_irq, soft);
  548. tiocx_irq_free(soft->algo_sn_irq);
  549. }
  550. static inline int mbcs_hw_init(struct mbcs_soft *soft)
  551. {
  552. void *mmr_base = soft->mmr_base;
  553. union cm_control cm_control;
  554. union cm_req_timeout cm_req_timeout;
  555. uint64_t err_stat;
  556. cm_req_timeout.cm_req_timeout_reg =
  557. MBCS_MMR_GET(mmr_base, MBCS_CM_REQ_TOUT);
  558. cm_req_timeout.time_out = MBCS_CM_CONTROL_REQ_TOUT_MASK;
  559. MBCS_MMR_SET(mmr_base, MBCS_CM_REQ_TOUT,
  560. cm_req_timeout.cm_req_timeout_reg);
  561. mbcs_gscr_pioaddr_set(soft);
  562. mbcs_debug_pioaddr_set(soft);
  563. /* clear errors */
  564. err_stat = MBCS_MMR_GET(mmr_base, MBCS_CM_ERR_STAT);
  565. MBCS_MMR_SET(mmr_base, MBCS_CM_CLR_ERR_STAT, err_stat);
  566. MBCS_MMR_ZERO(mmr_base, MBCS_CM_ERROR_DETAIL1);
  567. /* enable interrupts */
  568. /* turn off 2^23 (INT_EN_PIO_REQ_ADDR_INV) */
  569. MBCS_MMR_SET(mmr_base, MBCS_CM_ERR_INT_EN, 0x3ffffff7e00ffUL);
  570. /* arm status regs and clear engines */
  571. cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
  572. cm_control.rearm_stat_regs = 1;
  573. cm_control.alg_clr = 1;
  574. cm_control.wr_dma_clr = 1;
  575. cm_control.rd_dma_clr = 1;
  576. MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
  577. return 0;
  578. }
  579. static ssize_t show_algo(struct device *dev, struct device_attribute *attr, char *buf)
  580. {
  581. struct cx_dev *cx_dev = to_cx_dev(dev);
  582. struct mbcs_soft *soft = cx_dev->soft;
  583. uint64_t debug0;
  584. /*
  585. * By convention, the first debug register contains the
  586. * algorithm number and revision.
  587. */
  588. debug0 = *(uint64_t *) soft->debug_addr;
  589. return sprintf(buf, "0x%x 0x%x\n",
  590. upper_32_bits(debug0), lower_32_bits(debug0));
  591. }
  592. static ssize_t store_algo(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
  593. {
  594. int n;
  595. struct cx_dev *cx_dev = to_cx_dev(dev);
  596. struct mbcs_soft *soft = cx_dev->soft;
  597. if (count <= 0)
  598. return 0;
  599. n = simple_strtoul(buf, NULL, 0);
  600. if (n == 1) {
  601. mbcs_algo_start(soft);
  602. if (wait_event_interruptible(soft->algo_queue,
  603. atomic_read(&soft->algo_done)))
  604. return -ERESTARTSYS;
  605. }
  606. return count;
  607. }
  608. DEVICE_ATTR(algo, 0644, show_algo, store_algo);
  609. /**
  610. * mbcs_probe - Initialize for device
  611. * @dev: device pointer
  612. * @device_id: id table pointer
  613. *
  614. */
  615. static int mbcs_probe(struct cx_dev *dev, const struct cx_device_id *id)
  616. {
  617. struct mbcs_soft *soft;
  618. dev->soft = NULL;
  619. soft = kzalloc(sizeof(struct mbcs_soft), GFP_KERNEL);
  620. if (soft == NULL)
  621. return -ENOMEM;
  622. soft->nasid = dev->cx_id.nasid;
  623. list_add(&soft->list, &soft_list);
  624. soft->mmr_base = (void *)tiocx_swin_base(dev->cx_id.nasid);
  625. dev->soft = soft;
  626. soft->cxdev = dev;
  627. init_waitqueue_head(&soft->dmawrite_queue);
  628. init_waitqueue_head(&soft->dmaread_queue);
  629. init_waitqueue_head(&soft->algo_queue);
  630. mutex_init(&soft->dmawritelock);
  631. mutex_init(&soft->dmareadlock);
  632. mutex_init(&soft->algolock);
  633. mbcs_getdma_init(&soft->getdma);
  634. mbcs_putdma_init(&soft->putdma);
  635. mbcs_algo_init(&soft->algo);
  636. mbcs_hw_init(soft);
  637. /* Allocate interrupts */
  638. mbcs_intr_alloc(dev);
  639. device_create_file(&dev->dev, &dev_attr_algo);
  640. return 0;
  641. }
  642. static int mbcs_remove(struct cx_dev *dev)
  643. {
  644. if (dev->soft) {
  645. mbcs_intr_dealloc(dev);
  646. kfree(dev->soft);
  647. }
  648. device_remove_file(&dev->dev, &dev_attr_algo);
  649. return 0;
  650. }
  651. static const struct cx_device_id __devinitdata mbcs_id_table[] = {
  652. {
  653. .part_num = MBCS_PART_NUM,
  654. .mfg_num = MBCS_MFG_NUM,
  655. },
  656. {
  657. .part_num = MBCS_PART_NUM_ALG0,
  658. .mfg_num = MBCS_MFG_NUM,
  659. },
  660. {0, 0}
  661. };
  662. MODULE_DEVICE_TABLE(cx, mbcs_id_table);
  663. static struct cx_drv mbcs_driver = {
  664. .name = DEVICE_NAME,
  665. .id_table = mbcs_id_table,
  666. .probe = mbcs_probe,
  667. .remove = mbcs_remove,
  668. };
  669. static void __exit mbcs_exit(void)
  670. {
  671. unregister_chrdev(mbcs_major, DEVICE_NAME);
  672. cx_driver_unregister(&mbcs_driver);
  673. }
  674. static int __init mbcs_init(void)
  675. {
  676. int rv;
  677. if (!ia64_platform_is("sn2"))
  678. return -ENODEV;
  679. // Put driver into chrdevs[]. Get major number.
  680. rv = register_chrdev(mbcs_major, DEVICE_NAME, &mbcs_ops);
  681. if (rv < 0) {
  682. DBG(KERN_ALERT "mbcs_init: can't get major number. %d\n", rv);
  683. return rv;
  684. }
  685. mbcs_major = rv;
  686. return cx_driver_register(&mbcs_driver);
  687. }
  688. module_init(mbcs_init);
  689. module_exit(mbcs_exit);
  690. MODULE_AUTHOR("Bruce Losure <blosure@sgi.com>");
  691. MODULE_DESCRIPTION("Driver for MOATB Core Services");
  692. MODULE_LICENSE("GPL");