pata_at91.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474
  1. /*
  2. * PATA driver for AT91SAM9260 Static Memory Controller
  3. * with CompactFlash interface in True IDE mode
  4. *
  5. * Copyright (C) 2009 Matyukevich Sergey
  6. * 2011 Igor Plyatov
  7. *
  8. * Based on:
  9. * * generic platform driver by Paul Mundt: drivers/ata/pata_platform.c
  10. * * pata_at32 driver by Kristoffer Nyborg Gregertsen
  11. * * at91_ide driver by Stanislaw Gruszka
  12. *
  13. * This program is free software; you can redistribute it and/or modify it
  14. * under the terms of the GNU General Public License version 2
  15. * as published by the Free Software Foundation.
  16. *
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/init.h>
  21. #include <linux/blkdev.h>
  22. #include <linux/gfp.h>
  23. #include <scsi/scsi_host.h>
  24. #include <linux/ata.h>
  25. #include <linux/clk.h>
  26. #include <linux/libata.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/ata_platform.h>
  29. #include <mach/at91sam9_smc.h>
  30. #include <mach/board.h>
  31. #include <mach/gpio.h>
  32. #define DRV_NAME "pata_at91"
  33. #define DRV_VERSION "0.3"
  34. #define CF_IDE_OFFSET 0x00c00000
  35. #define CF_ALT_IDE_OFFSET 0x00e00000
  36. #define CF_IDE_RES_SIZE 0x08
  37. #define CS_PULSE_MAXIMUM 319
  38. #define ER_SMC_CALC 1
  39. #define ER_SMC_RECALC 2
  40. struct at91_ide_info {
  41. unsigned long mode;
  42. unsigned int cs;
  43. struct clk *mck;
  44. void __iomem *ide_addr;
  45. void __iomem *alt_addr;
  46. };
  47. /**
  48. * struct smc_range - range of valid values for SMC register.
  49. */
  50. struct smc_range {
  51. int min;
  52. int max;
  53. };
  54. /**
  55. * adjust_smc_value - adjust value for one of SMC registers.
  56. * @value: adjusted value
  57. * @range: array of SMC ranges with valid values
  58. * @size: SMC ranges array size
  59. *
  60. * This returns the difference between input and output value or negative
  61. * in case of invalid input value.
  62. * If negative returned, then output value = maximal possible from ranges.
  63. */
  64. static int adjust_smc_value(int *value, struct smc_range *range, int size)
  65. {
  66. int maximum = (range + size - 1)->max;
  67. int remainder;
  68. do {
  69. if (*value < range->min) {
  70. remainder = range->min - *value;
  71. *value = range->min; /* nearest valid value */
  72. return remainder;
  73. } else if ((range->min <= *value) && (*value <= range->max))
  74. return 0;
  75. range++;
  76. } while (--size);
  77. *value = maximum;
  78. return -1; /* invalid value */
  79. }
  80. /**
  81. * calc_smc_vals - calculate SMC register values
  82. * @dev: ATA device
  83. * @setup: SMC_SETUP register value
  84. * @pulse: SMC_PULSE register value
  85. * @cycle: SMC_CYCLE register value
  86. *
  87. * This returns negative in case of invalid values for SMC registers:
  88. * -ER_SMC_RECALC - recalculation required for SMC values,
  89. * -ER_SMC_CALC - calculation failed (invalid input values).
  90. *
  91. * SMC use special coding scheme, see "Coding and Range of Timing
  92. * Parameters" table from AT91SAM9 datasheets.
  93. *
  94. * SMC_SETUP = 128*setup[5] + setup[4:0]
  95. * SMC_PULSE = 256*pulse[6] + pulse[5:0]
  96. * SMC_CYCLE = 256*cycle[8:7] + cycle[6:0]
  97. */
  98. static int calc_smc_vals(struct device *dev,
  99. int *setup, int *pulse, int *cycle, int *cs_pulse)
  100. {
  101. int ret_val;
  102. int err = 0;
  103. struct smc_range range_setup[] = { /* SMC_SETUP valid values */
  104. {.min = 0, .max = 31}, /* first range */
  105. {.min = 128, .max = 159} /* second range */
  106. };
  107. struct smc_range range_pulse[] = { /* SMC_PULSE valid values */
  108. {.min = 0, .max = 63}, /* first range */
  109. {.min = 256, .max = 319} /* second range */
  110. };
  111. struct smc_range range_cycle[] = { /* SMC_CYCLE valid values */
  112. {.min = 0, .max = 127}, /* first range */
  113. {.min = 256, .max = 383}, /* second range */
  114. {.min = 512, .max = 639}, /* third range */
  115. {.min = 768, .max = 895} /* fourth range */
  116. };
  117. ret_val = adjust_smc_value(setup, range_setup, ARRAY_SIZE(range_setup));
  118. if (ret_val < 0)
  119. dev_warn(dev, "maximal SMC Setup value\n");
  120. else
  121. *cycle += ret_val;
  122. ret_val = adjust_smc_value(pulse, range_pulse, ARRAY_SIZE(range_pulse));
  123. if (ret_val < 0)
  124. dev_warn(dev, "maximal SMC Pulse value\n");
  125. else
  126. *cycle += ret_val;
  127. ret_val = adjust_smc_value(cycle, range_cycle, ARRAY_SIZE(range_cycle));
  128. if (ret_val < 0)
  129. dev_warn(dev, "maximal SMC Cycle value\n");
  130. *cs_pulse = *cycle;
  131. if (*cs_pulse > CS_PULSE_MAXIMUM) {
  132. dev_err(dev, "unable to calculate valid SMC settings\n");
  133. return -ER_SMC_CALC;
  134. }
  135. ret_val = adjust_smc_value(cs_pulse, range_pulse,
  136. ARRAY_SIZE(range_pulse));
  137. if (ret_val < 0) {
  138. dev_warn(dev, "maximal SMC CS Pulse value\n");
  139. } else if (ret_val != 0) {
  140. *cycle = *cs_pulse;
  141. dev_warn(dev, "SMC Cycle extended\n");
  142. err = -ER_SMC_RECALC;
  143. }
  144. return err;
  145. }
  146. /**
  147. * to_smc_format - convert values into SMC format
  148. * @setup: SETUP value of SMC Setup Register
  149. * @pulse: PULSE value of SMC Pulse Register
  150. * @cycle: CYCLE value of SMC Cycle Register
  151. * @cs_pulse: NCS_PULSE value of SMC Pulse Register
  152. */
  153. static void to_smc_format(int *setup, int *pulse, int *cycle, int *cs_pulse)
  154. {
  155. *setup = (*setup & 0x1f) | ((*setup & 0x80) >> 2);
  156. *pulse = (*pulse & 0x3f) | ((*pulse & 0x100) >> 2);
  157. *cycle = (*cycle & 0x7f) | ((*cycle & 0x300) >> 1);
  158. *cs_pulse = (*cs_pulse & 0x3f) | ((*cs_pulse & 0x100) >> 2);
  159. }
  160. static unsigned long calc_mck_cycles(unsigned long ns, unsigned long mck_hz)
  161. {
  162. unsigned long mul;
  163. /*
  164. * cycles = x [nsec] * f [Hz] / 10^9 [ns in sec] =
  165. * x * (f / 1_000_000_000) =
  166. * x * ((f * 65536) / 1_000_000_000) / 65536 =
  167. * x * (((f / 10_000) * 65536) / 100_000) / 65536 =
  168. */
  169. mul = (mck_hz / 10000) << 16;
  170. mul /= 100000;
  171. return (ns * mul + 65536) >> 16; /* rounding */
  172. }
  173. /**
  174. * set_smc_timing - SMC timings setup.
  175. * @dev: device
  176. * @info: AT91 IDE info
  177. * @ata: ATA timings
  178. *
  179. * Its assumed that write timings are same as read timings,
  180. * cs_setup = 0 and cs_pulse = cycle.
  181. */
  182. static void set_smc_timing(struct device *dev, struct ata_device *adev,
  183. struct at91_ide_info *info, const struct ata_timing *ata)
  184. {
  185. int ret = 0;
  186. int use_iordy;
  187. unsigned int t6z; /* data tristate time in ns */
  188. unsigned int cycle; /* SMC Cycle width in MCK ticks */
  189. unsigned int setup; /* SMC Setup width in MCK ticks */
  190. unsigned int pulse; /* CFIOR and CFIOW pulse width in MCK ticks */
  191. unsigned int cs_setup = 0;/* CS4 or CS5 setup width in MCK ticks */
  192. unsigned int cs_pulse; /* CS4 or CS5 pulse width in MCK ticks*/
  193. unsigned int tdf_cycles; /* SMC TDF MCK ticks */
  194. unsigned long mck_hz; /* MCK frequency in Hz */
  195. t6z = (ata->mode < XFER_PIO_5) ? 30 : 20;
  196. mck_hz = clk_get_rate(info->mck);
  197. cycle = calc_mck_cycles(ata->cyc8b, mck_hz);
  198. setup = calc_mck_cycles(ata->setup, mck_hz);
  199. pulse = calc_mck_cycles(ata->act8b, mck_hz);
  200. tdf_cycles = calc_mck_cycles(t6z, mck_hz);
  201. do {
  202. ret = calc_smc_vals(dev, &setup, &pulse, &cycle, &cs_pulse);
  203. } while (ret == -ER_SMC_RECALC);
  204. if (ret == -ER_SMC_CALC)
  205. dev_err(dev, "Interface may not operate correctly\n");
  206. dev_dbg(dev, "SMC Setup=%u, Pulse=%u, Cycle=%u, CS Pulse=%u\n",
  207. setup, pulse, cycle, cs_pulse);
  208. to_smc_format(&setup, &pulse, &cycle, &cs_pulse);
  209. /* disable or enable waiting for IORDY signal */
  210. use_iordy = ata_pio_need_iordy(adev);
  211. if (use_iordy)
  212. info->mode |= AT91_SMC_EXNWMODE_READY;
  213. if (tdf_cycles > 15) {
  214. tdf_cycles = 15;
  215. dev_warn(dev, "maximal SMC TDF Cycles value\n");
  216. }
  217. dev_dbg(dev, "Use IORDY=%u, TDF Cycles=%u\n", use_iordy, tdf_cycles);
  218. info->mode |= AT91_SMC_TDF_(tdf_cycles);
  219. /* write SMC Setup Register */
  220. at91_sys_write(AT91_SMC_SETUP(info->cs),
  221. AT91_SMC_NWESETUP_(setup) |
  222. AT91_SMC_NRDSETUP_(setup) |
  223. AT91_SMC_NCS_WRSETUP_(cs_setup) |
  224. AT91_SMC_NCS_RDSETUP_(cs_setup));
  225. /* write SMC Pulse Register */
  226. at91_sys_write(AT91_SMC_PULSE(info->cs),
  227. AT91_SMC_NWEPULSE_(pulse) |
  228. AT91_SMC_NRDPULSE_(pulse) |
  229. AT91_SMC_NCS_WRPULSE_(cs_pulse) |
  230. AT91_SMC_NCS_RDPULSE_(cs_pulse));
  231. /* write SMC Cycle Register */
  232. at91_sys_write(AT91_SMC_CYCLE(info->cs),
  233. AT91_SMC_NWECYCLE_(cycle) |
  234. AT91_SMC_NRDCYCLE_(cycle));
  235. /* write SMC Mode Register*/
  236. at91_sys_write(AT91_SMC_MODE(info->cs), info->mode);
  237. }
  238. static void pata_at91_set_piomode(struct ata_port *ap, struct ata_device *adev)
  239. {
  240. struct at91_ide_info *info = ap->host->private_data;
  241. struct ata_timing timing;
  242. int ret;
  243. /* Compute ATA timing and set it to SMC */
  244. ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0);
  245. if (ret) {
  246. dev_warn(ap->dev, "Failed to compute ATA timing %d, "
  247. "set PIO_0 timing\n", ret);
  248. timing = *ata_timing_find_mode(XFER_PIO_0);
  249. }
  250. set_smc_timing(ap->dev, adev, info, &timing);
  251. }
  252. static unsigned int pata_at91_data_xfer_noirq(struct ata_device *dev,
  253. unsigned char *buf, unsigned int buflen, int rw)
  254. {
  255. struct at91_ide_info *info = dev->link->ap->host->private_data;
  256. unsigned int consumed;
  257. unsigned long flags;
  258. unsigned int mode;
  259. local_irq_save(flags);
  260. mode = at91_sys_read(AT91_SMC_MODE(info->cs));
  261. /* set 16bit mode before writing data */
  262. at91_sys_write(AT91_SMC_MODE(info->cs),
  263. (mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_16);
  264. consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
  265. /* restore 8bit mode after data is written */
  266. at91_sys_write(AT91_SMC_MODE(info->cs),
  267. (mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_8);
  268. local_irq_restore(flags);
  269. return consumed;
  270. }
  271. static struct scsi_host_template pata_at91_sht = {
  272. ATA_PIO_SHT(DRV_NAME),
  273. };
  274. static struct ata_port_operations pata_at91_port_ops = {
  275. .inherits = &ata_sff_port_ops,
  276. .sff_data_xfer = pata_at91_data_xfer_noirq,
  277. .set_piomode = pata_at91_set_piomode,
  278. .cable_detect = ata_cable_40wire,
  279. };
  280. static int __devinit pata_at91_probe(struct platform_device *pdev)
  281. {
  282. struct at91_cf_data *board = pdev->dev.platform_data;
  283. struct device *dev = &pdev->dev;
  284. struct at91_ide_info *info;
  285. struct resource *mem_res;
  286. struct ata_host *host;
  287. struct ata_port *ap;
  288. int irq_flags = 0;
  289. int irq = 0;
  290. int ret;
  291. /* get platform resources: IO/CTL memories and irq/rst pins */
  292. if (pdev->num_resources != 1) {
  293. dev_err(&pdev->dev, "invalid number of resources\n");
  294. return -EINVAL;
  295. }
  296. mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  297. if (!mem_res) {
  298. dev_err(dev, "failed to get mem resource\n");
  299. return -EINVAL;
  300. }
  301. irq = board->irq_pin;
  302. /* init ata host */
  303. host = ata_host_alloc(dev, 1);
  304. if (!host)
  305. return -ENOMEM;
  306. ap = host->ports[0];
  307. ap->ops = &pata_at91_port_ops;
  308. ap->flags |= ATA_FLAG_SLAVE_POSS;
  309. ap->pio_mask = ATA_PIO4;
  310. if (!irq) {
  311. ap->flags |= ATA_FLAG_PIO_POLLING;
  312. ata_port_desc(ap, "no IRQ, using PIO polling");
  313. }
  314. info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
  315. if (!info) {
  316. dev_err(dev, "failed to allocate memory for private data\n");
  317. return -ENOMEM;
  318. }
  319. info->mck = clk_get(NULL, "mck");
  320. if (IS_ERR(info->mck)) {
  321. dev_err(dev, "failed to get access to mck clock\n");
  322. return -ENODEV;
  323. }
  324. info->cs = board->chipselect;
  325. info->mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  326. AT91_SMC_EXNWMODE_READY | AT91_SMC_BAT_SELECT |
  327. AT91_SMC_DBW_8 | AT91_SMC_TDF_(0);
  328. info->ide_addr = devm_ioremap(dev,
  329. mem_res->start + CF_IDE_OFFSET, CF_IDE_RES_SIZE);
  330. if (!info->ide_addr) {
  331. dev_err(dev, "failed to map IO base\n");
  332. ret = -ENOMEM;
  333. goto err_put;
  334. }
  335. info->alt_addr = devm_ioremap(dev,
  336. mem_res->start + CF_ALT_IDE_OFFSET, CF_IDE_RES_SIZE);
  337. if (!info->alt_addr) {
  338. dev_err(dev, "failed to map CTL base\n");
  339. ret = -ENOMEM;
  340. goto err_put;
  341. }
  342. ap->ioaddr.cmd_addr = info->ide_addr;
  343. ap->ioaddr.ctl_addr = info->alt_addr + 0x06;
  344. ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
  345. ata_sff_std_ports(&ap->ioaddr);
  346. ata_port_desc(ap, "mmio cmd 0x%llx ctl 0x%llx",
  347. (unsigned long long)mem_res->start + CF_IDE_OFFSET,
  348. (unsigned long long)mem_res->start + CF_ALT_IDE_OFFSET);
  349. host->private_data = info;
  350. return ata_host_activate(host, irq ? gpio_to_irq(irq) : 0,
  351. irq ? ata_sff_interrupt : NULL,
  352. irq_flags, &pata_at91_sht);
  353. err_put:
  354. clk_put(info->mck);
  355. return ret;
  356. }
  357. static int __devexit pata_at91_remove(struct platform_device *pdev)
  358. {
  359. struct ata_host *host = dev_get_drvdata(&pdev->dev);
  360. struct at91_ide_info *info;
  361. if (!host)
  362. return 0;
  363. info = host->private_data;
  364. ata_host_detach(host);
  365. if (!info)
  366. return 0;
  367. clk_put(info->mck);
  368. return 0;
  369. }
  370. static struct platform_driver pata_at91_driver = {
  371. .probe = pata_at91_probe,
  372. .remove = __devexit_p(pata_at91_remove),
  373. .driver = {
  374. .name = DRV_NAME,
  375. .owner = THIS_MODULE,
  376. },
  377. };
  378. static int __init pata_at91_init(void)
  379. {
  380. return platform_driver_register(&pata_at91_driver);
  381. }
  382. static void __exit pata_at91_exit(void)
  383. {
  384. platform_driver_unregister(&pata_at91_driver);
  385. }
  386. module_init(pata_at91_init);
  387. module_exit(pata_at91_exit);
  388. MODULE_LICENSE("GPL");
  389. MODULE_DESCRIPTION("Driver for CF in True IDE mode on AT91SAM9260 SoC");
  390. MODULE_AUTHOR("Matyukevich Sergey");
  391. MODULE_VERSION(DRV_VERSION);