tvafe.c 37 KB

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  1. /*
  2. * TVAFE char device driver.
  3. *
  4. * Copyright (c) 2010 Bo Yang <bo.yang@amlogic.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the smems of the GNU General Public License as published by
  8. * the Free Software Foundation; version 2 of the License.
  9. */
  10. /* Standard Linux headers */
  11. #include <linux/types.h>
  12. #include <linux/errno.h>
  13. #include <linux/init.h>
  14. #include <linux/module.h>
  15. #include <linux/kernel.h>
  16. #include <linux/slab.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/fs.h>
  19. #include <linux/device.h>
  20. #include <linux/cdev.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/errno.h>
  24. #include <asm/uaccess.h>
  25. #include <linux/mutex.h>
  26. /* Amlogic headers */
  27. #include <linux/amports/canvas.h>
  28. #include <mach/am_regs.h>
  29. #include <linux/amports/vframe.h>
  30. /* Local include */
  31. #include "tvin_global.h"
  32. #include "tvin_frontend.h"
  33. #include "tvafe_regs.h"
  34. #include "tvafe.h" /* For user used */
  35. #include "tvafe_general.h" /* For Kernel used only */
  36. #include "tvafe_adc.h" /* For Kernel used only */
  37. #include "tvafe_cvd.h" /* For Kernel used only */
  38. #define TVAFE_NAME "tvafe"
  39. #define TVAFE_DRIVER_NAME "tvafe"
  40. #define TVAFE_MODULE_NAME "tvafe"
  41. #define TVAFE_DEVICE_NAME "tvafe"
  42. #define TVAFE_CLASS_NAME "tvafe"
  43. #define TVAFE_COUNT 1
  44. static dev_t tvafe_devno;
  45. static struct class *tvafe_clsp;
  46. /* used to set the flag of tvafe_dev_s */
  47. #define TVAFE_FLAG_DEV_OPENED 0x00000010
  48. #define TVAFE_FLAG_DEV_STARTED 0x00000020
  49. typedef struct tvafe_dev_s {
  50. int index;
  51. struct cdev cdev;
  52. struct timer_list timer;
  53. struct tvafe_info_s tvafe_info;
  54. tvin_frontend_t frontend;
  55. unsigned int flag;
  56. struct mutex afe_mutex;
  57. } tvafe_dev_t;
  58. #define TVAFE_TIMER_INTERVAL (HZ/100) //10ms, #define HZ 100
  59. #define TVAFE_ADC_CONFIGURE_INIT 1
  60. #define TVAFE_ADC_CONFIGURE_NORMAL 1|(1<<POWERDOWNZ_BIT)|(1<<RSTDIGZ_BIT) // 7
  61. #define TVAFE_ADC_CONFIGURE_RESET_ON 1|(1<<POWERDOWNZ_BIT)
  62. static struct tvafe_dev_s *tvafe_devp[TVAFE_COUNT];
  63. static void tvafe_vga_pinmux_enable(void)
  64. {
  65. // diable TCON
  66. //WRITE_CBUS_REG_BITS(PERIPHS_PIN_MUX_7, 0, 1, 1);
  67. // diable DVIN
  68. WRITE_CBUS_REG_BITS(PERIPHS_PIN_MUX_6, 0, 27, 1);
  69. // HS0
  70. WRITE_CBUS_REG_BITS(PERIPHS_PIN_MUX_6, 1, 15, 1);
  71. // VS0
  72. WRITE_CBUS_REG_BITS(PERIPHS_PIN_MUX_6, 1, 14, 1);
  73. // DDC_SDA0
  74. //WRITE_CBUS_REG_BITS(PERIPHS_PIN_MUX_6, 1, 13, 1);
  75. // DDC_SCL0
  76. //WRITE_CBUS_REG_BITS(PERIPHS_PIN_MUX_6, 1, 12, 1);
  77. }
  78. static void tvafe_vga_pinmux_disable(void)
  79. {
  80. // HS0
  81. WRITE_CBUS_REG_BITS(PERIPHS_PIN_MUX_6, 0, 15, 1);
  82. // VS0
  83. WRITE_CBUS_REG_BITS(PERIPHS_PIN_MUX_6, 0, 14, 1);
  84. // DDC_SDA0
  85. //WRITE_CBUS_REG_BITS(PERIPHS_PIN_MUX_6, 0, 13, 1);
  86. // DDC_SCL0
  87. //WRITE_CBUS_REG_BITS(PERIPHS_PIN_MUX_6, 0, 12, 1);
  88. }
  89. void tvafe_timer_handler(unsigned long arg)
  90. {
  91. struct tvafe_dev_s *devp = (struct tvafe_dev_s *)arg;
  92. //int tmp_data;
  93. enum tvin_port_e port = devp->tvafe_info.param.port;
  94. if (((port >= TVIN_PORT_VGA0) && (port <= TVIN_PORT_VGA7)) &&
  95. (devp->tvafe_info.vga_auto_flag == 1))
  96. {
  97. tvafe_vga_auto_adjust_handler(&devp->tvafe_info);
  98. if ((devp->tvafe_info.cmd_status == TVAFE_CMD_STATUS_FAILED) ||
  99. (devp->tvafe_info.cmd_status == TVAFE_CMD_STATUS_SUCCESSFUL)
  100. )
  101. devp->tvafe_info.vga_auto_flag = 0;
  102. }
  103. devp->timer.expires = jiffies + TVAFE_TIMER_INTERVAL;
  104. add_timer(&devp->timer);
  105. }
  106. int tvafe_dec_support(struct tvin_frontend_s *fe, enum tvin_port_e port)
  107. {
  108. if ((port < TVIN_PORT_VGA0) || (port > TVIN_PORT_SVIDEO7))
  109. return -1;
  110. return 0;
  111. }
  112. void tvafe_dec_open(struct tvin_frontend_s *fe, enum tvin_port_e port)
  113. {
  114. struct tvafe_dev_s *devp = container_of(fe, struct tvafe_dev_s, frontend);
  115. struct tvin_parm_s *parm = &devp->tvafe_info.param;
  116. mutex_lock(&devp->afe_mutex);
  117. if (devp->flag & TVAFE_FLAG_DEV_OPENED)
  118. {
  119. pr_err("%s(%d), %s opened already\n", __func__,
  120. devp->index, tvin_port_str(port));
  121. mutex_unlock(&devp->afe_mutex);
  122. return ;
  123. }
  124. devp->tvafe_info.param.port = port;
  125. /* init variable */
  126. parm->info.fmt = TVIN_SIG_FMT_NULL;
  127. parm->info.status = TVIN_SIG_STATUS_NULL;
  128. devp->tvafe_info.last_fmt = TVIN_SIG_FMT_NULL; //reset last fmt after source switch
  129. devp->tvafe_info.adc_cal_val.reserved &= ~TVAFE_ADC_CAL_VALID;
  130. if (((parm->port >= TVIN_PORT_VGA0) &&
  131. (parm->port <= TVIN_PORT_VGA7)) ||
  132. ((parm->port >= TVIN_PORT_COMP0) &&
  133. (parm->port <= TVIN_PORT_COMP7)))
  134. {
  135. memset(&devp->tvafe_info.operand, 0, sizeof(struct tvafe_operand_s));
  136. }
  137. else if ((port >= TVIN_PORT_CVBS0) && (port <= TVIN_PORT_CVBS7))
  138. {
  139. devp->tvafe_info.cvd2_info.s_video = false;
  140. if (port != TVIN_PORT_CVBS0)
  141. devp->tvafe_info.cvd2_info.tuner = false;
  142. else
  143. devp->tvafe_info.cvd2_info.tuner = true;
  144. }
  145. else // S_VIDEO0
  146. {
  147. devp->tvafe_info.cvd2_info.s_video = true;
  148. devp->tvafe_info.cvd2_info.tuner = false;
  149. }
  150. devp->tvafe_info.vga_auto_flag = 0;
  151. /**enable tvafe clock**/
  152. tvafe_enable_module(true);
  153. switch(devp->tvafe_info.param.port)
  154. {
  155. case TVIN_PORT_VGA0:
  156. tvafe_vga_pinmux_enable();
  157. break;
  158. default:
  159. break;
  160. }
  161. if ((port >= TVIN_PORT_VGA0) && (port <= TVIN_PORT_VGA7))
  162. tvafe_set_vga_default(TVIN_SIG_FMT_VGA_1024X768P_60D004);
  163. else if ((port >= TVIN_PORT_COMP0) && (port <= TVIN_PORT_COMP7))
  164. tvafe_set_comp_default(TVIN_SIG_FMT_COMP_720P_59D940);
  165. else if ((port >= TVIN_PORT_CVBS0) && (port <= TVIN_PORT_SVIDEO7))
  166. {
  167. tvafe_cvd2_set_default(&devp->tvafe_info.cvd2_info);
  168. }
  169. tvafe_source_muxing(&devp->tvafe_info);
  170. /* timer */
  171. init_timer(&devp->timer);
  172. devp->timer.data = (ulong)devp;
  173. devp->timer.function = tvafe_timer_handler;
  174. devp->timer.expires = jiffies + (TVAFE_TIMER_INTERVAL);
  175. add_timer(&devp->timer);
  176. /* set the flag to enabble ioctl access */
  177. devp->flag |= TVAFE_FLAG_DEV_OPENED;
  178. pr_info("%s ok.\n", __func__);
  179. mutex_unlock(&devp->afe_mutex);
  180. }
  181. void tvafe_dec_start(struct tvin_frontend_s *fe, enum tvin_sig_fmt_e fmt)
  182. {
  183. struct tvafe_dev_s *devp = container_of(fe, struct tvafe_dev_s, frontend);
  184. struct tvin_parm_s *parm = &devp->tvafe_info.param;
  185. mutex_lock(&devp->afe_mutex);
  186. if(!(devp->flag & TVAFE_FLAG_DEV_OPENED))
  187. {
  188. pr_err("tvafe_dec_start(%d) decode havn't opened\n", devp->index);
  189. mutex_unlock(&devp->afe_mutex);
  190. return;
  191. }
  192. if (devp->flag & TVAFE_FLAG_DEV_STARTED)
  193. {
  194. pr_err("%s(%d), %s started already\n", __func__,
  195. devp->index, tvin_port_str(parm->port));
  196. mutex_unlock(&devp->afe_mutex);
  197. return;
  198. }
  199. parm->info.fmt = fmt;
  200. parm->info.status = TVIN_SIG_STATUS_STABLE;
  201. if ((parm->port >= TVIN_PORT_CVBS0) &&
  202. (parm->port <= TVIN_PORT_CVBS7))
  203. {
  204. #ifdef TVAFE_SET_CVBS_PGA_EN
  205. devp->tvafe_info.cvd2_info.dgain_cnt = 0;
  206. #endif
  207. #ifdef TVAFE_SET_CVBS_CDTO_EN
  208. devp->tvafe_info.cvd2_info.hcnt64_cnt = 0;
  209. #endif
  210. }
  211. if (((parm->port >= TVIN_PORT_VGA0) &&
  212. (parm->port <= TVIN_PORT_VGA7)) ||
  213. ((parm->port >= TVIN_PORT_COMP0) &&
  214. (parm->port <= TVIN_PORT_COMP7)))
  215. {
  216. memset(&devp->tvafe_info.operand, 0, sizeof(struct tvafe_operand_s));
  217. }
  218. tvafe_source_muxing(&devp->tvafe_info); // why again?
  219. devp->flag |= TVAFE_FLAG_DEV_STARTED;
  220. pr_info("%s ok.\n", __func__);
  221. mutex_unlock(&devp->afe_mutex);
  222. }
  223. void tvafe_dec_stop(struct tvin_frontend_s *fe, enum tvin_port_e port)
  224. {
  225. struct tvafe_dev_s *devp = container_of(fe, struct tvafe_dev_s, frontend);
  226. struct tvin_parm_s *parm = &devp->tvafe_info.param;
  227. mutex_lock(&devp->afe_mutex);
  228. if(!(devp->flag & TVAFE_FLAG_DEV_STARTED))
  229. {
  230. pr_err("tvafe_dec_stop(%d) decode havn't started\n", devp->index);
  231. mutex_unlock(&devp->afe_mutex);
  232. return;
  233. }
  234. #if 0
  235. if ((parm->port >= TVIN_PORT_CVBS0) &&
  236. (parm->port <= TVIN_PORT_SVIDEO7))
  237. tvafe_cvd2_try_format(&devp->tvafe_info.cvd2_info, TVIN_SIG_FMT_CVBS_PAL_I);
  238. #endif
  239. parm->info.fmt = TVIN_SIG_FMT_NULL;
  240. parm->info.status = TVIN_SIG_STATUS_NULL;
  241. devp->tvafe_info.last_fmt = TVIN_SIG_FMT_NULL; //reset last fmt after source switch
  242. devp->tvafe_info.adc_cal_val.reserved &= ~TVAFE_ADC_CAL_VALID;
  243. if (((parm->port >= TVIN_PORT_VGA0) &&
  244. (parm->port <= TVIN_PORT_VGA7)) ||
  245. ((parm->port >= TVIN_PORT_COMP0) &&
  246. (parm->port <= TVIN_PORT_COMP7)))
  247. {
  248. memset(&devp->tvafe_info.operand, 0, sizeof(struct tvafe_operand_s));
  249. }
  250. // tvafe_reset_module();
  251. tvafe_adc_digital_reset();
  252. // need to do ...
  253. #ifdef TVAFE_ADC_CVBS_CLAMP_SEQUENCE_EN
  254. /** write 7740 register for cvbs clamp **/
  255. if ((parm->port >= TVIN_PORT_CVBS0) &&
  256. (parm->port <= TVIN_PORT_SVIDEO7))
  257. {
  258. tvafe_cvd2_reset_pga(&devp->tvafe_info.cvd2_info);
  259. tvafe_adc_cvbs_clamp_sequence();
  260. }
  261. #endif
  262. devp->flag &= (~TVAFE_FLAG_DEV_STARTED);
  263. pr_info("%s ok.\n", __func__);
  264. mutex_unlock(&devp->afe_mutex);
  265. }
  266. // #define TVAFE_POWERDOWN_IN_IDLE
  267. void tvafe_dec_close(struct tvin_frontend_s *fe)
  268. {
  269. struct tvafe_dev_s *devp = container_of(fe, struct tvafe_dev_s, frontend);
  270. struct tvin_parm_s *parm = &devp->tvafe_info.param;
  271. mutex_lock(&devp->afe_mutex);
  272. if(!(devp->flag & TVAFE_FLAG_DEV_OPENED))
  273. {
  274. pr_err("tvafe_dec_close(%d) decode havn't opened\n", devp->index);
  275. mutex_unlock(&devp->afe_mutex);
  276. return;
  277. }
  278. del_timer_sync(&devp->timer);
  279. switch(parm->port)
  280. {
  281. case TVIN_PORT_VGA0:
  282. tvafe_vga_pinmux_disable();
  283. break;
  284. default:
  285. break;
  286. }
  287. #ifdef TVAFE_POWERDOWN_IN_IDLE
  288. /**disable tvafe clock**/
  289. tvafe_enable_module(false);
  290. #endif
  291. parm->info.fmt = TVIN_SIG_FMT_NULL;
  292. parm->info.status = TVIN_SIG_STATUS_NULL;
  293. devp->tvafe_info.last_fmt = TVIN_SIG_FMT_NULL; //reset last fmt after source switch
  294. devp->tvafe_info.adc_cal_val.reserved &= ~TVAFE_ADC_CAL_VALID;
  295. if (((parm->port >= TVIN_PORT_VGA0) &&
  296. (parm->port <= TVIN_PORT_VGA7)) ||
  297. ((parm->port >= TVIN_PORT_COMP0) &&
  298. (parm->port <= TVIN_PORT_COMP7)))
  299. {
  300. memset(&devp->tvafe_info.operand, 0, sizeof(struct tvafe_operand_s));
  301. }
  302. devp->flag &= (~TVAFE_FLAG_DEV_OPENED);
  303. pr_info("%s ok.\n", __func__);
  304. mutex_unlock(&devp->afe_mutex);
  305. }
  306. int tvafe_dec_isr(struct tvin_frontend_s *fe, unsigned int hcnt64)
  307. {
  308. struct tvafe_dev_s *devp = container_of(fe, struct tvafe_dev_s, frontend);
  309. struct tvin_parm_s *parm = &devp->tvafe_info.param;
  310. /* if there is any error or overflow, do some reset, then rerurn -1;*/
  311. if ((parm->info.status != TVIN_SIG_STATUS_STABLE) ||
  312. (parm->info.fmt == TVIN_SIG_FMT_NULL)) {
  313. return -1;
  314. }
  315. /* TVAFE CVD2 3D works abnormally => reset cvd2 */
  316. if ((parm->port >= TVIN_PORT_CVBS0) &&
  317. (parm->port <= TVIN_PORT_CVBS7))
  318. {
  319. tvafe_check_cvbs_3d_comb(&devp->tvafe_info.cvd2_info);
  320. }
  321. #ifdef TVAFE_SET_CVBS_PGA_EN
  322. if ((parm->port >= TVIN_PORT_CVBS0) &&
  323. (parm->port <= TVIN_PORT_SVIDEO7))
  324. {
  325. tvafe_set_cvbs_pga(&devp->tvafe_info.cvd2_info);
  326. }
  327. #endif
  328. #ifdef TVAFE_SET_CVBS_CDTO_EN
  329. if (parm->info.fmt == TVIN_SIG_FMT_CVBS_PAL_I)
  330. {
  331. tvafe_set_cvbs_cdto(&devp->tvafe_info.cvd2_info,hcnt64);
  332. }
  333. #endif
  334. //tvafe_adc_clamp_adjust(&devp->tvafe_info);
  335. tvafe_vga_vs_cnt();
  336. // fetch WSS data must get them during VBI
  337. tvafe_get_wss_data(&devp->tvafe_info.comp_wss);
  338. return 0;
  339. }
  340. static struct tvin_decoder_ops_s tvafe_dec_ops = {
  341. .support = tvafe_dec_support,
  342. .open = tvafe_dec_open,
  343. .start = tvafe_dec_start,
  344. .stop = tvafe_dec_stop,
  345. .close = tvafe_dec_close,
  346. .decode_isr = tvafe_dec_isr,
  347. };
  348. bool tvafe_is_nosig(struct tvin_frontend_s *fe)
  349. {
  350. bool ret = 0;
  351. /* Get the per-device structure that contains this frontend */
  352. struct tvafe_dev_s *devp = container_of(fe, struct tvafe_dev_s, frontend);
  353. struct tvin_parm_s *parm = &devp->tvafe_info.param;
  354. #ifdef LOG_ADC_CAL
  355. struct tvafe_operand_s *operand = &devp->tvafe_info.operand;
  356. struct tvafe_adc_cal_s *adc_cal = &devp->tvafe_info.adc_cal_val;
  357. #endif
  358. if ((parm->port >= TVIN_PORT_VGA0) &&
  359. (parm->port <= TVIN_PORT_COMP7))
  360. ret = tvafe_adc_no_sig();
  361. else if ((parm->port >= TVIN_PORT_CVBS0) &&
  362. (parm->port <= TVIN_PORT_SVIDEO7))
  363. {
  364. ret = tvafe_cvd2_no_sig(&devp->tvafe_info.cvd2_info);
  365. /* normal sigal & adc reg error, reload source mux */
  366. if (devp->tvafe_info.cvd2_info.adc_reload_en && !ret)
  367. {
  368. devp->tvafe_info.cvd2_info.adc_reload_en = false;
  369. tvafe_source_muxing(&devp->tvafe_info);
  370. }
  371. }
  372. #ifdef LOG_ADC_CAL
  373. if (operand->adj)
  374. {
  375. operand->adj = 0;
  376. pr_info("\nadc_clamp_adjust\n");
  377. pr_info("Data = %4d %4d %4d\n", operand->data0,
  378. operand->data1,
  379. operand->data2);
  380. pr_info("A_cl = %4d %4d %4d\n", (int)(adc_cal->a_analog_clamp),
  381. (int)(adc_cal->b_analog_clamp),
  382. (int)(adc_cal->c_analog_clamp));
  383. pr_info("A_gn = %4d %4d %4d\n", (int)(adc_cal->a_analog_gain),
  384. (int)(adc_cal->b_analog_gain),
  385. (int)(adc_cal->c_analog_gain));
  386. pr_info("D_gn = %4d %4d %4d\n", (int)(adc_cal->a_digital_gain),
  387. (int)(adc_cal->b_digital_gain),
  388. (int)(adc_cal->c_digital_gain));
  389. pr_info("D_o1 = %4d %4d %4d\n", ((int)(adc_cal->a_digital_offset1) << 21) >> 21,
  390. ((int)(adc_cal->b_digital_offset1) << 21) >> 21,
  391. ((int)(adc_cal->c_digital_offset1) << 21) >> 21);
  392. pr_info("D_o2 = %4d %4d %4d\n", ((int)(adc_cal->a_digital_offset2) << 21) >> 21,
  393. ((int)(adc_cal->b_digital_offset2) << 21) >> 21,
  394. ((int)(adc_cal->c_digital_offset2) << 21) >> 21);
  395. pr_info("\n");
  396. }
  397. #endif
  398. return ret;
  399. }
  400. bool tvafe_fmt_chg(struct tvin_frontend_s *fe)
  401. {
  402. bool ret = false;
  403. /* Get the per-device structure that contains this frontend */
  404. struct tvafe_dev_s *devp = container_of(fe, struct tvafe_dev_s, frontend);
  405. struct tvin_parm_s *parm = &devp->tvafe_info.param;
  406. if ((parm->port >= TVIN_PORT_VGA0) &&
  407. (parm->port <= TVIN_PORT_COMP7))
  408. ret = tvafe_adc_fmt_chg(&devp->tvafe_info);
  409. else if ((parm->port >= TVIN_PORT_CVBS0) &&
  410. (parm->port <= TVIN_PORT_SVIDEO7))
  411. ret = tvafe_cvd2_fmt_chg(&devp->tvafe_info.cvd2_info);
  412. return ret;
  413. }
  414. bool tvafe_pll_lock(struct tvin_frontend_s *fe)
  415. {
  416. bool ret = true;
  417. #if 0 //can not trust pll lock status
  418. /* Get the per-device structure that contains this frontend */
  419. struct tvafe_dev_s *devp = container_of(fe, struct tvafe_dev_s, frontend);
  420. struct tvin_parm_s *parm = &devp->tvafe_info.param;
  421. if ((parm->port >= TVIN_PORT_VGA0) &&
  422. (parm->port <= TVIN_PORT_COMP7))
  423. ret = tvafe_adc_get_pll_status();
  424. #endif
  425. return (ret);
  426. }
  427. enum tvin_sig_fmt_e tvafe_get_fmt(struct tvin_frontend_s *fe)
  428. {
  429. enum tvin_sig_fmt_e fmt = TVIN_SIG_FMT_NULL;
  430. /* Get the per-device structure that contains this frontend */
  431. struct tvafe_dev_s *devp = container_of(fe, struct tvafe_dev_s, frontend);
  432. struct tvin_parm_s *parm = &devp->tvafe_info.param;
  433. if ((parm->port >= TVIN_PORT_VGA0) &&
  434. (parm->port <= TVIN_PORT_COMP7))
  435. fmt = tvafe_adc_search_mode(parm->port);
  436. else if ((parm->port >= TVIN_PORT_CVBS0) &&
  437. (parm->port <= TVIN_PORT_SVIDEO7))
  438. fmt = tvafe_cvd2_get_format(&devp->tvafe_info.cvd2_info);
  439. parm->info.fmt = fmt;
  440. return fmt;
  441. }
  442. #ifdef TVAFE_SET_CVBS_MANUAL_FMT_POS
  443. enum tvin_cvbs_pos_ctl_e tvafe_set_cvbs_fmt_pos(struct tvin_frontend_s *fe)
  444. {
  445. /* Get the per-device structure that contains this frontend */
  446. struct tvafe_dev_s *devp = container_of(fe, struct tvafe_dev_s, frontend);
  447. struct tvafe_cvd2_info_s *cvd2_info = &devp->tvafe_info.cvd2_info;
  448. enum tvin_cvbs_pos_ctl_e cvbs_pos_ctl = TVIN_CVBS_POS_NULL;
  449. if (cvd2_info->manual_fmt == TVIN_SIG_FMT_CVBS_PAL_I)
  450. {
  451. if (!cvd2_info->data.line625) //wrong format, change video size
  452. {
  453. cvbs_pos_ctl = TVIN_CVBS_POS_P_TO_N;
  454. tvafe_cvd2_set_video_positon(cvd2_info, TVIN_SIG_FMT_CVBS_NTSC_M);
  455. }
  456. else //right format, reload video size
  457. {
  458. cvbs_pos_ctl = TVIN_CVBS_POS_P_TO_P;
  459. tvafe_cvd2_set_video_positon(cvd2_info, TVIN_SIG_FMT_CVBS_PAL_I);
  460. }
  461. }
  462. else if ((cvd2_info->manual_fmt == TVIN_SIG_FMT_CVBS_NTSC_M) )
  463. {
  464. if (cvd2_info->data.line625) //wrong format, change video size
  465. {
  466. cvbs_pos_ctl = TVIN_CVBS_POS_N_TO_P;
  467. tvafe_cvd2_set_video_positon(cvd2_info, TVIN_SIG_FMT_CVBS_PAL_I);
  468. }
  469. else //right format, reload video size
  470. {
  471. cvbs_pos_ctl = TVIN_CVBS_POS_N_TO_N;
  472. tvafe_cvd2_set_video_positon(cvd2_info, TVIN_SIG_FMT_CVBS_NTSC_M);
  473. }
  474. }
  475. else // reset default postion
  476. {
  477. tvafe_cvd2_set_video_positon(cvd2_info, cvd2_info->config_fmt);
  478. }
  479. return (cvbs_pos_ctl);
  480. }
  481. #endif
  482. void tvafe_get_sig_propery(struct tvin_frontend_s *fe, struct tvin_sig_property_s *prop)
  483. {
  484. struct tvafe_dev_s *devp = container_of(fe, struct tvafe_dev_s, frontend);
  485. struct tvin_parm_s *parm = &devp->tvafe_info.param;
  486. prop->trans_fmt = TVIN_TFMT_2D;
  487. if ((parm->port >= TVIN_PORT_VGA0) &&
  488. (parm->port <= TVIN_PORT_VGA7))
  489. prop->color_format = TVIN_RGB444;
  490. else
  491. prop->color_format = TVIN_YUV444;
  492. prop->aspect_ratio = TVIN_ASPECT_NULL;
  493. prop->pixel_repeat= 0;
  494. }
  495. void tvafe_vga_set_parm(struct tvafe_vga_parm_s *vga_parm, struct tvin_frontend_s *fe)
  496. {
  497. struct tvafe_dev_s *devp = container_of(fe, struct tvafe_dev_s, frontend);
  498. struct tvafe_info_s *info = &devp->tvafe_info;
  499. tvafe_adc_set_param(vga_parm, info);
  500. }
  501. void tvafe_vga_get_parm(struct tvafe_vga_parm_s *vga_parm, struct tvin_frontend_s *fe)
  502. {
  503. struct tvafe_dev_s *devp = container_of(fe, struct tvafe_dev_s, frontend);
  504. struct tvafe_vga_parm_s *parm = &devp->tvafe_info.vga_parm;
  505. vga_parm->clk_step = parm->clk_step;
  506. vga_parm->phase = parm->phase;
  507. vga_parm->hpos_step = parm->hpos_step;
  508. vga_parm->vpos_step = parm->vpos_step;
  509. vga_parm->vga_in_clean = parm->vga_in_clean;
  510. }
  511. void tvafe_adc_monitor(enum tvin_sig_fmt_e fmt)
  512. {
  513. unsigned int x = tvin_fmt_tbl[fmt].hs_width + tvin_fmt_tbl[fmt].hs_bp + ((tvin_fmt_tbl[fmt].h_active + 1) >> 1);
  514. unsigned int y = tvin_fmt_tbl[fmt].vs_width + tvin_fmt_tbl[fmt].vs_bp - 10;
  515. WRITE_APB_REG(TVFE_ADC_READBACK_CTRL, (1 << 31) |
  516. (1 << 29) |
  517. (x << 16) |
  518. (1 << 13) |
  519. (y << 0));
  520. }
  521. void fmt_config(struct tvin_frontend_s *fe)
  522. {
  523. struct tvafe_dev_s *devp = container_of(fe, struct tvafe_dev_s, frontend);
  524. struct tvin_parm_s *parm = &devp->tvafe_info.param;
  525. /* do not need to configure format again if format remains unchanged */
  526. if (devp->tvafe_info.last_fmt == parm->info.fmt)
  527. return;
  528. if ((parm->port >= TVIN_PORT_COMP0) &&
  529. (parm->port <= TVIN_PORT_COMP7)) {
  530. tvafe_set_comp_default(parm->info.fmt);
  531. tvafe_source_muxing(&devp->tvafe_info);
  532. tvafe_set_cal_value(&devp->tvafe_info.adc_cal_val);
  533. tvafe_adc_monitor(parm->info.fmt);
  534. }
  535. if ((parm->port >= TVIN_PORT_VGA0) &&
  536. (parm->port <= TVIN_PORT_VGA7)) {
  537. tvafe_set_vga_default(parm->info.fmt);
  538. tvafe_source_muxing(&devp->tvafe_info);
  539. tvafe_set_cal_value(&devp->tvafe_info.adc_cal_val);
  540. tvafe_adc_monitor(parm->info.fmt);
  541. }
  542. devp->tvafe_info.last_fmt = parm->info.fmt;
  543. }
  544. bool adc_cal(struct tvin_frontend_s *fe)
  545. {
  546. struct tvafe_dev_s *devp = container_of(fe, struct tvafe_dev_s, frontend);
  547. return tvafe_adc_cal(&devp->tvafe_info, &devp->tvafe_info.operand);
  548. }
  549. bool tvafe_check_frame_skip(struct tvin_frontend_s *fe)
  550. {
  551. bool ret = false;
  552. struct tvafe_dev_s *devp = container_of(fe, struct tvafe_dev_s, frontend);
  553. struct tvin_parm_s *parm = &devp->tvafe_info.param;
  554. if (((parm->port >= TVIN_PORT_COMP0) && (parm->port <= TVIN_PORT_COMP7)) ||
  555. ((parm->port >= TVIN_PORT_VGA0) && (parm->port <= TVIN_PORT_VGA7))) {
  556. ret = tvafe_adc_check_frame_skip();
  557. }
  558. return ret;
  559. }
  560. static struct tvin_state_machine_ops_s tvafe_sm_ops = {
  561. .nosig = tvafe_is_nosig,
  562. .fmt_changed = tvafe_fmt_chg,
  563. .get_fmt = tvafe_get_fmt,
  564. .fmt_config = fmt_config,
  565. .adc_cal = adc_cal,
  566. .pll_lock = tvafe_pll_lock,
  567. .get_sig_propery = tvafe_get_sig_propery,
  568. #ifdef TVAFE_SET_CVBS_MANUAL_FMT_POS
  569. .set_cvbs_fmt_pos = tvafe_set_cvbs_fmt_pos,
  570. #endif
  571. .vga_set_param = tvafe_vga_set_parm,
  572. .vga_get_param = tvafe_vga_get_parm,
  573. .check_frame_skip = tvafe_check_frame_skip,
  574. };
  575. static int tvafe_open(struct inode *inode, struct file *file)
  576. {
  577. tvafe_dev_t *devp;
  578. /* Get the per-device structure that contains this cdev */
  579. devp = container_of(inode->i_cdev, tvafe_dev_t, cdev);
  580. file->private_data = devp;
  581. /* ... */
  582. pr_info("%s: open device \n", __FUNCTION__);
  583. return 0;
  584. }
  585. static int tvafe_release(struct inode *inode, struct file *file)
  586. {
  587. tvafe_dev_t *devp = file->private_data;
  588. file->private_data = NULL;
  589. /* Release some other fields */
  590. /* ... */
  591. pr_info("tvafe: device %d release ok.\n", devp->index);
  592. return 0;
  593. }
  594. static int tvafe_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
  595. {
  596. int ret = 0;
  597. struct tvafe_vga_edid_s edid;
  598. enum tvafe_cvbs_video_e cvbs_lock_status = TVAFE_CVBS_VIDEO_HV_UNLOCKED;
  599. void __user *argp = (void __user *)arg;
  600. struct tvafe_dev_s *devp;
  601. struct tvin_parm_s *parm;
  602. devp = container_of(inode->i_cdev, struct tvafe_dev_s, cdev);
  603. parm = &devp->tvafe_info.param;
  604. mutex_lock(&devp->afe_mutex);
  605. /* EDID command !!! */
  606. if (((cmd != TVIN_IOC_S_AFE_VGA_EDID) && (cmd != TVIN_IOC_G_AFE_VGA_EDID)) &&
  607. (!(devp->flag & TVAFE_FLAG_DEV_OPENED))
  608. )
  609. {
  610. pr_info("%s, tvafe device is disable, ignore the command %d\n", __func__, cmd);
  611. mutex_unlock(&devp->afe_mutex);
  612. return -EPERM;
  613. }
  614. switch (cmd)
  615. {
  616. case TVIN_IOC_S_AFE_ADC_CAL:
  617. if (copy_from_user(&devp->tvafe_info.adc_cal_val, argp, sizeof(struct tvafe_adc_cal_s)))
  618. {
  619. ret = -EFAULT;
  620. break;
  621. }
  622. devp->tvafe_info.adc_cal_val.reserved |= TVAFE_ADC_CAL_VALID;
  623. tvafe_vga_auto_adjust_disable(&devp->tvafe_info);
  624. if ((parm->port >= TVIN_PORT_COMP0) &&(parm->port <= TVIN_PORT_COMP7))
  625. {
  626. if((parm->info.fmt>=TVIN_SIG_FMT_COMP_1080P_23D976)&&(parm->info.fmt<=TVIN_SIG_FMT_COMP_1080P_60D000))
  627. devp->tvafe_info.adc_cal_val.a_analog_clamp += 7;
  628. else if((parm->info.fmt>=TVIN_SIG_FMT_COMP_1080I_47D952)&&(parm->info.fmt<=TVIN_SIG_FMT_COMP_1080I_60D000))
  629. devp->tvafe_info.adc_cal_val.a_analog_clamp += 6;
  630. else
  631. devp->tvafe_info.adc_cal_val.a_analog_clamp += 5;
  632. devp->tvafe_info.adc_cal_val.b_analog_clamp += 1;
  633. devp->tvafe_info.adc_cal_val.c_analog_clamp += 2;
  634. }
  635. else if((parm->port >= TVIN_PORT_VGA0) &&(parm->port <= TVIN_PORT_VGA7))
  636. {
  637. devp->tvafe_info.adc_cal_val.a_analog_clamp += 5;
  638. devp->tvafe_info.adc_cal_val.b_analog_clamp += 5;
  639. devp->tvafe_info.adc_cal_val.c_analog_clamp += 5;
  640. }
  641. //pr_info("\nNot allow to use TVIN_IOC_S_AFE_ADC_CAL command!!!\n\n");
  642. tvafe_set_cal_value(&devp->tvafe_info.adc_cal_val);
  643. #ifdef LOG_ADC_CAL
  644. pr_info("\nset_adc_cal\n");
  645. pr_info("A_cl = %4d %4d %4d\n", (int)(devp->tvafe_info.adc_cal_val.a_analog_clamp),
  646. (int)(devp->tvafe_info.adc_cal_val.b_analog_clamp),
  647. (int)(devp->tvafe_info.adc_cal_val.c_analog_clamp));
  648. pr_info("A_gn = %4d %4d %4d\n", (int)(devp->tvafe_info.adc_cal_val.a_analog_gain),
  649. (int)(devp->tvafe_info.adc_cal_val.b_analog_gain),
  650. (int)(devp->tvafe_info.adc_cal_val.c_analog_gain));
  651. pr_info("D_gn = %4d %4d %4d\n", (int)(devp->tvafe_info.adc_cal_val.a_digital_gain),
  652. (int)(devp->tvafe_info.adc_cal_val.b_digital_gain),
  653. (int)(devp->tvafe_info.adc_cal_val.c_digital_gain));
  654. pr_info("D_o1 = %4d %4d %4d\n", ((int)(devp->tvafe_info.adc_cal_val.a_digital_offset1) << 21) >> 21,
  655. ((int)(devp->tvafe_info.adc_cal_val.b_digital_offset1) << 21) >> 21,
  656. ((int)(devp->tvafe_info.adc_cal_val.c_digital_offset1) << 21) >> 21);
  657. pr_info("D_o2 = %4d %4d %4d\n", ((int)(devp->tvafe_info.adc_cal_val.a_digital_offset2) << 21) >> 21,
  658. ((int)(devp->tvafe_info.adc_cal_val.b_digital_offset2) << 21) >> 21,
  659. ((int)(devp->tvafe_info.adc_cal_val.c_digital_offset2) << 21) >> 21);
  660. pr_info("\n");
  661. #endif
  662. break;
  663. case TVIN_IOC_G_AFE_ADC_CAL:
  664. tvafe_get_cal_value(&devp->tvafe_info.adc_cal_val);
  665. #ifdef LOG_ADC_CAL
  666. pr_info("\nget_adc_cal\n");
  667. pr_info("A_cl = %4d %4d %4d\n", (int)(devp->tvafe_info.adc_cal_val.a_analog_clamp),
  668. (int)(devp->tvafe_info.adc_cal_val.b_analog_clamp),
  669. (int)(devp->tvafe_info.adc_cal_val.c_analog_clamp));
  670. pr_info("A_gn = %4d %4d %4d\n", (int)(devp->tvafe_info.adc_cal_val.a_analog_gain),
  671. (int)(devp->tvafe_info.adc_cal_val.b_analog_gain),
  672. (int)(devp->tvafe_info.adc_cal_val.c_analog_gain));
  673. pr_info("D_gn = %4d %4d %4d\n", (int)(devp->tvafe_info.adc_cal_val.a_digital_gain),
  674. (int)(devp->tvafe_info.adc_cal_val.b_digital_gain),
  675. (int)(devp->tvafe_info.adc_cal_val.c_digital_gain));
  676. pr_info("D_o1 = %4d %4d %4d\n", ((int)(devp->tvafe_info.adc_cal_val.a_digital_offset1) << 21) >> 21,
  677. ((int)(devp->tvafe_info.adc_cal_val.b_digital_offset1) << 21) >> 21,
  678. ((int)(devp->tvafe_info.adc_cal_val.c_digital_offset1) << 21) >> 21);
  679. pr_info("D_o2 = %4d %4d %4d\n", ((int)(devp->tvafe_info.adc_cal_val.a_digital_offset2) << 21) >> 21,
  680. ((int)(devp->tvafe_info.adc_cal_val.b_digital_offset2) << 21) >> 21,
  681. ((int)(devp->tvafe_info.adc_cal_val.c_digital_offset2) << 21) >> 21);
  682. pr_info("\n");
  683. #endif
  684. if (copy_to_user(argp, &devp->tvafe_info.adc_cal_val, sizeof(struct tvafe_adc_cal_s)))
  685. {
  686. ret = -EFAULT;
  687. break;
  688. }
  689. break;
  690. case TVIN_IOC_G_AFE_COMP_WSS:
  691. if (copy_to_user(argp, &devp->tvafe_info.comp_wss, sizeof(struct tvafe_comp_wss_s)))
  692. {
  693. ret = -EFAULT;
  694. break;
  695. }
  696. break;
  697. case TVIN_IOC_S_AFE_VGA_EDID:
  698. if (copy_from_user(&edid, argp, sizeof(struct tvafe_vga_edid_s)))
  699. {
  700. ret = -EFAULT;
  701. break;
  702. }
  703. tvafe_vga_set_edid(&edid);
  704. break;
  705. case TVIN_IOC_G_AFE_VGA_EDID:
  706. tvafe_vga_get_edid(&edid);
  707. if (copy_to_user(argp, &edid, sizeof(struct tvafe_vga_edid_s)))
  708. {
  709. ret = -EFAULT;
  710. break;
  711. }
  712. break;
  713. case TVIN_IOC_S_AFE_VGA_PARM:
  714. {
  715. if (copy_from_user(&devp->tvafe_info.vga_parm, argp, sizeof(struct tvafe_vga_parm_s)))
  716. {
  717. ret = -EFAULT;
  718. break;
  719. }
  720. tvafe_vga_auto_adjust_disable(&devp->tvafe_info);
  721. //tvafe_adc_set_param(&devp->tvafe_info.vga_parm, &devp->tvafe_info);
  722. break;
  723. }
  724. case TVIN_IOC_G_AFE_VGA_PARM:
  725. {
  726. struct tvafe_vga_parm_s vga_parm = {0, 0, 0, 0, 0};
  727. tvafe_adc_get_param(&vga_parm, &devp->tvafe_info);
  728. if (copy_to_user(argp, &vga_parm, sizeof(struct tvafe_vga_parm_s)))
  729. {
  730. ret = -EFAULT;
  731. break;
  732. }
  733. break;
  734. }
  735. case TVIN_IOC_S_AFE_VGA_AUTO:
  736. ret = tvafe_vga_auto_adjust_enable(&devp->tvafe_info);
  737. break;
  738. case TVIN_IOC_G_AFE_CMD_STATUS:
  739. if (copy_to_user(argp, &devp->tvafe_info.cmd_status, sizeof(enum tvafe_cmd_status_e)))
  740. {
  741. ret = -EFAULT;
  742. break;
  743. }
  744. if ((devp->tvafe_info.cmd_status == TVAFE_CMD_STATUS_SUCCESSFUL)
  745. || (devp->tvafe_info.cmd_status == TVAFE_CMD_STATUS_FAILED)
  746. || (devp->tvafe_info.cmd_status == TVAFE_CMD_STATUS_TERMINATED))
  747. {
  748. devp->tvafe_info.cmd_status = TVAFE_CMD_STATUS_IDLE;
  749. }
  750. break;
  751. case TVIN_IOC_G_AFE_CVBS_LOCK:
  752. if (!devp->tvafe_info.cvd2_info.data.h_lock && !devp->tvafe_info.cvd2_info.data.v_lock)
  753. cvbs_lock_status = TVAFE_CVBS_VIDEO_HV_UNLOCKED;
  754. else if (devp->tvafe_info.cvd2_info.data.h_lock)
  755. cvbs_lock_status = TVAFE_CVBS_VIDEO_H_LOCKED;
  756. else if (devp->tvafe_info.cvd2_info.data.v_lock)
  757. cvbs_lock_status = TVAFE_CVBS_VIDEO_V_LOCKED;
  758. else if (devp->tvafe_info.cvd2_info.data.h_lock && devp->tvafe_info.cvd2_info.data.v_lock)
  759. cvbs_lock_status = TVAFE_CVBS_VIDEO_HV_LOCKED;
  760. if (copy_to_user(argp, &cvbs_lock_status, sizeof(int)))
  761. {
  762. ret = -EFAULT;
  763. break;
  764. }
  765. break;
  766. case TVIN_IOC_S_AFE_CVBS_STD:
  767. {
  768. enum tvin_sig_fmt_e fmt = TVIN_SIG_FMT_NULL;
  769. if (copy_from_user(&fmt, argp, sizeof(enum tvin_sig_fmt_e))) {
  770. ret = -EFAULT;
  771. break;
  772. }
  773. devp->tvafe_info.cvd2_info.manual_fmt = fmt;
  774. pr_info("%s: ioctl set cvd2 manual fmt:%s. \n", __func__, tvin_sig_fmt_str(fmt));
  775. break;
  776. }
  777. default:
  778. ret = -ENOIOCTLCMD;
  779. break;
  780. }
  781. mutex_unlock(&devp->afe_mutex);
  782. return ret;
  783. }
  784. /* File operations structure. Defined in linux/fs.h */
  785. static struct file_operations tvafe_fops = {
  786. .owner = THIS_MODULE, /* Owner */
  787. .open = tvafe_open, /* Open method */
  788. .release = tvafe_release, /* Release method */
  789. .ioctl = tvafe_ioctl, /* Ioctl method */
  790. /* ... */
  791. };
  792. static int tvafe_probe(struct platform_device *pdev)
  793. {
  794. int ret;
  795. int i;
  796. struct device *devp;
  797. struct resource *res;
  798. //struct tvin_frontend_s * frontend;
  799. ret = alloc_chrdev_region(&tvafe_devno, 0, TVAFE_COUNT, TVAFE_NAME);
  800. if (ret < 0) {
  801. pr_err("tvafe: failed to allocate major number\n");
  802. return 0;
  803. }
  804. tvafe_clsp = class_create(THIS_MODULE, TVAFE_NAME);
  805. if (IS_ERR(tvafe_clsp))
  806. {
  807. pr_err("tvafe: can't get tvafe_clsp\n");
  808. unregister_chrdev_region(tvafe_devno, TVAFE_COUNT);
  809. return PTR_ERR(tvafe_clsp);
  810. }
  811. for (i = 0; i < TVAFE_COUNT; ++i)
  812. {
  813. /* allocate memory for the per-device structure */
  814. tvafe_devp[i] = kmalloc(sizeof(struct tvafe_dev_s), GFP_KERNEL);
  815. if (!tvafe_devp[i])
  816. {
  817. pr_err("tvafe: failed to allocate memory for tvafe device\n");
  818. return -ENOMEM;
  819. }
  820. memset(tvafe_devp[i], 0, sizeof(struct tvafe_dev_s));
  821. tvafe_devp[i]->index = i;
  822. /* connect the file operations with cdev */
  823. cdev_init(&tvafe_devp[i]->cdev, &tvafe_fops);
  824. tvafe_devp[i]->cdev.owner = THIS_MODULE;
  825. /* connect the major/minor number to the cdev */
  826. ret = cdev_add(&tvafe_devp[i]->cdev, (tvafe_devno + i), 1);
  827. if (ret) {
  828. pr_err("tvafe: failed to add device\n");
  829. /* @todo do with error */
  830. return ret;
  831. }
  832. /* create /dev nodes */
  833. devp = device_create(tvafe_clsp, NULL, MKDEV(MAJOR(tvafe_devno), i),
  834. NULL, "tvafe%d", i);
  835. if (IS_ERR(devp)) {
  836. pr_err("tvafe: failed to create device node\n");
  837. class_destroy(tvafe_clsp);
  838. /* @todo do with error */
  839. return PTR_ERR(devp);
  840. }
  841. /* get device memory */
  842. res = platform_get_resource(pdev, IORESOURCE_MEM, i);
  843. if (!res) {
  844. pr_err("tvafe: can't get memory resource\n");
  845. return -EFAULT;
  846. }
  847. tvafe_devp[i]->tvafe_info.cvd2_info.mem_addr = res->start;
  848. tvafe_devp[i]->tvafe_info.cvd2_info.mem_size = res->end - res->start + 1;
  849. pr_info(" tvafe[%d] cvd memory addr is:0x%x, cvd mem_size is:0x%x . \n",i,
  850. tvafe_devp[i]->tvafe_info.cvd2_info.mem_addr,
  851. tvafe_devp[i]->tvafe_info.cvd2_info.mem_size);
  852. tvafe_devp[i]->tvafe_info.pinmux = pdev->dev.platform_data;
  853. if (!tvafe_devp[i]->tvafe_info.pinmux) {
  854. pr_err("tvafe: no platform data!\n");
  855. ret = -ENODEV;
  856. }
  857. /* frontend */
  858. tvin_frontend_init(&tvafe_devp[i]->frontend, &tvafe_dec_ops, &tvafe_sm_ops, i);
  859. sprintf(tvafe_devp[i]->frontend.name, "%s%d", TVAFE_NAME, i);
  860. tvin_reg_frontend(&tvafe_devp[i]->frontend);
  861. mutex_init(&tvafe_devp[i]->afe_mutex);
  862. /* set APB bus register accessing error exception */
  863. WRITE_APB_REG(TVFE_APB_ERR_CTRL_MUX1, 0x8fff8fff);
  864. WRITE_APB_REG(TVFE_APB_ERR_CTRL_MUX2, 0x00008fff);
  865. }
  866. pr_info("tvafe: driver probe ok\n");
  867. return 0;
  868. }
  869. static int tvafe_remove(struct platform_device *pdev)
  870. {
  871. int i = 0;
  872. for (i = 0; i < TVAFE_COUNT; ++i)
  873. {
  874. mutex_destroy(&tvafe_devp[i]->afe_mutex);
  875. tvin_unreg_frontend(&tvafe_devp[i]->frontend);
  876. device_destroy(tvafe_clsp, MKDEV(MAJOR(tvafe_devno), i));
  877. cdev_del(&tvafe_devp[i]->cdev);
  878. kfree(tvafe_devp[i]);
  879. }
  880. class_destroy(tvafe_clsp);
  881. unregister_chrdev_region(tvafe_devno, TVAFE_COUNT);
  882. pr_info("tvafe: driver removed ok.\n");
  883. return 0;
  884. }
  885. #ifdef CONFIG_PM
  886. static int tvafe_suspend(struct platform_device *pdev,pm_message_t state)
  887. {
  888. int i = 0;
  889. for (i = 0; i < TVAFE_COUNT; ++i)
  890. tvafe_devp[i]->flag &= (~TVAFE_FLAG_DEV_OPENED);
  891. tvafe_enable_module(false);
  892. pr_info("tvafe: suspend module\n");
  893. return 0;
  894. }
  895. static int tvafe_resume(struct platform_device *pdev)
  896. {
  897. pr_info("tvafe: resume module\n");
  898. return 0;
  899. }
  900. #endif
  901. static struct platform_driver tvafe_driver = {
  902. .probe = tvafe_probe,
  903. .remove = tvafe_remove,
  904. #ifdef CONFIG_PM
  905. .suspend = tvafe_suspend,
  906. .resume = tvafe_resume,
  907. #endif
  908. .driver = {
  909. .name = TVAFE_DRIVER_NAME,
  910. }
  911. };
  912. static int __init tvafe_init(void)
  913. {
  914. int ret = 0;
  915. ret = platform_driver_register(&tvafe_driver);
  916. if (ret != 0) {
  917. pr_err("failed to register tvafe module, error %d\n", ret);
  918. return -ENODEV;
  919. }
  920. return ret;
  921. }
  922. static void __exit tvafe_exit(void)
  923. {
  924. platform_driver_unregister(&tvafe_driver);
  925. }
  926. module_init(tvafe_init);
  927. module_exit(tvafe_exit);
  928. MODULE_DESCRIPTION("AMLOGIC TVAFE driver");
  929. MODULE_LICENSE("GPL");
  930. MODULE_AUTHOR("Xu Lin <lin.xu@amlogic.com>");