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cardreader
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xd
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xd_port.h

xd_port.h 8.3 KB
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  1. #ifndef _H_XD_PORT_COMMON
    2. 

  2. #define _H_XD_PORT_COMMON
    3. 

  3. 

  4. #include <asm/types.h>
    5. 

  5. #include <asm/io.h>
    6. 

  6. #include <asm/arch/am_regs.h>
    7. 

  7.     
    8. 

  8. #include <asm/drivers/cardreader/card_io.h>
    9. 

  9.     
    10. 

  10. //Following I/O configurations are just for default case if no any known PCB defined
    11. 

  11.     
    12. 

  12. #define XD_IO_EXTERNAL
    13. 

  13.     
    14. 

  14. //Port operation for XD BUS
    15. 

  15. //write it as such form that could be replaced by function later if needed
    16. 

  16.     
    17. 

  17. #ifdef XD_IO_EXTERNAL
    18. 

  18. 
extern unsigned XD_DAT_OUTPUT_EN_REG;
    19. 

  19. 
extern unsigned XD_DAT0_7_OUTPUT_EN_MASK;
    20. 

  20. 
extern unsigned XD_DAT_INPUT_REG;
    21. 

  21. 
extern unsigned XD_DAT_OUTPUT_REG;
    22. 

  22. 
extern unsigned XD_DAT0_7_INPUT_MASK;
    23. 

  23. 
extern unsigned XD_DAT0_7_OUTPUT_MASK;
    24. 

  24. 
extern unsigned XD_DAT_INPUT_OFFSET;
    25. 

  25. 
extern unsigned XD_DAT_OUTPUT_OFFSET;
    26. 

  26. 

extern unsigned XD_RB_OUTPUT_EN_REG;
    27. 

  27. 
extern unsigned XD_RB_OUTPUT_EN_MASK;
    28. 

  28. 
extern unsigned XD_RB_INPUT_REG;
    29. 

  29. 
extern unsigned XD_RB_INPUT_MASK;
    30. 

  30. 

extern unsigned XD_RE_OUTPUT_EN_REG;
    31. 

  31. 
extern unsigned XD_RE_OUTPUT_EN_MASK;
    32. 

  32. 
extern unsigned XD_RE_OUTPUT_REG;
    33. 

  33. 
extern unsigned XD_RE_OUTPUT_MASK;
    34. 

  34. 

extern unsigned XD_CE_OUTPUT_EN_REG;
    35. 

  35. 
extern unsigned XD_CE_OUTPUT_EN_MASK;
    36. 

  36. 
extern unsigned XD_CE_OUTPUT_REG;
    37. 

  37. 
extern unsigned XD_CE_OUTPUT_MASK;
    38. 

  38. 

extern unsigned XD_ALE_OUTPUT_EN_REG;
    39. 

  39. 
extern unsigned XD_ALE_OUTPUT_EN_MASK;
    40. 

  40. 
extern unsigned XD_ALE_OUTPUT_REG;
    41. 

  41. 
extern unsigned XD_ALE_OUTPUT_MASK;
    42. 

  42. 

extern unsigned XD_CLE_OUTPUT_EN_REG;
    43. 

  43. 
extern unsigned XD_CLE_OUTPUT_EN_MASK;
    44. 

  44. 
extern unsigned XD_CLE_OUTPUT_REG;
    45. 

  45. 
extern unsigned XD_CLE_OUTPUT_MASK;
    46. 

  46. 

extern unsigned XD_WE_OUTPUT_EN_REG;
    47. 

  47. 
extern unsigned XD_WE_OUTPUT_EN_MASK;
    48. 

  48. 
extern unsigned XD_WE_OUTPUT_REG;
    49. 

  49. 
extern unsigned XD_WE_OUTPUT_MASK;
    50. 

  50. 

extern unsigned XD_WP_OUTPUT_EN_REG;
    51. 

  51. 
extern unsigned XD_WP_OUTPUT_EN_MASK;
    52. 

  52. 
extern unsigned XD_WP_OUTPUT_REG;
    53. 

  53. 
extern unsigned XD_WP_OUTPUT_MASK;
    54. 

  54. 

extern unsigned XD_INS_OUTPUT_EN_REG;
    55. 

  55. 
extern unsigned XD_INS_OUTPUT_EN_MASK;
    56. 

  56. 
extern unsigned XD_INS_INPUT_REG;
    57. 

  57. 
extern unsigned XD_INS_INPUT_MASK;
    58. 

  58. 

extern unsigned XD_PWR_OUTPUT_EN_REG;
    59. 

  59. 
extern unsigned XD_PWR_OUTPUT_EN_MASK;
    60. 

  60. 
extern unsigned XD_PWR_OUTPUT_REG;
    61. 

  61. 
extern unsigned XD_PWR_OUTPUT_MASK;
    62. 

  62. 
extern unsigned XD_PWR_EN_LEVEL;
    63. 

  63. 

  64. #define XD_POWER_CONTROL
    65. 

  65. 
extern unsigned XD_WORK_MODE;
    66. 

  66. 

  67.     //extern void (*xd_power_register)(int power_on);
    68. 

  68.     //extern int (*xd_ins_register)(void);
    69. 

  69.     //extern void (*xd_io_release_register)(void);
    70. 

  70. 
void xd_gpio_enable(void);
    71. 

  71. 

  72. #else				//XD_IO_EXTERNAL
    73. 

  73.     
    74. 

  74. #define XD_DAT_OUTPUT_EN_REG			CARD_GPIO_ENABLE
    75. 

  75. #define XD_DAT0_7_OUTPUT_EN_MASK		PREG_IO_9_16_MASK
    76. 

  76. #define XD_DAT_INPUT_REG				CARD_GPIO_INPUT
    77. 

  77. #define XD_DAT_OUTPUT_REG				CARD_GPIO_OUTPUT
    78. 

  78. #define XD_DAT0_7_INPUT_MASK			PREG_IO_9_16_MASK
    79. 

  79. #define XD_DAT0_7_OUTPUT_MASK			PREG_IO_9_16_MASK
    80. 

  80. #define XD_DAT_INPUT_OFFSET				9
    81. 

  81. #define XD_DAT_OUTPUT_OFFSET			9
    82. 

  82.     
    83. 

  83. #define XD_RB_OUTPUT_EN_REG				CARD_GPIO_ENABLE
    84. 

  84. #define XD_RB_OUTPUT_EN_MASK			PREG_IO_6_MASK
    85. 

  85. #define XD_RB_INPUT_REG					CARD_GPIO_INPUT
    86. 

  86. #define XD_RB_INPUT_MASK				PREG_IO_6_MASK
    87. 

  87.     
    88. 

  88. #define XD_RE_OUTPUT_EN_REG				CARD_GPIO_ENABLE
    89. 

  89. #define XD_RE_OUTPUT_EN_MASK			PREG_IO_18_MASK
    90. 

  90. #define XD_RE_OUTPUT_REG				CARD_GPIO_OUTPUT
    91. 

  91. #define XD_RE_OUTPUT_MASK				PREG_IO_18_MASK
    92. 

  92.     
    93. 

  93. #define XD_CE_OUTPUT_EN_REG				CARD_GPIO_ENABLE
    94. 

  94. #define XD_CE_OUTPUT_EN_MASK			PREG_IO_17_MASK
    95. 

  95. #define XD_CE_OUTPUT_REG				CARD_GPIO_OUTPUT
    96. 

  96. #define XD_CE_OUTPUT_MASK				PREG_IO_17_MASK
    97. 

  97.     
    98. 

  98. #define XD_ALE_OUTPUT_EN_REG			CARD_GPIO_ENABLE
    99. 

  99. #define XD_ALE_OUTPUT_EN_MASK			PREG_IO_1_MASK
    100. 

  100. #define XD_ALE_OUTPUT_REG				CARD_GPIO_OUTPUT
    101. 

  101. #define XD_ALE_OUTPUT_MASK				PREG_IO_1_MASK
    102. 

  102.     
    103. 

  103. #define XD_CLE_OUTPUT_EN_REG			CARD_GPIO_ENABLE
    104. 

  104. #define XD_CLE_OUTPUT_EN_MASK			PREG_IO_2_MASK
    105. 

  105. #define XD_CLE_OUTPUT_REG				CARD_GPIO_OUTPUT
    106. 

  106. #define XD_CLE_OUTPUT_MASK				PREG_IO_2_MASK
    107. 

  107.     
    108. 

  108. #define XD_WE_OUTPUT_EN_REG				CARD_GPIO_ENABLE
    109. 

  109. #define XD_WE_OUTPUT_EN_MASK			PREG_IO_19_MASK
    110. 

  110. #define XD_WE_OUTPUT_REG				CARD_GPIO_OUTPUT
    111. 

  111. #define XD_WE_OUTPUT_MASK				PREG_IO_19_MASK
    112. 

  112.     
    113. 

  113. #define XD_WP_OUTPUT_EN_REG				CARD_GPIO_ENABLE
    114. 

  114. #define XD_WP_OUTPUT_EN_MASK			PREG_IO_22_MASK
    115. 

  115. #define XD_WP_OUTPUT_REG				CARD_GPIO_OUTPUT
    116. 

  116. #define XD_WP_OUTPUT_MASK				PREG_IO_22_MASK
    117. 

  117.     
    118. 

  118. #define XD_INS_OUTPUT_EN_REG			CARD_GPIO_ENABLE
    119. 

  119. #define XD_INS_OUTPUT_EN_MASK			PREG_IO_20_MASK
    120. 

  120. #define XD_INS_INPUT_REG				CARD_GPIO_INPUT
    121. 

  121. #define XD_INS_INPUT_MASK				PREG_IO_20_MASK
    122. 

  122.     
    123. 

  123. #define XD_PWR_OUTPUT_EN_REG			CARD_GPIO_ENABLE
    124. 

  124. #define XD_PWR_OUTPUT_EN_MASK			PREG_IO_23_MASK
    125. 

  125. #define XD_PWR_OUTPUT_REG				CARD_GPIO_OUTPUT
    126. 

  126. #define XD_PWR_OUTPUT_MASK				PREG_IO_23_MASK
    127. 

  127. #define XD_PWR_EN_LEVEL					0
    128. 

  128.     
    129. 

  129. #define XD_WORK_MODE				CARD_SW_MODE
    130. 

  130. #define xd_gpio_enable()				{CLEAR_PERIPHS_REG_BITS(PERIPHS_PIN_MUX_2, 0x3F);CLEAR_PERIPHS_REG_BITS(SDIO_MULT_CONFIG, (1));}
    131. 

  131.     
    132. 

  132. #endif				//XD_IO_EXTERNAL
    133. 

  133. 
extern int i_GPIO_timer;
    134. 

  134. 

  135. #define xd_set_dat0_7_input()				{(*(volatile unsigned *)XD_DAT_OUTPUT_EN_REG) |= XD_DAT0_7_OUTPUT_EN_MASK; for(i_GPIO_timer=0;i_GPIO_timer<15;i_GPIO_timer++);}
    136. 

  136. #define xd_set_dat0_7_output()				{(*(volatile unsigned *)XD_DAT_OUTPUT_EN_REG) &= (~XD_DAT0_7_OUTPUT_EN_MASK);}
    137. 

  137. #define xd_set_dat0_7_value(data)			{(*(volatile unsigned *)XD_DAT_OUTPUT_REG) = (((*(volatile unsigned *)XD_DAT_OUTPUT_REG) & (~XD_DAT0_7_OUTPUT_MASK)) | (data << XD_DAT_OUTPUT_OFFSET));}
    138. 

  138. #define xd_get_dat0_7_value()				(((*(volatile unsigned *)XD_DAT_INPUT_REG) & XD_DAT0_7_INPUT_MASK) >> XD_DAT_INPUT_OFFSET)
    139. 

  139.     
    140. 

  140. #define xd_set_rb_input()       			{(*(volatile unsigned *)XD_RB_OUTPUT_EN_REG) |= XD_RB_OUTPUT_EN_MASK; for(i_GPIO_timer=0;i_GPIO_timer<15;i_GPIO_timer++);}
    141. 

  141. #define xd_get_rb_value()       			((*(volatile unsigned *)XD_RB_INPUT_REG & XD_RB_INPUT_MASK)?1:0)
    142. 

  142.     
    143. 

  143. #define xd_set_re_output()					{(*(volatile unsigned *)XD_RE_OUTPUT_EN_REG) &= (~XD_RE_OUTPUT_EN_MASK);}
    144. 

  144. #define xd_set_re_high()        			{(*(volatile unsigned *)XD_RE_OUTPUT_REG) |= XD_RE_OUTPUT_MASK;}
    145. 

  145. #define xd_set_re_low()         			{(*(volatile unsigned *)XD_RE_OUTPUT_REG) &= (~XD_RE_OUTPUT_MASK);}
    146. 

  146.     
    147. 

  147. #define xd_set_ce_output()					{(*(volatile unsigned *)XD_CE_OUTPUT_EN_REG) &= (~XD_CE_OUTPUT_EN_MASK);}
    148. 

  148. #define xd_set_ce_high()        			{(*(volatile unsigned *)XD_CE_OUTPUT_REG) |= XD_CE_OUTPUT_MASK;}
    149. 

  149. #define xd_set_ce_low()         			{(*(volatile unsigned *)XD_CE_OUTPUT_REG) &= (~XD_CE_OUTPUT_MASK);}
    150. 

  150.     
    151. 

  151. #define xd_set_ale_output()					{(*(volatile unsigned *)XD_ALE_OUTPUT_EN_REG) &= (~XD_ALE_OUTPUT_EN_MASK);}
    152. 

  152. #define xd_set_ale_high()       			{(*(volatile unsigned *)XD_ALE_OUTPUT_REG) |= XD_ALE_OUTPUT_MASK;}
    153. 

  153. #define xd_set_ale_low()        			{(*(volatile unsigned *)XD_ALE_OUTPUT_REG) &= (~XD_ALE_OUTPUT_MASK);}
    154. 

  154.     
    155. 

  155. #define xd_set_cle_output()					{(*(volatile unsigned *)XD_CLE_OUTPUT_EN_REG) &= (~XD_CLE_OUTPUT_EN_MASK);}
    156. 

  156. #define xd_set_cle_high()       			{(*(volatile unsigned *)XD_CLE_OUTPUT_REG) |= XD_CLE_OUTPUT_MASK;}
    157. 

  157. #define xd_set_cle_low()        			{(*(volatile unsigned *)XD_CLE_OUTPUT_REG) &= (~XD_CLE_OUTPUT_MASK);}
    158. 

  158.     
    159. 

  159. #define xd_set_we_output()					{(*(volatile unsigned *)XD_WE_OUTPUT_EN_REG) &= (~XD_WE_OUTPUT_EN_MASK);}
    160. 

  160. #define xd_set_we_high()        			{(*(volatile unsigned *)XD_WE_OUTPUT_REG) |= XD_WE_OUTPUT_MASK;}
    161. 

  161. #define xd_set_we_low()         			{(*(volatile unsigned *)XD_WE_OUTPUT_REG) &= (~XD_WE_OUTPUT_MASK);}
    162. 

  162.     
    163. 

  163. #define xd_set_wp_output()      			{(*(volatile unsigned *)XD_WP_OUTPUT_EN_REG) &= (~XD_WP_OUTPUT_EN_MASK);}
    164. 

  164. #define xd_set_wp_high()        			{(*(volatile unsigned *)XD_WP_OUTPUT_REG) |= XD_WP_OUTPUT_MASK;}
    165. 

  165. #define xd_set_wp_low()         			{(*(volatile unsigned *)XD_WP_OUTPUT_REG) &= (~XD_WP_OUTPUT_MASK);}
    166. 

  166.     
    167. 

  167. #define	xd_set_ins_input()					{(*(volatile unsigned *)XD_INS_OUTPUT_EN_REG) |= XD_INS_OUTPUT_EN_MASK; for(i_GPIO_timer=0;i_GPIO_timer<15;i_GPIO_timer++);}
    168. 

  168. #define xd_get_ins_value()					(((*(volatile unsigned *)XD_INS_INPUT_REG) & XD_INS_INPUT_MASK)?1:0)
    169. 

  169.     
    170. 

  170. #define XD_POWER_CONTROL                	
    171. 

  171.     
    172. 

  172. #ifdef XD_POWER_CONTROL                 	
    173. 

  173. #define xd_set_enable()         		{(*(volatile unsigned *)XD_PWR_OUTPUT_EN_REG) &= (~XD_PWR_OUTPUT_EN_MASK); if(XD_PWR_EN_LEVEL){*(volatile unsigned *)XD_PWR_OUTPUT_REG |= XD_PWR_OUTPUT_MASK;} else {*(volatile unsigned *)XD_PWR_OUTPUT_REG &= ~XD_PWR_OUTPUT_MASK;}}
    174. 

  174. #define xd_set_disable()        		{(*(volatile unsigned *)XD_PWR_OUTPUT_EN_REG) &= (~XD_PWR_OUTPUT_EN_MASK); if(XD_PWR_EN_LEVEL){*(volatile unsigned *)XD_PWR_OUTPUT_REG &= ~XD_PWR_OUTPUT_MASK;} else {*(volatile unsigned *)XD_PWR_OUTPUT_REG |= XD_PWR_OUTPUT_MASK;}}
    175. 

  175. #endif				/* 
 */
    176. 

  176.     
    177. 

  177. #endif				//_H_XD_PORT_COMMON
    178. 

  178.